CN116663479A

CN116663479A - PCB-Package collaborative design method

Info

Publication number: CN116663479A
Application number: CN202310704292.6A
Authority: CN
Inventors: 刘辛酉; 吴声誉; 任建辉; 王战义; 赵晓健
Original assignee: Shanghai Hongkuai Technology Co ltd
Current assignee: Shanghai Hongkuai Technology Co ltd
Priority date: 2023-06-14
Filing date: 2023-06-14
Publication date: 2023-08-29

Abstract

The invention discloses a novel PCB-Package collaborative design method, which is to integrate a PCB and a Package design into one design, break through the tool bottleneck of unified design of the PCB and the Package, realize layering design of the PCB and provide a feasible scheme for the integrated design of multiple DIE SIP designs and the PCB. The invention mainly aims to solve the problem that the PCB and the packaging design cannot be effectively interacted in the traditional design flow, and improve the efficiency and the performance of the whole design.

Description

PCB-Package collaborative design method

Technical Field

The invention relates to the field of integrated circuit Package design, in particular to a PCB-Package collaborative design method.

Background

Conventional chip-package-system design (chip-package-system) is one way to drive the design in a single direction from top to bottom. In the design flow, chip design is performed first, packaging design is performed again, and finally system design is performed, wherein the system design is PCB design. These three design processes are typically independent of each other. Therefore, it is difficult to consider the bottleneck of the package design when performing system design, especially when performing IC I/O layout. Likewise, packaging is difficult to consider in terms of bottlenecks in PCB system design. Therefore, the PCB system design optimization result cannot be directly pushed to the package design, and then pushed to the chip design, so that the overall optimization is performed.

The problem with this traditional design approach is that the lack of overall collaborative optimization may result in the final design result not being well pursued for maximum performance and efficiency. Because each design stage is relatively independent in such a design flow, and lacks overall consideration and optimization of the overall system, it may cause some parts of the design to be bottlenecked in the overall system, limiting the overall system performance and efficiency.

In particular, in IC I/O layout, it is difficult to consider the bottleneck of package design, because package design and IC design are typically done by different teams, which lack efficient coordination and communication between the two teams. Likewise, the bottleneck difficulty of PCB system design is also difficult to consider in package design, as these two design phases are also often done separately by different teams. These problems all result in some aspects of the design not being optimally addressed, thereby limiting the overall system performance and efficiency.

Therefore, in the method of PCB-Package co-design, the following key issues need to be considered by the chip Package engineer:

1. how to implement a PCB layering design to achieve global optimization from global to local.

2. How to consider the Package bottleneck in the PCB design, thereby achieving overall optimization.

3. How to consider the bottleneck of the PCB system design in the Package design, thereby achieving overall optimization.

Disclosure of Invention

The invention aims to provide a PCB-Package collaborative design method, which solves the problems in the background technology, integrates the PCB design and the Package design in the traditional chip-Package-system design flow into one design, solves the problem that the design processes of the PCB, package, chip three in the existing design flow are mutually independent, opens up the tool bottleneck of unified design of the PCB and the Package, realizes the layering design of the PCB, and provides a feasible scheme for the integration design of multiple DIE SIP designs and the PCB.

In order to achieve the above purpose, the present invention provides the following technical solutions: a PCB-Package collaborative design method comprises the following steps:

step one: creating a PCB-Package co-design tool, the co-design tool having the following functions:

(1) Independent design files of the PCB and the Package can be read and analyzed so as to share data;

(2) The PCB-Package design file can be read and analyzed;

(3) The cooperation of the PCB and the Package design can be realized, so that a designer can simultaneously perform the PCB and the Package design without considering conflict and bottleneck between the PCB and the Package design;

(4) The whole design flow can be managed and optimized so as to obtain an optimal design scheme;

(5) Version management can be performed on the PCB and the Package design file so as to realize forward and backward compatibility of tool versions to engineering design files;

step two: creating a PCB-Package collaborative design file for fusing the processes of PCB and Package designs, wherein the file can be realized by a PCB-Package collaborative design tool, and when the file is created, the design processes of the PCB and the Package are required to be combined together so as to realize subsequent collaborative design;

step three: the PCB-Package collaborative design is realized, which comprises the following substeps;

(1) Opening a PCB-Package design file in a collaborative design tool;

(2) Matching adjustment and optimization are carried out on the PCB and Package designs so as to realize overall design optimization;

(3) Feeding back the results of the PCB and the Package design to a collaborative design tool so as to perform the next collaborative design;

(4) Repeating the steps until a design scheme with better effect is obtained, wherein the measure of the better scheme aims at reducing winding, shortening the total wiring distance, reducing the number of punched through holes and reducing the stacking number;

step four: generating a PCB-Package co-design file, which contains the overall design of the PCB and Package, and can be used directly for subsequent manufacturing and testing,

the method comprises the following substeps:

(1) The PCB-Package design result in the collaborative design tool is led out to be a PCB-Package collaborative design file and a factory production and processing file, wherein the PCB-Package collaborative design file comprises information such as connection among a chip, a Package and a PCB;

(2) Checking and verifying the exported file to ensure that the file can be used for subsequent manufacturing, testing and verification;

(3) The PCB-Package co-design file and the factory production processing file are delivered to the manufacturing and testing departments for subsequent manufacturing and testing work.

By adopting the technical scheme, a PCB-Package collaborative design module is added in the design flow, and the PCB design and the Package design are fused into one design to realize unified design so as to achieve the aim of integral optimization, and the PCB-Package collaborative design module comprises three sub-modules, namely a PCB hierarchical design module, a Package design module, a PCB and a Package combined design module, wherein the PCB hierarchical design module is mainly responsible for realizing the hierarchical design of the PCB, namely the lamination design, and the PCB design needs to be provided with lamination design so as to improve the wiring density of the PCB, for example, reduce the wiring length, improve the signal integrity and simplify the PCB design, so that good signals and power management are provided among all layers of the PCB; the Package design module is mainly responsible for realizing Package and pin layout of the Package so as to meet the requirements of chip and PCB design; the PCB and Package combined design module performs combined design on the design results of the PCB and Package, realizes data exchange and information sharing in the whole design flow, performs data exchange and information sharing in a memory through a tool, and adjusts the shared data so as to achieve the aim of integral optimization.

Preferably, the matching adjustment and the overall optimization in the third step are mainly realized in two aspects,

one is in the Package module, the main method is to move/adjust the I/O cells in the Package to take into account the effect on the Package Ball, reassign the Ball to take into account the chip interface, optimize die position, adjust Ball position, adjust finger position and direction, adjust Bump pad position and direction, adjust routing and bonding wire,

secondly, in the PCB module, the main method is to adjust the position and direction of the IC packaging module, adjust the lamination structure of the PCB, adjust the layout, routing, copper coating, punching and other contents of the peripheral circuit.

Preferably, the PCB design is also included: for PCB layout, copper-clad and routing, including definition of layer number, size, shape, and routing of signal lines, supply lines, and also including constraint and optimization of high-speed signals,

package design: for designing IC package, including definition of pin shape, arrangement, package size, and definition of position and size of Die, bump, finger, bond, etc. inside IC package, design function of high density package including BGA, QFN, etc.,

PCB-Package joint debugging: the method is used for matching and optimizing the design of the PCB and the Package, and can comprise simulation and verification of signal integrity and electrical performance, finding out a mismatch place and performing adjustment and correction.

Compared with the prior art, the invention has the beneficial effects that:

1. the performance and efficiency of the whole system are improved: according to the PCB-Package collaborative design method, the PCB and Package designs are integrated into one integral design, so that tools and data bottlenecks in the original independent design process are opened, the design of the whole system is fully considered and optimized, and the performance and efficiency of the whole system are improved;

2. realize the hierarchical design of PCB: the PCB-Package collaborative design method provided by the invention adopts the concept of layering design, and fuses different layering designs of the PCB together, so that the collaborative problem between the PCB and the Package design can be better solved, and a feasible scheme is provided for the multi-DIE SIP design and the fusion design of the PCB;

3. the design flow is simplified, and the design efficiency is improved: according to the PCB-Package collaborative design method, the PCB and Package designs are fused together, so that data conversion and communication barriers in the original independent design process are eliminated, the design flow is simplified, and the design efficiency and accuracy are improved;

4. design quality and reliability are improved: according to the PCB-Package collaborative design method, the design quality and the reliability of the whole system are improved by fusing the PCB design and the Package design. Meanwhile, the invention adopts the concept of layering design, so that the problem of coordination among different design layers can be better solved, and the design quality and reliability are further improved;

5. the design cycle and cost are reduced. The time for the IC products to be developed is shortened to a certain extent;

6. the IC company can conveniently manufacture a better chip template circuit;

7. global optimization from whole to local is realized, and the performance and reliability of the system are improved;

8. the PCB-Package collaborative design is realized, and the bottleneck problem in the prior art is solved;

the method can reduce the complexity of design, improve the design efficiency, and optimize the overall performance and reliability. In addition, the method can provide a feasible scheme for the multi-DIE SIP design and the fusion design of the PCB, and has wide application prospect.

Drawings

FIG. 1 is a flow chart of a PCB-Package co-design of an embodiment;

FIG. 2 is a schematic diagram of a hierarchical design of a PCB according to an embodiment;

FIG. 3-1 is a schematic diagram of a Package design according to an embodiment;

FIG. 3-2 is a schematic diagram of another view of a Package according to an embodiment;

FIG. 4-1 is a Chip design of an embodiment;

FIG. 4-2 is a Package design of an embodiment;

FIGS. 4-3 are system designs of embodiments;

FIGS. 4-4 are schematic diagrams of PCB-Package designs;

FIG. 5 is a flow chart of network relationship file import;

FIG. 6 is a flow chart of Package chip layout file import;

FIG. 7 is a schematic diagram of a PCB-Package file fusion process;

FIG. 8 is a first exemplary view of a Package chip layout file;

FIG. 9 is a schematic diagram of a second example of a Package chip layout file;

fig. 10 is a schematic diagram of a file sample of a PCB netlist.

Description of the embodiments

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In an embodiment of the present invention,

the PCB-Package collaborative design method, as shown in FIG. 1, FIG. 2, FIG. 3-1, FIG. 3-2, FIG. 4-1, FIG. 4-2, FIG. 4-3, FIG. 4-4, FIG. 5, FIG. 6, FIG. 7, FIG. 8, FIG. 9 and FIG. 10, comprises the following steps:

(2) The PCB-Package design file can be read and analyzed;

(4) The whole design flow can be managed and optimized so as to obtain a better design scheme;

(1) Opening a PCB-Package design file in a collaborative design tool;

(4) The steps are repeated until a design scheme with better effect is obtained, and the measure of the better scheme aims at reducing winding, shortening the total wiring distance, reducing the number of punched through holes and reducing the stacking number.

It is noted that the optimal protocol standard has no specific quantization value. The result value is also a fixed value without standard, and technicians intuitively judge the better value compared with the prior scheme;

the method comprises the following substeps:

As shown in fig. 1, three sub-modules of the PCB design module, the Package design module, the PCB and the Package joint design module cooperate with each other to complete the whole PCB-Package joint design process.

The importing the network relation file in fig. 1 specifically includes the following steps: as shown in fig. 5, the network relationship file is read, and the network relationship file in the disk is read by a program, as in fig. 10, for example.

Checking the correctness of the netlist file, wherein the netlist file has a certain format requirement. Checking its correctness.

If the prompt file is abnormal, if the netlist file is incorrect, an error prompt is reported and the current processing program is exited.

And analyzing the packaging objects, namely analyzing the packaging objects in the netlist file row by row, wherein the packaging objects comprise the names, the attributes and the bit numbers of the packaging objects, and storing the packaging objects in a memory container specified by a program.

And analyzing the network, analyzing the network in the netlist file row by row, and storing the network in a memory container specified by the program.

Analyzing the association of the network, analyzing the association relation between the network and the object in the netlist file, and storing the association relation into the corresponding memory container.

And loading the encapsulation library, retrieving the encapsulation library from the encapsulation library appointed by the program according to the encapsulation object, and loading the corresponding content (comprising the graphic element content and the attribute content) in the encapsulation library to the engineering object.

And generating a PCB engineering object, and converting all the contents into a data object in a program. And stored in the memory according to certain logic.

And generating PCB engineering data, and packaging the converted data object into the PCB engineering data for use in the subsequent steps. The PCB engineering data file may also be derived separately afterwards.

The Package chip layout file in fig. 1 specifically includes the following procedures: as shown in figure 6 of the drawings,

and reading the chip layout file in the disk file. See fig. 8 for a sample file.

And checking the correctness of the chip layout file, and checking whether the file content read in the last step meets the format requirement.

Prompting file abnormality, and if file input meeting format requirements is not met, reporting an error prompt and exiting the current processing program.

And analyzing the chip packaging object, and identifying the chip packaging object from the input content, wherein the chip packaging object comprises information such as size, unit, name, lamination, position, bonding pad and the like.

And analyzing the Ball/Pin object, and identifying the Ball/Pin object of the chip package from the input content, wherein the Ball/Pin object comprises a pad name, a coordinate position, application, voltage attributes and the like.

And analyzing the Die object, and analyzing the Die entity content, wherein the Die entity content comprises information such as names, bit numbers, lamination, sizes, positions, bonding pads and the like.

The Die stamp object is parsed, and stamp entity content including pad name, coordinate location, and usage and voltage attributes are identified from the input content.

And loading the Pad library, retrieving the Pad content from the Pad library appointed by the program according to the encapsulation object, and loading the corresponding content (comprising the graphic element content and the attribute content) in the Pad library to the engineering object.

And analyzing the Pad object, identifying the Pad entity object from the input content, and associating the Pad entity object with the Ball/pin and the stamp object while corresponding to the Pad content loaded in the Pad library.

And analyzing the network object, identifying all network name data in the input file, and identifying all object relations associated with the network. The data is stored in a memory area designated by the program.

And generating a PKG engineering object, and generating all the contents into a corresponding PKG engineering data object.

And generating PKG engineering data, and packaging the converted data object into PKG engineering data for use in subsequent steps. The PKG engineering data file may also be derived separately afterwards.

The PCB-Package file fusion process in FIG. 1 includes the following steps: as shown in fig. 8 and 9, the PCB engineering data, the network relationship file, import the final data content generated in the process.

PKG engineering data and Package chip layout files are imported into final data content generated in the process.

Network extraction, namely, respective network object content in the PCB engineering data and the PKG engineering data.

And (3) network mapping, wherein the two groups of network object contents extracted in the previous step are mapped, so that the corresponding networks generate a connection relation. And stores the connection relationship in a specific memory container for subsequent design.

The PCB design module corresponds to the PCB design module in the first drawing.

The Package design module corresponds to the Package design module in fig. 1.

The DIE design in fig. 1 mainly refers to DIE option, position layout, and leadframe design.

Design rules refer to rules management design, and the requirements of space rules, physical rules, electrical rules and the like of various objects in the design process need to be considered.

A stacked design refers to a design of how to stack in the case of multiple did's in a package.

The BUMP design refers to the type selection, layout design, shape design, material selection and other aspects of BUMP in the chip package.

Layout refers to how to consider how to determine the placement position and the placement mode of each object on the premise of meeting the requirements of the needed various objects in small enough space content in chip packaging.

Finger design refers to how the placement, shape, size, material, etc. of the Finger are considered in the package design.

The gold wire design refers to how to consider the information of the type selection, shape, size and the like of the gold wire in the package design.

The Ball/PAD design refers to how the number, spacing, location, shape, etc. of Ball/PADs on a substrate are considered in the package design.

Adding a PCB-Package collaborative design module in a design flow, wherein the module fuses the PCB design and the Package design into one design to realize unified design so as to achieve the aim of integral optimization; the Package design module is mainly responsible for realizing Package and pin layout of the Package so as to meet the requirements of chip and PCB design; the PCB and Package combined design module performs combined design on the design results of the PCB and Package, realizes data exchange and information sharing in the whole design flow, and performs data exchange and information sharing in a memory through a tool so as to achieve the purpose of overall optimization.

1) And the PCB and the packaging design are fused into a unified design platform tool, so that the cooperative optimization of the PCB and the packaging design is realized. Through the platform tool, the IC I/O layout can be optimized to meet the packaging requirement while the PCB system is designed in consideration of the packaging requirement.

Fusion refers to the design operation which is originally needed to be performed in two tools and is performed in one tool.

2) The layering design of the PCB is realized, and the PCB design layer and the Package design layer can better consider the interaction between the PCB and the Package.

3) A multiple DIE SIP design scheme is provided that combines multiple chips into a SIP module and matches it to a package. By this solution, the design and manufacturing process of the SIP module can be greatly simplified.

4) The method provides a feasible scheme for the fusion design of the PCB, and by fusing the PCB and the packaging design into one platform, the problem of collaborative design between the PCB and the packaging can be better considered, and the efficiency and the performance of the overall design are improved.

The matching adjustment and the overall optimization in the third step are mainly realized in two aspects,

The PCB design is also included: for PCB layout, copper-clad and routing, including definition of layer number, size, shape, and routing of signal lines, supply lines, and also including constraint and optimization of high-speed signals,

as shown in fig. 2, the PCB is divided into a plurality of layers, each having a different function, e.g., a signal layer, a power layer, a ground layer, a dielectric layer, etc.

as shown in fig. 3-1, the stacked structure in the chip Package is derived from: https:// en. Wikichip. Org/wiki/tsmc/cowos.

A new PCB-Package collaborative design method is that a PCB and a Package design are fused into one design, a tool bottleneck of unified design of the PCB and the Package is opened, layering design of the PCB is realized, and a feasible scheme is provided for the fusion design of a plurality of DIE SIP designs and the PCB. The invention mainly aims to solve the problem that the PCB and the packaging design cannot be effectively interacted in the traditional design flow, and improve the efficiency and the performance of the whole design.

The foregoing is only a preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art, who is within the scope of the present invention, should make equivalent substitutions or modifications according to the technical scheme of the present invention and the inventive concept thereof, and should be covered by the scope of the present invention.

Claims

1. A PCB-Package collaborative design method is characterized in that: the method comprises the following steps:

(2) The PCB-Package design file can be read and analyzed;

(1) Opening a PCB-Package design file in a collaborative design tool;

the method comprises the following substeps:

2. The PCB-Package co-design method of claim 1, wherein: the matching adjustment and the overall optimization in the third step are mainly realized in two aspects,

3. The PCB-Package co-design method of claim 1, wherein: the PCB design is also included: for PCB layout, copper-clad and routing, including definition of layer number, size, shape, and routing of signal lines, supply lines, and also including constraint and optimization of high-speed signals,