CN117917750A - Method for forming semiconductor structure - Google Patents

Abstract

A method of forming a semiconductor structure, comprising: providing a substrate; forming a first material layer on a substrate; forming a plurality of first mask structures on the first material layer; forming a patterned structure on the top surface and the side wall surface of part of the first mask structure, wherein the width of the patterned structure is larger than that of the first mask structure; etching the first material layer by taking the first mask structure and the patterned structure as masks to form a plurality of second mandrel structures; forming a second side wall structure on the side wall of each second mandrel structure; and removing the second mandrel structure after the second side wall structure is formed. The method for forming the semiconductor structure improves the size and the pattern flexibility of the semiconductor device.

Description

Method for forming semiconductor structure

Technical Field

The invention relates to the technical field of semiconductors, in particular to a method for forming a semiconductor structure.

Background

As semiconductor technology advances, the size of semiconductor devices continues to decrease. In the back-end process of integrated circuits, the size requirements for metal lines are also increased, so that it is the subject of extensive research to ensure high-quality, small-size metal lines by improving the process.

In the existing semiconductor manufacturing process of the process below 7nm, a Self-aligned quadruple pattern process (Self-Aligned Quadruple Patterning, SAQP) is an important means for manufacturing small-size metal wires. The process of the self-aligned quad pattern process includes: the first step, a first mandrel pattern is formed; forming a first side wall pattern on the side wall of the first mandrel pattern by deposition, and removing the first mandrel pattern; step three, transmitting the first side wall pattern, and forming a second mandrel pattern according to the first side wall pattern; and fourthly, forming a second side wall pattern on the side wall of the second mandrel pattern through deposition, and removing the second mandrel pattern, so that the final pattern pitch (pitch) is only one fourth of the initial pattern pitch, and the pattern size is greatly reduced.

However, in the prior art, in the metal lines formed by the self-aligned quad pattern process, the size of a portion of the metal lines is completely determined by the width of the first sidewall pattern, so that the flexibility of the size and the spacing of the metal lines is poor, and the diversity of the integrated circuit design is limited.

Disclosure of Invention

The invention solves the technical problem of providing a method for forming a semiconductor structure, which improves the size and the pattern flexibility of a semiconductor device.

In order to solve the technical problems, the technical scheme of the invention provides a method for forming a semiconductor structure, which comprises the steps of providing a substrate; forming a first material layer on a substrate; forming a plurality of first mask structures on the first material layer; forming a patterned structure on the top surface and the side wall surface of part of the first mask structure, wherein the width of the patterned structure is larger than that of the first mask structure; etching the first material layer by taking the first mask structure and the patterned structure as masks to form a plurality of second mandrel structures; forming a second side wall structure on the side wall of each second mandrel structure; and removing the second mandrel structure after the second side wall structure is formed.

Optionally, the length of the first mask structure is the same as the length of the patterned structure.

Optionally, the length of the first mask structure is a dimension of the first mask structure parallel to a first direction, the first direction is parallel to the surface of the substrate, and the length of the patterned structure is a dimension of the patterned structure parallel to the first direction.

Optionally, the length of the first mask structure is a dimension of the first mask structure parallel to a first direction, the first direction is parallel to the surface of the substrate, the width of the first mask structure is a dimension of the first mask structure perpendicular to the first direction, and the width of the patterned structure is a dimension of the patterned structure perpendicular to the first direction.

Optionally, the forming method of the patterned structure includes: forming an initial pattern material layer positioned on the first material layer and the first mask structure after forming the first mask structure; patterning the initial patterned material layer to form a patterned structure on a top surface and a sidewall surface of a portion of the first mask structure.

Optionally, the width of the patterned structure is greater than 12 nanometers.

Optionally, the distance between the patterned structure and the adjacent first mask structure is greater than or equal to 3 times of the width of the second side wall structure.

Optionally, the number of patterned structures is different from the number of first mask structures.

Optionally, a patterned structure is located on a surface of a first mask structure.

Optionally, the material of the patterned structure includes photoresist.

Optionally, the second mandrel structure includes: the first structure is formed by taking the patterned structure and a first mask structure covered by the patterned structure as masks to etch the first material layer; and the second structure is formed by taking the first mask structure uncovered by the patterned structure as a mask to etch the first material layer.

Optionally, the width of the first structure is greater than the width of the second structure.

Optionally, the process of etching the first material layer is a dry etching process.

Optionally, the method for forming the first mask structure includes: forming a first mandrel structure on the first material layer; depositing a first mask material layer on the side wall and the top surface of the first mandrel structure; etching back the first mask material layer on the top surface of the first mandrel structure to form a first mask structure on the side wall surface of the first mandrel structure; and removing the first mandrel structure.

Optionally, the substrate includes: a substrate and an interlayer dielectric layer on the substrate.

Optionally, after removing the second mandrel structure, further comprising: and etching the interlayer dielectric layer by taking the second side wall structure as a mask so as to form a plurality of isolation structures positioned on the substrate and isolation gaps positioned between the isolation structures.

Optionally, an electrical interconnect structure is formed within each isolation gap.

Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:

in the method for forming the semiconductor structure provided by the technical scheme of the invention, after the first mask structure is formed, the patterning structure covering part of the first mask structure is formed, and the width of the patterning structure is larger than that of the first mask structure, so that the width of part of the first mask structure can be adjusted in a targeted manner, the width of the first mask structure is widened, and further, after the second mandrel structure is formed subsequently, part of the second mandrel structure has different widths, so that the flexibility of the finally formed device structure pattern is higher. Meanwhile, the width of part of the first mask structure is adjusted in a mode of forming a patterned structure covering part of the first mask structure, so that the forming process of the first mask structure is not required to be changed, a photomask required for forming the first mask structure is not required to be changed, the photomask can be reused in other processes, and the process cost is reduced.

Drawings

Fig. 1 to 4 are schematic cross-sectional views illustrating a process of forming a semiconductor structure;

Fig. 5 to 16 are schematic structural views of a forming process of a semiconductor structure according to an embodiment of the present invention.

Detailed Description

As described in the background art, in the metal lines formed by the self-aligned quad pattern process in the prior art, the size of a portion of the metal lines is completely determined by the width of the first sidewall pattern, so that the flexibility of the size and the spacing of the metal lines is poor, and the diversity of the integrated circuit design is limited.

Fig. 1 to 4 are schematic cross-sectional views illustrating a process of forming a semiconductor structure.

Referring to fig. 1, a substrate 100 is provided; forming a first material layer 101 on the substrate 100; a first mandrel structure 110 is formed on the first material layer 101.

Referring to fig. 2, a first sidewall structure 111 is formed on a sidewall of the first mandrel structure 110, and the first mandrel structure 110 is removed.

Referring to fig. 3, the first material layer 101 is etched by using the first sidewall structure 111 as a mask, so as to form a second mandrel structure 121; a second sidewall structure 122 is formed on the second mandrel structure sidewall.

Referring to fig. 4, the second mandrel structure 121 is removed; etching the substrate 100 with the second sidewall structures 122 as a mask to form isolation structures 131 and isolation gaps (not shown) between the isolation structures 131; metal lines (not shown) having different widths are formed in the respective isolation gaps.

In the present embodiment, the metal lines and the isolation structures 131 are formed in a self-aligned quad pattern process, and in each metal line, the width L of the first metal line 132a is determined by the width of the first sidewall structure 111, so that the structure of the first metal line 132a is fixed, and the overall metal line size and the pitch flexibility are poor.

In order to solve the technical problems, the technical scheme of the invention provides a method for forming a semiconductor structure, after a first mask structure is formed, a patterned structure covering part of the first mask structure is formed, and the width of the patterned structure is larger than that of the first mask structure, so that the width of part of the first mask structure can be adjusted in a targeted manner through the patterned structure, the width of the first mask structure is widened, and further, after a second mandrel structure is formed subsequently, part of the second mandrel structure has different widths, so that the flexibility of a finally formed device structure pattern is higher. Meanwhile, the width of part of the first mask structure is adjusted in a mode of forming a patterned structure covering part of the first mask structure, so that the forming process of the first mask structure is not required to be changed, a photomask required for forming the first mask structure is not required to be changed, and the process cost is reduced.

In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.

Fig. 5 to 16 are schematic structural views of a forming process of a semiconductor structure according to an embodiment of the present invention.

Referring to fig. 5, in the present embodiment, a substrate 200 includes: a substrate 201 and an interlayer dielectric layer 202 on the substrate 201.

In this embodiment, the interlayer dielectric layer 202 provides a raw material for the isolation structure between the subsequently formed electrical interconnect structures.

In this embodiment, the material of the substrate 201 includes silicon, silicon germanium, silicon carbide, silicon-on-insulator (SOI), germanium-on-insulator (GOI), and the like. Specifically, in the present embodiment, the material of the substrate 201 is silicon.

Referring to fig. 6 and 7, fig. 6 is a schematic cross-sectional view along AA' direction of fig. 7, and fig. 7 is a top view along P direction of fig. 6; a first material layer 203 is formed on the substrate 200.

In this embodiment, the first material layer 203 provides a raw material for a subsequently formed second mandrel structure.

In this embodiment, the material of the first material layer 203 includes silicon.

Referring to fig. 8, the view direction of fig. 8 is identical to that of fig. 7, and a plurality of first mask structures 230 are formed on the first material layer 203.

In this embodiment, the pattern of the first mask structure 230 is transferred into the substrate 200 through a subsequent process, and the structure and position of the first mask structure 230 determine the size of the electrical interconnection structure to be formed later and the size of the isolation structure between the electrical interconnection structures.

In this embodiment, the method for forming the first mask structure 230 includes: forming a first mandrel structure (not shown) on the first material layer 203; depositing a first masking material layer (not shown) on the first mandrel structure sidewalls and top surface; etching back the first mask material layer on the top surface of the first mandrel structure to form a first mask structure 230 on the sidewall surface of the first mandrel structure; and removing the first mandrel structure.

In this embodiment, the first mask structure 230 is formed on the sidewall surface of the first mandrel structure in a self-aligned manner, the first mask structure 230 serves as the first sidewall structure, and the pattern of the first mask structure 230 is continuously transferred downward through the subsequent etching process. Compared with the traditional photoetching process, the side wall structure formed in a self-alignment mode can meet the requirements of small-size device structures, and the size limit of the traditional process is broken through.

Referring to fig. 9, a patterned structure 231 is formed on a top surface and a sidewall surface of a portion of the first mask structure 230, wherein a width of the patterned structure 231 is greater than a width of the first mask structure 230.

In this embodiment, the length X1 of the first mask structure 230 is a dimension of the first mask structure 230 parallel to a first direction, the first direction is parallel to the surface of the substrate 200, the width Y1 of the first mask structure 230 is a dimension of the first mask structure 230 perpendicular to the first direction, and the width Y2 of the patterned structure 231 is a dimension of the patterned structure 231 perpendicular to the first direction.

In this embodiment, by forming the patterned structure 231 covering a portion of the first mask structure 230, and the width of the patterned structure 231 is larger than that of the first mask structure 230, the width of a portion of the first mask structure 230 can be adjusted in a targeted manner, so as to widen the width thereof, and further after the second mandrel structure is formed subsequently, a portion of the second mandrel structure has different widths, so that the flexibility of the finally formed device structure pattern is higher.

In this embodiment, the length X1 of the first mask structure 230 is a dimension of the first mask structure 230 parallel to a first direction, the first direction is parallel to the surface of the substrate 200, and the length X2 of the patterned structure 231 is a dimension of the patterned structure 231 parallel to the first direction. The length X1 of the first mask structure 230 is the same as the length X2 of the patterned structure 231.

In this embodiment, one patterned structure 231 is located on only one surface of the first mask structure 230, so as to adjust the width of the corresponding first mask structure 230. The number of the patterned structures 231 is greater than or equal to 1, and the number of the patterned structures 231 is different from the number of the first mask structures 230, so that the patterned structures 231 can flexibly adjust the widths of the first mask structures 230 at different positions, and the flexibility of subsequently formed device structure patterns is further increased.

In this embodiment, the method for forming the patterned structure 231 includes: after forming the first mask structure 230, an initial pattern material layer (not shown) is formed on the first material layer 203 and the first mask structure 230; the initial layer of patterning material is patterned to form patterned structures 231 on top surfaces and sidewall surfaces of portions of the first mask structure 230.

In this embodiment, since the patterned structure 231 is formed by patterning, the dimension of the patterned structure 231 should be larger than the limit dimension of the photolithography process during the patterning process, and in addition, the width of the patterned structure 231 should be larger than the width of the first mask structure 230, so as to widen the width of the first mask structure 230.

Specifically, the width of the patterned structure 231 is greater than 12 nm.

In this embodiment, the width of the first mask structure 230 is extended by the patterned structure 231, and a certain distance between the patterned structure 231 and the adjacent first mask structure 230 should be ensured, so that sufficient space is provided for the second sidewall structures formed on both sides of each first mask structure 230 and patterned structure 231.

Specifically, the spacing between the patterned structure 231 and the adjacent first mask structure 230 is greater than or equal to 3 times the width of the second sidewall structure 250 formed later, so that structural defects are avoided.

In this embodiment, the material of the patterned structure 231 includes photoresist. The material of the first mask structure 230 includes silicon nitride or silicon oxide.

Referring to fig. 10 and 11, fig. 10 is a top view of fig. 11 along the Q direction, fig. 11 is a schematic cross-sectional view of fig. 10 along the BB' direction, and the first material layer 203 is etched to form a plurality of second mandrel structures (not shown) by using the first mask structures 230 and the patterned structures 231 as masks.

In this embodiment, the second mandrel structure includes: a first structure 240, where the first structure 240 is formed by etching the first material layer 203 using the patterned structure 231 and the first mask structure 230 covered by the patterned structure 231 as a mask; and a second structure 241, where the second structure 241 is formed by etching the first material layer 203 using the first mask structure 230 uncovered by the patterned structure 231 as a mask.

In this embodiment, since the width of the first mask structure 230 is expanded by the patterned structure 231, the width of the first structure 240 is formed to be larger than the width of the second structure 241, so that flexibility of the width dimension of the second mandrel structure is increased, and further, after the electrical interconnection structure is formed subsequently, the width dimension of the electrical interconnection structure is made to have more design flexibility.

In this embodiment, the process of etching the first material layer 203 is a dry etching process.

Referring to fig. 12, the first mask structure 230 and the patterned structure 231 are removed, so that the surfaces of the first structure 240 and the second structure 241 are exposed.

In this embodiment, the process of removing the patterned structure 231 includes an ashing process. The process of removing the first mask structure 230 includes a wet etching process.

Referring to fig. 13, a second sidewall structure 250 is formed on the sidewall of each second mandrel structure.

In this embodiment, the patterning and transferring of the first mask structure 230, the second mandrel structure and the second sidewall structure 250 completes the process of self-aligned quad pattern, so that the pattern pitch (pitch) of the final structure is only one fourth of the initial pattern pitch, and the pattern size is greatly reduced.

In this embodiment, the method for forming the second sidewall structure 250 includes: depositing a second sidewall material layer (not shown) on the sidewalls and top surface of the second mandrel structure; and etching back the second sidewall material layer on the top surface of the second mandrel structure to form a second sidewall structure 250 located on the sidewall surface of the second mandrel structure.

In this embodiment, the material of the second sidewall structure 250 is the same as that of the first mask structure 230, and the material of the second sidewall structure 250 is different from that of the first material layer 203.

Referring to fig. 14, after forming the second sidewall structure 250, the second mandrel structure is removed.

In this embodiment, the process of removing the second mandrel structure includes a wet etching process. Specifically, the etching solution used in the wet etching process includes an alkaline solution, and the second mandrel structure can be removed by using the alkaline solution without affecting the second sidewall structure 250.

Referring to fig. 15, the interlayer dielectric layer 202 is etched using the second sidewall structures 250 as a mask, so as to form a plurality of isolation structures 260 on the substrate 201 and isolation gaps (not shown) between the isolation structures 260.

In this embodiment, the isolation gap provides space for subsequently formed electrical interconnect structures.

In this embodiment, the process of etching the interlayer dielectric layer 202 includes a dry etching process.

Referring to fig. 16, an electrical interconnect structure 261 is formed within each isolation gap.

In this embodiment, the material of the electrical interconnect structure 261 includes a metal.

In the present embodiment, the width dimension H of the etched electrical interconnect structure 261 corresponds to the width dimension of the first structure 240, i.e., the width dimension Y2 of the patterned structure 231, with the first structure 240 as a mask.

After the first mask structure 230 is formed, a patterned structure 231 covering a portion of the first mask structure 230 is formed, and the width of the patterned structure 231 is larger than that of the first mask structure 230, so that the width of a portion of the first mask structure 230 can be specifically adjusted, thereby widening the width thereof, and further enabling a portion of the first structure 240 and the second structure 241 included in the second mandrel structure to have different widths. Compared with the metal lines formed by the conventional self-aligned quad-patterning process, the dimensions of part of the metal lines are completely determined by the width of the side wall in the first self-aligned deposition process, and the width of the first mask structure 230 is changed by forming the patterned structure 231 in this embodiment, so that the width dimensions of the finally formed part of the electrical interconnection structure 261 are not completely dependent on the width of the first mask structure 230, flexible adjustment of the width of the electrical interconnection structure 261 is realized, the defect of single metal line pattern structure formed by the conventional self-aligned quad-patterning process is overcome, and the flexibility of the pattern design of the electrical interconnection structure 261 is improved.

In addition, the width of a portion of the first mask structure 230 is adjusted by forming the patterned structure 231 covering the portion of the first mask structure 230, so that there is no need to intervene in changing the forming process of the first mask structure 230, and there is no need to change a photomask required for forming the first mask structure 230, which can be reused in other processes, thereby reducing the process cost.

Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (17)

1. A method of forming a semiconductor structure, comprising:

Providing a substrate;

Forming a first material layer on the substrate;

Forming a plurality of first mask structures on the first material layer;

forming a patterned structure on the top surface and the side wall surface of part of the first mask structure, wherein the width of the patterned structure is larger than that of the first mask structure;

etching the first material layer by taking the first mask structure and the patterned structure as masks to form a plurality of second mandrel structures;

Forming a second side wall structure on the side wall of each second mandrel structure;

And removing the second mandrel structure after the second side wall structure is formed.

2. The method of forming a semiconductor structure of claim 1, wherein a length of the first mask structure is the same as a length of the patterned structure.

3. The method of claim 2, wherein a length of the first mask structure is a dimension of the first mask structure parallel to a first direction, the first direction being parallel to a surface of the substrate, and a length of the patterned structure is a dimension of the patterned structure parallel to the first direction.

4. The method of claim 1, wherein a length of the first mask structure is a dimension of the first mask structure parallel to a first direction, the first direction being parallel to the substrate surface, a width of the first mask structure is a dimension of the first mask structure perpendicular to the first direction, and a width of the patterned structure is a dimension of the patterned structure perpendicular to the first direction.

5. The method of forming a semiconductor structure of claim 1, wherein the method of forming a patterned structure comprises: forming an initial pattern material layer positioned on the first material layer and the first mask structure after forming the first mask structure; patterning the initial patterned material layer to form a patterned structure on a top surface and a sidewall surface of a portion of the first mask structure.

6. The method of forming a semiconductor structure of claim 1, wherein the patterned structure has a width greater than 12 nanometers.

7. The method of forming a semiconductor structure of claim 1, wherein a spacing between the patterned structure and an adjacent first mask structure is greater than or equal to 3 times a width of the second sidewall structure.

8. The method of forming semiconductor structures of claim 1, wherein the number of patterned structures is different from the number of first mask structures.

9. The method of forming a semiconductor structure of claim 1, wherein a patterned structure is located on a surface of a first mask structure.

10. The method of forming a semiconductor structure of claim 1, wherein the material of the patterned structure comprises a photoresist.

11. The method of forming a semiconductor structure of claim 1, wherein the second mandrel structure comprises: the first structure is formed by taking the patterned structure and a first mask structure covered by the patterned structure as masks to etch the first material layer; and the second structure is formed by taking the first mask structure uncovered by the patterned structure as a mask to etch the first material layer.

12. The method of forming a semiconductor structure of claim 11, wherein a width of the first structure is greater than a width of the second structure.

13. The method of forming a semiconductor structure of claim 1, wherein the process of etching the first material layer is a dry etching process.

14. The method of forming a semiconductor structure of claim 1, wherein the method of forming the first mask structure comprises: forming a first mandrel structure on the first material layer; depositing a first mask material layer on the side wall and the top surface of the first mandrel structure; etching back the first mask material layer on the top surface of the first mandrel structure to form a first mask structure on the side wall surface of the first mandrel structure; and removing the first mandrel structure.

15. The method of forming a semiconductor structure of claim 1, wherein the substrate comprises: a substrate and an interlayer dielectric layer on the substrate.

16. The method of forming a semiconductor structure of claim 15, further comprising, after removing the second mandrel structure: and etching the interlayer dielectric layer by taking the second side wall structure as a mask so as to form a plurality of isolation structures positioned on the substrate and isolation gaps positioned between the isolation structures.

17. The method of forming a semiconductor structure of claim 16, wherein an electrical interconnect structure is formed within each isolation gap.