CN117912515A - Row address decoding circuit and memory - Google Patents

Row address decoding circuit and memory Download PDF

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Publication number
CN117912515A
CN117912515A CN202211241702.XA CN202211241702A CN117912515A CN 117912515 A CN117912515 A CN 117912515A CN 202211241702 A CN202211241702 A CN 202211241702A CN 117912515 A CN117912515 A CN 117912515A
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China
Prior art keywords
address
signal
decoding
control signal
memory
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CN202211241702.XA
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Inventor
刘忠来
尚为兵
高恩鹏
冀康灵
邱安平
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202211241702.XA priority Critical patent/CN117912515A/en
Priority to PCT/CN2022/127067 priority patent/WO2024077659A1/en
Publication of CN117912515A publication Critical patent/CN117912515A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/408—Address circuits

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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)
  • Read Only Memory (AREA)

Abstract

The embodiment of the disclosure discloses a row address decoding circuit and a memory, wherein the row address decoding circuit comprises N storage address control circuits, and N is greater than or equal to 1. Each memory address control circuit includes: and a control signal generation module. The control signal generation module is used for receiving at least one address pre-decoding signal and generating an address control signal according to the address pre-decoding signal; the control signal generation module includes a low threshold voltage transistor. The embodiment of the disclosure can shorten the time of row decoding and improve the efficiency.

Description

Row address decoding circuit and memory
Technical Field
The present disclosure relates to, but is not limited to, a row address decoding circuit and a memory.
Background
In order to improve the performance of the memory, faster reading and writing of the memory cells is required. The Row address decoding circuit of the memory cell is necessary in the memory circuit for decoding and gating the Row address (Row address). The row address decoding circuit directly affects the read speed of the memory and the load of the charge pump.
Disclosure of Invention
In view of this, the embodiments of the present disclosure provide a row address decoding circuit and a memory, which can shorten the time of row decoding and improve the efficiency.
The technical scheme of the embodiment of the disclosure is realized as follows:
the embodiment of the disclosure provides a row address decoding circuit, which comprises N storage address control circuits, wherein N is greater than or equal to 1; each memory address control circuit includes: the control signal generation module is used for receiving at least one address pre-decoding signal and generating an address control signal according to the address pre-decoding signal; the control signal generation module includes a low threshold voltage transistor.
In the above solution, the memory address control circuit further includes: the power supply control module is respectively connected with the control signal generation module and the power supply end and is used for receiving the operation pulse signal and the address control signal, and transmitting the power supply voltage of the power supply end to the control signal generation module according to the operation pulse signal and the address control signal so as to enable the control signal generation module to operate.
In the above scheme, the power control module includes: the power supply control signal generating unit is used for receiving the operation pulse signal and the address control signal and generating a power supply control signal according to the operation pulse signal and the address control signal; and the power switch unit is respectively connected with the power control signal generation unit, the control signal generation module and the power end and is used for receiving the power control signal and responding to the power control signal to transmit the power voltage to the control signal generation module.
In the above aspect, the power control signal generating unit includes: the first input end of the OR gate receives the operation pulse signal, the second input end of the OR gate receives the address control signal, and the OR gate outputs the power supply control signal.
In the above scheme, the control signal generating module includes a decoding module; the address control signals include row address decoding signals; the decoding module is used for receiving at least one address pre-decoding signal and generating a row address decoding signal according to the address pre-decoding signal.
In the above scheme, the control signal generating module further includes other control signal generating modules; the address control signals also include other control signals; the other control signal generating module is configured to receive at least one address pre-decoding signal, and generate the other control signals according to the address pre-decoding signal.
In the above aspect, the row address decoding circuit further includes: and the operation pulse generation module is used for receiving the initial operation signal and generating an operation pulse signal according to the initial operation signal.
In the above scheme, the initial operation signal is an activation command signal.
In the above scheme, the operation pulse generation module includes: the input end of the inverter receives the initial operation signal; the input end of the delayer is connected with the output end of the inverter; and the first input end of the AND gate receives the initial running signal, the second input end of the AND gate is connected with the output end of the delay device, and the AND gate outputs the running pulse signal.
The embodiment of the disclosure also provides a memory, which comprises the row address decoding circuit in the scheme.
In the above solution, the memory further includes: at least one memory bank; at least one of the banks is disposed on at least one of two sides of the row address decoding circuit opposite in the first direction.
In the above scheme, each memory bank includes N memory segments; the row address decoding circuit comprises N storage address control circuits; n storage segments are in one-to-one correspondence to receive the address control signals output by N storage address control circuits.
In the above solution, the memory further includes: and the pre-decoding module is used for receiving an initial running signal and a row address coding signal, pre-decoding the row address coding signal according to the initial running signal and obtaining at least one address pre-decoding signal.
In the above scheme, the pre-decoding module includes: a combinational logic circuit, a row fuse matching circuit and a row address pre-decoding circuit; the combinational logic circuit is used for receiving an initial operation signal and an initial address signal and generating a pre-decoding driving signal corresponding to the initial address signal; the row fuse matching circuit is used for receiving the initial address signal, performing matching and replacement of fuse addresses on the initial address signal, and transmitting the matched and replaced address signal to the row address pre-decoding circuit; the row address pre-decoding circuit is respectively connected with the combinational logic circuit and the row fuse matching circuit and is used for receiving the pre-decoding driving signal and the matched and replaced address signals, pre-decoding the address signals and generating address pre-decoding signals.
In the above scheme, the memory is a dynamic random access memory DRAM.
It can be seen that the embodiments of the present disclosure provide a row address decoding circuit and a memory, where the row address decoding circuit includes N memory address control circuits, and N is greater than or equal to 1. Each memory address control circuit includes: and a control signal generation module. The control signal generation module is used for receiving at least one address pre-decoding signal and generating an address control signal according to the address pre-decoding signal; the control signal generation module includes a low threshold voltage transistor. Since the smaller the threshold voltage is, the stronger the current capability is, and the smaller the delay is, the transistor with a low threshold voltage is formed in the control signal generating module, so that the time for row decoding can be shortened, and the efficiency can be improved.
Drawings
Fig. 1 is a schematic diagram of a row address decoding circuit according to an embodiment of the disclosure;
fig. 2 is a schematic diagram of a row address decoding circuit according to an embodiment of the disclosure;
FIG. 3 is an explanatory diagram of threshold voltages of transistors;
Fig. 4 is a schematic diagram III of a structure of a row address decoding circuit according to an embodiment of the disclosure;
Fig. 5 is a schematic diagram of a row address decoding circuit according to an embodiment of the disclosure;
Fig. 6 is a schematic diagram of a row address decoding circuit according to an embodiment of the disclosure;
fig. 7 is a schematic diagram of a row address decoding circuit according to an embodiment of the disclosure;
FIG. 8 is a first signal diagram of a row address decoder according to an embodiment of the disclosure;
fig. 9 is a schematic diagram seventh of a structure of a row address decoding circuit according to an embodiment of the disclosure;
Fig. 10 is a schematic diagram eight of a structure of a row address decoding circuit according to an embodiment of the disclosure;
FIG. 11 is a second signal diagram of a row address decoder according to an embodiment of the disclosure;
FIG. 12 is a schematic diagram of a memory according to an embodiment of the disclosure;
fig. 13 is a schematic diagram of a second structure of the memory according to the embodiment of the disclosure.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present disclosure more apparent, the technical solutions of the present disclosure are further elaborated below in conjunction with the drawings and the embodiments, and the described embodiments should not be construed as limiting the present disclosure, and all other embodiments obtained by those skilled in the art without making inventive efforts are within the scope of protection of the present disclosure.
In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.
If a similar description of "first/second" appears in the application document, the following description is added, in which the terms "first/second/third" merely distinguish similar objects and do not represent a specific ordering of the objects, it being understood that "first/second/third" may, where allowed, interchange a specific order or precedence, to enable embodiments of the disclosure described herein to be practiced otherwise than as illustrated or described herein.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.
Fig. 1 is a schematic diagram of an alternative structure of a row address decoding circuit according to an embodiment of the present disclosure, and as shown in fig. 1, a row address decoding circuit 10 includes N memory address control circuits 20, where N is greater than or equal to 1.
Referring to fig. 1 and 2, each memory address control circuit 20 includes: a control signal generation module 201. The control signal generating module 201 is configured to receive at least one address pre-decoding signal ra_pre, and generate an address control signal ra_en according to the address pre-decoding signal ra_pre. The control signal generation module 201 includes a low threshold voltage transistor.
In the embodiment of the present disclosure, the number N of the memory address control circuits 20 may be set according to the number of memory segments in the memory. In some embodiments, the number N of memory address control circuits 20 is set to 32, 64, 65, 66, 128, or the like. Each memory address control circuit 20 may control several memory addresses, for example, 4096 memory addresses per memory address control circuit 20. Each memory address stores 1 bit of data.
In the disclosed embodiment, the address pre-decoding signal ra_pre is obtained by pre-decoding (preDecode) the encoded address signal. For example, the encoded address signal contains 17 bits, denoted Ra <16:0>, i.e., bits 0-16. The partial address bits may be column multiplexed, with Ra <16> being multiplexed as an example.
When Ra <16> is used to represent a column address, the row address pre-decode signal Ra_pre may comprise ：R210<7:0>、R543<7:0>、R876<7:0>、R9<1:0>、R121110<7:0>、R151413<7:0>, etc. signals that represent the pre-decode result of a portion of the bits in the memory address, respectively. Wherein R210<7:0> is the pre-decoding result of the 0 th to 2 nd bits of the memory address, and <7:0> indicates that there is 8 bits of data in the pre-decoding result, that is, 3 bits (0 th to 2 nd bits) in the encoded memory address are pre-decoded into the pre-decoding result containing 8 bits (i.e., 2 3 bits) of data. Similarly, R543<7:0> is the 3 rd to 5 th bit pre-decoding result of the memory address, and contains 8 bits (i.e. 2 3 bits) of data; r876<7:0> is the pre-decoding result of bits 6-8 of the memory address, and contains 8 bits (i.e. 2 3 bits) of data; r9<1:0> is the pre-decoding result of bit 9 of the memory address, comprising 2 bits (i.e., 2 1 bits) of data; r121110<7:0> is the 10 th to 12 th bit pre-decoding result of the memory address, and contains 8 bit (namely 2 3 bit) data; r151413<7:0> is the pre-decode result of bits 13-15 of the memory address, containing 8 bits (i.e., 2 3 bits) of data.
When Ra <16> is used to represent a row address, the row address pre-decode signal ra_pre may include: signals R210<7:0>, R543<7:0>, R876<7:0>, R109<3:0>, R131211<7:0> and R161514<7:0>, etc. Wherein R210<7:0> is the pre-decoding result of bits 0-2 of the memory address, and comprises 8 bits (i.e. 2 3 bits) of data; r543<7:0> is the 3 rd to 5 th bit pre-decoding result of the memory address, and contains 8 bits (i.e. 2 3 bits) of data; r876<7:0> is the pre-decoding result of bits 6-8 of the memory address, and contains 8 bits (i.e. 2 3 bits) of data; r109<3:0> is the pre-decoding result of the 9 th to 10 th bits of the memory address, and comprises 4 bits (namely 2 2 bits) of data; r131211<7:0> is the pre-decoding result of the 11 th to 13 th bits of the memory address, and contains 8 bits (namely 2 3 bits) of data; r161514<7:0> is the pre-decode result of bits 14-16 of the memory address, containing 8 bits (i.e., 2 3 bits) of data.
Further, the address pre-decode signal ra_pre is input to each control signal generation block 201. The control signal generating module 201 may decode the address pre-decode signal ra_pre after receiving the address pre-decode signal ra_pre to obtain the address control signal ra_en. Thus, the encoded address signal is decoded into the address control signal ra_en after being "pre-decoded", which is a step-by-step decoding. It should be noted that, the embodiments of the present disclosure are not limited to the two-step decoding mode of "pre-decoding", that is, the embodiments of the present disclosure may also directly decode without pre-decoding, and may also decode after multiple pre-decoding.
The gate-source voltage V GS corresponding to the critical point of the on-state and the off-state of the NMOS transistor is generally referred to as a threshold voltage. Fig. 3 schematically illustrates a transmission characteristic curve of an NMOS transistor, that is, a variation curve of the drain current I D with the gate-source voltage V GS, and an NMOS transistor is taken as an example for illustration.
Referring to fig. 3, in the NMOS transistor, when the device is turned from depletion to inversion, a state where the electron concentration is equal to the hole concentration is required, and at this time, the device is in a critical on state, and the corresponding gate-source voltage V GS is the threshold voltage Vt. If the gate-source voltage V GS is smaller than the threshold voltage Vt, a channel cannot be formed in the NMOS transistor, and the NMOS transistor is not conducted. On the other hand, the threshold voltage of an NMOS transistor also affects its current capability. That is, for two NMOS transistors with different threshold voltages, when the same gate-source voltage is input, the NMOS transistor with smaller threshold voltage can transmit larger current. The stronger the current capability of the NMOS transistor, the faster the signal transmission speed, that is, the smaller the delay time caused by the NMOS transistor with smaller threshold voltage. It should be noted that the PMOS transistor may be understood with reference to the NMOS transistor.
In the disclosed embodiment, a low threshold voltage transistor is included in the control signal generation module 201. Here, the threshold voltage of the low threshold voltage transistor is lower than that of the normal transistor; the common transistor refers to a transistor formed by a common process. For example, for a DDR (double Rate synchronous dynamic random Access memory), the threshold voltage of a normal transistor is between 0.5V and 0.7V, while the threshold voltage of a low threshold voltage transistor is 100mV to 200mV less than the threshold voltage of a normal transistor. For another example, for an LPDDR (low power double rate synchronous dynamic random access memory), the threshold voltage of the normal transistor is between 0.3V and 0.6V, and the threshold voltage of the low threshold voltage transistor is 100mV to 200mV less than the threshold voltage of the normal transistor.
The threshold voltage of the low threshold voltage transistor may be different according to different products, different processes, or different transistor applications. The above exemplary values are merely some of the optional cases of low threshold voltage transistors and are not limiting of the embodiments of the present disclosure.
Further, referring to fig. 1 and 2, the row address decoding circuit 10 decodes the row address of the address pre-decoding signal ra_pre. The low threshold voltage transistor is adopted in the control signal generating module 201, so that delay in the control signal generating module 201 can be reduced, and the time for row decoding can be shortened.
In the embodiment of the disclosure, the threshold voltage of the transistor can be influenced and controlled by controlling the doping of the back gate, the gate material or the gate dielectric thickness and other factors. For example, by controlling the doping of the back gate, inversion of the semiconductor surface is made easier, thereby lowering the threshold voltage. As another example, the threshold voltage is lowered by reducing the gate dielectric thickness. In this way, in the control signal generation module 201, a low threshold voltage transistor can be formed by processing.
It can be understood that the transistor with smaller threshold voltage has stronger current capability and smaller delay time, so that the transistor with lower threshold voltage is formed in the control signal generating module, thereby shortening the time of row decoding and improving the efficiency.
In some embodiments of the present disclosure, as shown in fig. 4, the memory address control circuit 20 further includes: the power control module 202. The power control module 202 is connected to the control signal generating module 201 and a power terminal (not shown in fig. 4), respectively. The power control module 202 is configured to receive the operation pulse signal ActPls and the address control signal ra_en, and transmit a power voltage P of a power terminal to the control signal generating module 201 according to the operation pulse signal ActPls and the address control signal ra_en, so that the control signal generating module 201 operates.
It should be noted that, the power supply voltage P at the power supply end may be a constant voltage or a variable voltage signal, which will be understood with reference to the following description will not be repeated.
In the above embodiments, the power supply terminal refers only to the input power of the row address decoding circuit, and is not the input power at the pin (pin) or the terminal (terminal). However, the present disclosure is not limited thereto, and in other embodiments, the power supply terminal may be an input power source of a row address decoding circuit directly input to the row address decoding circuit from a pin or terminal.
The control signal generating module 201 has a quiescent current. The quiescent current refers to the current existing in the device when no signal is input, and each device in the chip has the quiescent current. Taking DDR (double rate synchronous dynamic random access memory) as an example, DDR includes working states such as Precharge, active, read, write, refresh, etc. Under different operating conditions, there may be quiescent current in the DDR, for example, I DD2P is the quiescent current in the precharge state and I DD3N is the quiescent current in the active state. The presence of quiescent current can cause the static power consumption of the chip, i.e., the chip also generates power consumption in the Idle state.
In the embodiment of the present disclosure, referring to fig. 4, the power control module 202 may control whether the power voltage P is transmitted to the control signal generation module 201 according to the operation pulse signal ActPls and the address control signal ra_en. In this way, when the control signal generating module 201 is in an idle state, the power control module 202 may cut off the transmission of the power voltage P to the control signal generating module 201, so as to avoid generating a quiescent current in the control signal generating module 201 (if the device is not connected to the power voltage P, there is no voltage difference between the ends thereof, and no quiescent current will be generated therein).
On the other hand, a low threshold voltage transistor is included in the control signal generation module 201. Compared with a common transistor, the low threshold voltage transistor has stronger current capability, that is, for two MOS transistors with different threshold voltages, under the condition of inputting the same gate-source voltage, the MOS transistor with smaller threshold voltage can transmit larger current, so that the low threshold voltage transistor is easy to generate larger static current.
It can be appreciated that by controlling the transmission of the power supply voltage, the power supply control module 202 cuts off the transmission of the power supply voltage to the control signal generating module 201 when the control signal generating module 201 is in an idle state, so that the generation of a larger quiescent current by the low threshold voltage transistor in the control signal generating module 201 can be avoided, thereby reducing the quiescent power consumption.
Further, the row address decoding circuit provided by the embodiment of the disclosure may be applied to an LPDDR (low power consumption double rate synchronous dynamic random access memory) to further reduce power consumption of the LPDDR.
In some embodiments of the present disclosure, as shown in fig. 5, the power control module 202 includes: a power control signal generation unit 203 and a power switching unit 204. The power control signal generating unit 203 is configured to receive the operation pulse signal ActPls and the address control signal ra_en, and generate a power control signal sc_en according to the operation pulse signal ActPls and the address control signal ra_en. The power switching unit 204 is connected to the power control signal generating unit 203, the control signal generating module 201, and a power source terminal (not shown in fig. 5), respectively. The power switch unit 204 is configured to receive a power control signal sc_en, and transmit a power voltage P to the control signal generating module 201 in response to the power control signal sc_en.
In some embodiments of the present disclosure, referring to fig. 6, the power switching unit 204 may include an AND gate AND1. A first input end of the AND gate AND1 receives a power supply control signal Sc_En; the second input end of the AND gate AND1 is connected with a power supply end, namely receives a power supply voltage P; the output end of the AND gate AND1 is connected with a control signal generating module. Thus, when the power supply control signal sc_en is at a high level, the AND gate AND1 outputs the power supply voltage P to the control signal generation block; when the power control signal sc_en is low, the output terminal of the AND gate AND1 is also low, i.e., the power voltage P is not output.
It should be noted that fig. 6 only shows an alternative structure of the power switch unit 204, and the power switch unit 204 may also be formed by a separate transistor or a complementary MOS transistor (CMOS transistor), that is, the power control signal sc_en is connected to the control terminal of the separate transistor or the complementary MOS transistor to control the output of the power supply voltage P. There is no limitation in this regard.
Further, referring to fig. 5, the power switching unit 204 may further include a level shifter (LEVEL SHIFTER) and an inverter, etc. The level shifter is used to shift the power supply voltage P to an appropriate level. The inverter is used for improving the driving capability of the power switch unit 204 to avoid signal attenuation.
In some embodiments of the present disclosure, as shown in fig. 7, the power control signal generation unit 203 includes: OR gate OR1. The first input terminal of the OR gate OR1 receives the operation pulse signal ActPls, the second input terminal of the OR gate OR1 receives the address control signal ra_en, and the OR gate OR1 outputs the power control signal sc_en.
Fig. 8 is a schematic waveform diagram of an alternative of the run pulse signal ActPls, the address control signal ra_en, and the power control signal sc_en.
In the disclosed embodiment, in conjunction with fig. 7 and 8, the operation pulse signal ActPls is active high after being activated by the initial operation signal. The initial operation signal may be an activation command signal (active) or an independent control signal. The inactive (i.e., low level) address control signal ra_en and the active (i.e., high level) operation pulse signal ActPls are logically ored (i.e., through the OR gate OR 1) to obtain the active power control signal sc_en. Then, the address control signal ra_en remains in an active state, and the power control signal sc_en remains in an active state. That is, the running pulse signal ActPls activates the active state of the power control signal sc_en, and then the address control signal ra_en maintains the active state of the power control signal sc_en.
In the embodiment of the present disclosure, referring to fig. 5 and 8, when the power control signal sc_en is at a high level, the control signal generation module 201 may operate and output the address control signal ra_en. Here, since the operation pulse signal ActPls is earlier in time sequence, the active state of the power control signal sc_en can be activated earlier, and thus the power switching unit 204 can transmit the power voltage P to the control signal generation module 201 faster to cause the signal generation module 201 to operate, so that the delay time can be reduced, facilitating control.
In some embodiments of the present disclosure, as shown in fig. 9, the control signal generation module 201 includes a decoding module 205, and the address control signal includes a row address decoding signal sec_en. The decoding module 205 is configured to receive at least one address pre-decoding signal ra_pre, and generate a row address decoding signal sec_en according to the address pre-decoding signal ra_pre.
In some embodiments of the present disclosure, as shown in fig. 9, the control signal generation module 201 further includes an other control signal generation module 206, and the address control signal further includes an other control signal Oth _en. The other control signal generating module 206 is configured to receive at least one address pre-decoding signal ra_pre, and generate other control signals Oth _en according to the address pre-decoding signal ra_pre.
It should be noted that the address control signal ra_en shown in fig. 4 may be the row address decode signal sec_en and/or the other control signal Oth _en shown in fig. 9. In some embodiments, the row address decode signal Sec_En is transmitted to the power control module 202 for controlling the transmission of the power supply voltage, as shown in FIG. 9. In other embodiments, other control signals Oth _en are transmitted to the power control module 202 for controlling the transmission of the power supply voltage.
In the embodiment of the present disclosure, referring to fig. 9, the decoding module 205 may generate the row address decoding signal sec_en according to the address pre-decoding signal ra_pre, that is, the decoding module 205 may decode the connection and the section (section) of the row address program (program). The other control signal generating module 206 may generate the other control signal Oth _en according to the address pre-decoding signal ra_pre, that is, the other control signal generating module 206 may generate other control signals in the memory Array (Array).
In the disclosed embodiment, the other control signals Oth _en include: a phase drive signal (PHASE DRIVING SIGNAL), a main word line drive signal (main word LINE DRIVING SIGNAL), a sense amplifier control signal (SENSE AMPLIFIER controlling signal), and the like. That is, other control signals Oth _en include, but are not limited to, drive signals and control signals in memory.
In some embodiments, as shown in fig. 9, the row address decoding signal sec_en generated by the decoding module 205 is transmitted to the power control module 202, and the power control module 202 transmits the power voltage P of the power terminal to the decoding module 205 and the other control signal generating module 206 according to the operation pulse signal ActPls and the row address decoding signal sec_en, so that both operate. In other embodiments, the other control signal Oth _en generated by the other control signal generating module 206 is transmitted to the power control module 202, and the power control module 202 transmits the power voltage P of the power terminal to the decoding module 205 and the other control signal generating module 206 according to the operation pulse signal ActPls and the other control signal Oth _en, so that both operate.
In some embodiments of the present disclosure, the row address decoding circuit 10 shown in fig. 1 further includes an operation pulse generation module therein. The operation pulse generation module is used for receiving the initial operation signal and generating an operation pulse signal according to the initial operation signal.
In some embodiments of the present disclosure, the initial operation signal is an activation command signal (active), i.e., the multiplexed activation command signal (active) is the initial operation signal. Since the activate command signal is the first command signal at the time of memory read-write, it is earliest in time sequence; therefore, the operation pulse signal generated from the initial operation signal also has an earlier timing.
In other embodiments of the present disclosure, the initial run signal may also be a separately transmitted control signal or other multiplexed signal, which also has an earlier timing, thereby allowing the run pulse signal to have an earlier timing.
In some embodiments of the present disclosure, as shown in fig. 10, the operation pulse generation module 101 includes: inverter INV1, delay DEL AND gate AND2. An input terminal of the inverter INV1 receives the initial operation signal Act. An input terminal of the delay DEL is connected to an output terminal of the inverter INV 1. The first input terminal of the AND gate AND2 receives the initial operation signal Act, the second input terminal of the AND gate AND2 is connected to the output terminal of the delay DEL, AND the AND gate AND2 outputs the operation pulse signal ActPls.
In the embodiment of the present disclosure, the delay DEL may be configured with an even number of inverters, or may be configured with an inverter, a CMOS capacitor, or the like. It should be noted that the delay device is a structure commonly used in the art, so long as the delay function can be completed, and the delay device is not specifically limited herein.
Fig. 11 is a schematic diagram of signals corresponding to fig. 10. Referring to fig. 10 AND 11, the initial operation signal Act may obtain an operation pulse signal ActPls after passing through the inverter INV1, the delay DEL, AND the AND gate AND 2. Both the initial run signal Act and the run pulse signal ActPls are active high, and the effective pulse width of the run pulse signal ActPls is less than the effective pulse width of the initial run signal Act. It should be noted that, since the inverter INV1, the delay DEL AND the AND gate AND2 have physical delays, the running pulse signal ActPls has a delay with respect to the initial running signal Act, AND the pulse leading edge of the running pulse signal ActPls may be relatively delayed from the signal leading edge of the initial running signal Act.
It will be appreciated that since the initial operating signal Act is most forward of the various signals in the memory, that is, the initial operating signal Act is more forward in time sequence than the other signals; therefore, the operation pulse signal ActPls obtained from the initial operation signal Act is also more forward in timing. And the operation pulse signal ActPls is used by the power switching unit for a control signal to transmit the power supply voltage to the control signal generation module. In this way, the power switching unit can transfer the power supply voltage to the control signal generating module faster to cause the signal generating module to operate, thereby enabling to reduce the delay time, or even the influence on the parameter tRCD (row strobe period) in the chip.
The disclosed embodiments also provide a memory, referring to fig. 12, the memory 80 includes a row address decoding circuit 10.
In some embodiments of the present disclosure, referring to fig. 12, the memory 80 further includes: at least one bank (bank), each of which may include two half banks 30 (i.e., half-bank) provided separately on both sides of the row address decoding circuit 10.
In still other embodiments, the memory 80 may further comprise: at least one bank (bank), each bank being provided on at least one of two opposite sides of the row address decoding circuit 10 in the first direction X.
In some embodiments of the present disclosure, in conjunction with fig. 1, 2, and 12, each memory bank 30 includes N memory segments 40. The row address decoding circuit 10 includes N memory address control circuits 20. The N memory segments 40 receive the address control signals ra_en output from the N memory address control circuits 20 in one-to-one correspondence.
In the disclosed embodiment, the address decoding circuit (including the row address decoding circuit 10) may direct the input binary address to the corresponding physical space in the memory 80. In the memory 80, in order to read data of a specific cell, it is first determined which bank is addressed, and then addressing of a row and column is performed in this selected bank. During operation of memory 80, the bank address is issued simultaneously with the corresponding row address, and this command is referred to as "row valid" or "row active". After this, a column address addressing command and a specific operation command (read or write) are sent, which are also sent simultaneously, so column addressing is denoted by "read/write command". Wherein the row and column addresses are reusable. The interval from row valid to read/write command issue is defined as tRCD (row strobe period), i.e., RAS to CAS Delay (RAS to CAS Delay), where RAS is the row address strobe and CAS is the column address strobe.
In some embodiments of the present disclosure, the memory 80 shown in fig. 12 further includes: and a pre-decoding module. The pre-decoding module is used for receiving the initial running signal and the row address coding signal, pre-decoding the row address coding signal according to the initial running signal, and obtaining at least one address pre-decoding signal.
In some embodiments of the present disclosure, as shown in fig. 13, the pre-decoding module 50 includes: a combinational logic circuit 501, a row fuse matching circuit 502, and a row address pre-decoding circuit 503. The combinational logic circuit 501 is configured to receive the initial operation signal Act and the initial address signal Ra, and generate a pre-decoded driving signal corresponding to the initial address signal Ra. The row fuse matching circuit 502 is configured to receive an initial address signal Ra, match and replace the fuse address of the initial address signal Ra, and then transmit the matched and replaced address signal to the row address pre-decoding circuit 503. The row address pre-decoding circuit 503 is connected to the combinational logic circuit 501 and the row fuse matching circuit 502, and is configured to receive the pre-decoding driving signal and the matched and replaced address signal, and pre-decode the matched and replaced address signal to generate an address pre-decoding signal ra_pre.
In the embodiment of the present disclosure, referring to fig. 13, the combinational logic circuit 501 processes the initial operation signal Act and the initial address signal Ra received by the combinational logic circuit to output the pre-decode driving signal. In the memory, the opening of the memory row (row) requires a plurality of signals to be driven together, such as a phase driving signal (PHASE DRIVING SIGNAL) and a main word line driving signal (main word LINE DRIVING SIGNAL), and the like. The pre-decode drive signal may control the memory row (row) to perform various operations (e.g., read/write operations), along with other drive signals.
In the embodiment of the disclosure, since the memory cells in the memory may be in error during the preparation process or the use process, that is, the data cannot be correctly stored, the fuse circuit is disposed in the memory to record the address of the in-error memory cell in the memory array (array). The fuse circuit includes a fuse array, a broadcast circuit, a latch, a fuse matching circuit, and the like. The fuse matching circuit comprises a row fuse matching circuit and a column fuse matching circuit. Referring to fig. 13, the row fuse matching circuit 502, upon receiving the initial address signal Ra, matches the initial address signal Ra with the error address information recorded in the fuse array to determine whether the error address is included in the initial address signal Ra. If the initial address signal Ra and the error address information are successfully matched, i.e. the initial address signal Ra comprises the error address, the address of the redundant memory cell in the memory array area is used for replacing the error address, and the intact memory cell in the redundant array is activated
In the embodiment of the present disclosure, the address pre-decoding signal ra_pre is obtained by pre-decoding (preDecode) the matched and replaced address signals. For example, the initial address signal Ra includes 17 bits, denoted Ra <16:0>, i.e., bits 0-16. The partial address bits may be column multiplexed. Ra <16> is multiplexed as an example.
When Ra <16> is used to represent a column address, the row address pre-decode signal Ra_pre may comprise ：R210<7:0>、R543<7:0>、R876<7:0>、R9<1:0>、R121110<7:0>、R151413<7:0>, etc. signals that represent the pre-decode result of a portion of the bits in the memory address, respectively. Wherein R210<7:0> is the pre-decoding result of the 0 th to 2 nd bits of the memory address, and <7:0> indicates that there is 8 bits of data in the pre-decoding result, that is, 3 bits (0 th to 2 nd bits) in the encoded memory address are pre-decoded into the pre-decoding result containing 8 bits (i.e., 2 3 bits) of data. Similarly, R543<7:0> is the 3 rd to 5 th bit pre-decoding result of the memory address, and contains 8 bits (i.e. 2 3 bits) of data; r876<7:0> is the pre-decoding result of bits 6-8 of the memory address, and contains 8 bits (i.e. 2 3 bits) of data; r9<1:0> is the pre-decoding result of bit 9 of the memory address, comprising 2 bits (i.e., 2 1 bits) of data; r121110<7:0> is the 10 th to 12 th bit pre-decoding result of the memory address, and contains 8 bit (namely 2 3 bit) data; r151413<7:0> is the pre-decode result of bits 13-15 of the memory address, containing 8 bits (i.e., 2 3 bits) of data.
When Ra <16> is used to represent a row address, the row address pre-decode signal ra_pre may include: signals R210<7:0>, R543<7:0>, R876<7:0>, R109<3:0>, R131211<7:0> and R161514<7:0>, etc. Wherein R210<7:0> is the pre-decoding result of bits 0-2 of the memory address, and comprises 8 bits (i.e. 2 3 bits) of data; r543<7:0> is the 3 rd to 5 th bit pre-decoding result of the memory address, and contains 8 bits (i.e. 2 3 bits) of data; r876<7:0> is the pre-decoding result of bits 6-8 of the memory address, and contains 8 bits (i.e. 2 3 bits) of data; r109<3:0> is the pre-decoding result of the 9 th to 10 th bits of the memory address, and comprises 4 bits (namely 2 2 bits) of data; r131211<7:0> is the pre-decoding result of the 11 th to 13 th bits of the memory address, and contains 8 bits (namely 2 3 bits) of data; r161514<7:0> is the pre-decode result of bits 14-16 of the memory address, containing 8 bits (i.e., 2 3 bits) of data.
Further, the address pre-decoding signal ra_pre is inputted to each control signal generating block to be decoded. The process of "pre-decoding" is thus step-decoding. It should be noted that, the embodiments of the present disclosure are not limited to the two-step decoding mode of "pre-decoding", that is, the embodiments of the present disclosure may also directly decode without pre-decoding, and may also decode after multiple pre-decoding.
In some embodiments of the present disclosure, the memory of the present disclosure is a dynamic random access memory, DRAM. The memory of the present disclosure may be LPDDR4 (fourth generation low power consumption double rate synchronous dynamic random access memory), LPDDR5 (fifth generation low power consumption double rate synchronous dynamic random access memory), LPDDR6 (sixth generation low power consumption double rate synchronous dynamic random access memory), or the memory of the present disclosure may also be DDR4 (fourth generation double rate synchronous dynamic random access memory), DDR5 (fifth generation double rate synchronous dynamic random access memory), or DDR6 (sixth generation double rate synchronous dynamic random access memory).
It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment. The features disclosed in the several product embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.
The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (15)

1. A row address decoding circuit, wherein the row address decoding circuit includes N memory address control circuits, N being 1 or more; each memory address control circuit includes:
The control signal generation module is used for receiving at least one address pre-decoding signal and generating an address control signal according to the address pre-decoding signal; the control signal generation module includes a low threshold voltage transistor.
2. The row address decoding circuit of claim 1, wherein the memory address control circuit further comprises:
The power supply control module is respectively connected with the control signal generation module and the power supply end and is used for receiving the operation pulse signal and the address control signal, and transmitting the power supply voltage of the power supply end to the control signal generation module according to the operation pulse signal and the address control signal so as to enable the control signal generation module to operate.
3. The row address decoding circuit of claim 2, wherein the power control module comprises:
The power supply control signal generating unit is used for receiving the operation pulse signal and the address control signal and generating a power supply control signal according to the operation pulse signal and the address control signal;
And the power switch unit is respectively connected with the power control signal generation unit, the control signal generation module and the power end and is used for receiving the power control signal and responding to the power control signal to transmit the power voltage to the control signal generation module.
4. The row address decoding circuit of claim 3, wherein the power control signal generating unit comprises:
The first input end of the OR gate receives the operation pulse signal, the second input end of the OR gate receives the address control signal, and the OR gate outputs the power supply control signal.
5. The row address decoding circuit of claim 1, wherein the control signal generation module comprises a decoding module; the address control signals include row address decoding signals;
the decoding module is used for receiving at least one address pre-decoding signal and generating a row address decoding signal according to the address pre-decoding signal.
6. The row address decoding circuit of claim 5, wherein the control signal generation module further comprises an other control signal generation module; the address control signals also include other control signals;
the other control signal generating module is configured to receive at least one address pre-decoding signal, and generate the other control signals according to the address pre-decoding signal.
7. The row address decoding circuit of claim 1, wherein the row address decoding circuit further comprises:
And the operation pulse generation module is used for receiving the initial operation signal and generating an operation pulse signal according to the initial operation signal.
8. The row address decoding circuit of claim 7, wherein the initial run signal is an activate command signal.
9. The row address decoding circuit of claim 7, wherein the run pulse generation module comprises:
the input end of the inverter receives the initial operation signal;
the input end of the delayer is connected with the output end of the inverter;
and the first input end of the AND gate receives the initial running signal, the second input end of the AND gate is connected with the output end of the delay device, and the AND gate outputs the running pulse signal.
10. A memory comprising a row address decoding circuit as claimed in any one of claims 1 to 9.
11. The memory of claim 10, wherein the memory further comprises: at least one memory bank;
At least one of the banks is disposed on at least one of two sides of the row address decoding circuit opposite in the first direction.
12. The memory of claim 11, wherein each of the banks comprises N memory segments; the row address decoding circuit comprises N storage address control circuits;
N storage segments are in one-to-one correspondence to receive the address control signals output by N storage address control circuits.
13. The memory of claim 10, wherein the memory further comprises:
and the pre-decoding module is used for receiving an initial running signal and a row address coding signal, pre-decoding the row address coding signal according to the initial running signal and obtaining at least one address pre-decoding signal.
14. The memory of claim 13, wherein the pre-decoding module comprises: a combinational logic circuit, a row fuse matching circuit and a row address pre-decoding circuit;
the combinational logic circuit is used for receiving an initial operation signal and an initial address signal and generating a pre-decoding driving signal corresponding to the initial address signal;
The row fuse matching circuit is used for receiving the initial address signal, performing matching and replacement of fuse addresses on the initial address signal, and transmitting the matched and replaced address signal to the row address pre-decoding circuit;
the row address pre-decoding circuit is respectively connected with the combinational logic circuit and the row fuse matching circuit and is used for receiving the pre-decoding driving signal and the matched and replaced address signals, pre-decoding the address signals and generating address pre-decoding signals.
15. The memory of claim 10, wherein the memory is a dynamic random access memory, DRAM.
CN202211241702.XA 2022-10-11 2022-10-11 Row address decoding circuit and memory Pending CN117912515A (en)

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