CN117912513A

CN117912513A - Method, device, equipment and medium for testing self-refresh frequency of memory

Info

Publication number: CN117912513A
Application number: CN202211249718.5A
Authority: CN
Inventors: 魏鹏飞; 张卫
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2022-10-12
Filing date: 2022-10-12
Publication date: 2024-04-19

Abstract

The disclosure provides a self-refresh frequency test method, device, equipment and medium for a memory, and relates to the technical field of semiconductors. The method comprises the following steps: obtaining a read-write test result of a memory to be tested, wherein the read-write test result comprises a plurality of groups of test data, each group of test data corresponds to the holding time length of a self-refresh command, each group of test data comprises at least one read-write state parameter, each read-write state parameter corresponds to the time delay time length of a self-refresh command, and each read-write state parameter represents the success or failure of reading and writing of the memory to be tested under the corresponding holding time length and the time delay time length; determining a plurality of reference holding time lengths based on a read-write test result, wherein each reference holding time length is a holding time length corresponding to a group of test data with read-write state parameters representing read-write failure; and determining the self-refresh frequency of the memory to be tested according to the plurality of reference holding time lengths. According to the embodiment of the disclosure, the test precision of the self-refresh frequency can be improved.

Description

Method, device, equipment and medium for testing self-refresh frequency of memory

Technical Field

The disclosure relates to the field of semiconductor technology, and in particular, to a method, a device, equipment and a medium for testing self-refresh frequency of a memory.

Background

Due to limitations such as manufacturing process, the charge on the gate capacitance of each memory cell tends to drain over time, and when the amount of charge is below a certain threshold, the data stored by the memory cell cannot be read correctly. Therefore, to prevent data loss, it is often necessary to supplement the charge lost over time on the gate capacitance of the memory cell by self-refresh. Therefore, the self-refresh frequency is an important parameter of the memory because it can reflect the power consumption and data retention capability of the memory. Accordingly, how to test the self-refresh frequency of a memory is one of the research directions in the field of semiconductor technology.

In one related art, the self-refresh frequency of a memory may be determined by measuring the power supply current waveform of the chip during self-refresh with an oscilloscope.

However, the self-refresh rate test accuracy of the related art is low, and thus, how to accurately detect the self-refresh rate of the memory becomes a problem to be solved.

It should be noted that the information disclosed in the above background section is only for enhancing understanding of the background of the present disclosure and thus may include information that does not constitute prior art known to those of ordinary skill in the art.

Disclosure of Invention

The present disclosure provides a method, apparatus, device, and medium for testing self-refresh frequency of a memory, which overcome, at least to some extent, the problem of low accuracy of testing self-refresh frequency of a memory.

Other features and advantages of the present disclosure will be apparent from the following detailed description, or may be learned in part by the practice of the disclosure.

According to one aspect of the present disclosure, there is provided a self-refresh frequency test method of a memory, including:

Obtaining a read-write test result of a memory to be tested, wherein the read-write test result comprises a plurality of groups of test data, each group of test data corresponds to the holding time length of a self-refresh command, each group of test data comprises at least one read-write state parameter, each read-write state parameter corresponds to the time delay time length of a self-refresh command, and each read-write state parameter represents the success or failure of reading and writing of the memory to be tested under the corresponding holding time length and the time delay time length;

Determining a plurality of reference holding time lengths based on a read-write test result, wherein each reference holding time length is a holding time length corresponding to a group of test data with read-write state parameters representing read-write failure;

And determining the self-refresh frequency of the memory to be tested according to the plurality of reference holding time lengths.

In one embodiment, determining the self-refresh frequency of the memory under test based on a plurality of reference retention periods comprises:

for a plurality of reference holding durations, determining a time interval between any two adjacent reference holding durations to obtain at least one self-refresh frequency value;

A self-refresh frequency of the memory under test is determined based on the at least one self-refresh frequency value.

In one embodiment, before obtaining the read-write test result of the memory to be tested, the method further includes:

Performing multiple self-refresh frequency tests on the memory to be tested to obtain read-write state parameters corresponding to the multiple self-refresh frequency tests, wherein each self-refresh frequency test corresponds to a holding time length and a delay time length, each self-refresh frequency test is used for generating one read-write state parameter,

Wherein, in each self-refresh frequency test, the following steps are performed:

Controlling the memory to be tested to enter a self-refresh state;

controlling the memory to be tested to exit from the self-refresh state under the condition that the real-time holding time length of the self-refresh state reaches the holding time length corresponding to the self-refresh frequency test;

under the condition that the duration of exiting the self-refresh state reaches the time delay duration corresponding to the self-refresh frequency test, writing test data into a memory to be tested;

reading data in the memory to be tested, which is written with the test data, to obtain read data;

based on whether the test data and the read-out data are the same, generating the read-write state parameters corresponding to the self-refresh frequency test.

In one embodiment, controlling the memory under test to enter a self-refresh state includes:

Sending a self-refresh entry command to the memory to be tested, so that the memory to be tested enters a self-refresh state in response to the self-refresh entry command;

and/or the number of the groups of groups,

Controlling the memory to be tested to exit the self-refresh state, comprising:

And sending a self-refresh exit command to the controller to be tested so that the memory to be tested exits from the self-refresh state in response to the self-refresh exit command.

In one embodiment, the memory to be tested includes a plurality of control signal terminals,

Sending a self-refresh entry command to a memory under test, comprising:

For each control signal terminal, determining a first target level state corresponding to a self-refresh entry command according to a preset standard protocol;

for each control signal end, setting the actual level state of the control signal end as a first target level state corresponding to the control signal end, so that the memory to be tested can determine that a self-refresh entry command is received based on the actual level states of a plurality of control signal ends;

and/or the number of the groups of groups,

Sending a self-refresh exit command to a controller under test, comprising:

determining a second target level state corresponding to the self-refresh exit command according to a preset standard protocol for each control signal end;

And setting the actual level state of each control signal end to be a second target level state corresponding to the control signal end aiming at each control signal end, so that the memory to be tested can determine that the self-refresh exit command is received based on the actual level states of a plurality of control signal ends.

In one embodiment, writing test data into the memory under test when the duration of exiting the self-refresh state reaches a time delay duration corresponding to the current self-refresh frequency test includes:

When the duration of the self-refresh state is up to the time delay duration corresponding to the self-refresh frequency test, a read-write control command is sent to the memory to be tested, which is out of the self-refresh state, so as to control the memory to be tested to write test data through the read-write control command.

In one embodiment, the plurality of self-refresh rate tests are divided into a plurality of groups, each of the plurality of self-refresh rate tests corresponding to a same retention period;

The method further comprises the steps of after data reading is carried out on the memory to be tested written with the test data to obtain read data:

judging whether the self-refresh frequency test of the group is finished or not;

Under the condition that the self-refresh frequency test is not completed, updating the time delay duration corresponding to the self-refresh frequency test to obtain the time delay duration corresponding to the next refresh frequency test, and executing the next self-refresh frequency test based on the time delay duration corresponding to the next refresh frequency test;

Under the condition that the self-refresh frequency test of the group is completed, updating the holding time length corresponding to the self-refresh frequency test of the group to obtain the holding time length corresponding to each self-refresh frequency test in the self-refresh frequency test of the group, and executing each self-refresh frequency test in the self-refresh frequency test of the group based on the holding time length corresponding to each self-refresh frequency test in the self-refresh frequency test of the group.

In one embodiment, before controlling the memory under test to enter the self-refresh state, the method further comprises:

Writing background data into a memory to be tested;

wherein, control the memory to be measured to enter the self-refresh state, include:

And controlling the memory to be tested, in which the background data are written, to enter a self-refresh state.

In one embodiment, the read-write test results include: read-write test results corresponding to a plurality of test amounts under the test factors of the preset self-refresh frequency respectively;

based on the read-write test results, determining a plurality of reference hold durations, including:

For each test amount, determining a plurality of reference holding periods corresponding to the test amount;

determining the self-refresh frequency of the memory to be tested according to the plurality of reference holding durations, comprising:

and determining the self-refresh frequency of the memory to be tested under the plurality of test amounts based on the plurality of reference holding time lengths corresponding to the plurality of test amounts.

In one embodiment, the preset self-refresh frequency test factors include:

The ambient temperature of the memory to be measured and/or the type of memory to be measured.

In one embodiment, after determining the self-refresh frequency of the memory under test based on the plurality of reference retention periods, the method further comprises:

Acquiring a self-refresh frequency standard value specified by a preset standard protocol;

Based on the determined self-refresh frequency and the self-refresh frequency specification value, a verification result of the self-refresh function of the memory is obtained, and the verification result characterizes whether the self-refresh function of the memory is abnormal.

In one embodiment, determining a plurality of reference retention periods based on read-write test results includes:

Generating a shmoo test chart based on a read-write test result, wherein the shmoo test chart comprises a plurality of image sequences, each image sequence corresponds to a group of test data in the read-write test result, each image sequence comprises at least one image unit, each image unit corresponds to a read-write state parameter, and each image unit is provided with a visual identifier which is used for identifying success or failure of reading and writing;

a plurality of reference retention periods are determined based on the shmoo plot.

According to another aspect of the present disclosure, there is provided a self-refresh frequency test device of a memory, including:

the device comprises a result acquisition module, a data processing module and a data processing module, wherein the result acquisition module is used for acquiring a read-write test result of a memory to be tested, the read-write test result comprises a plurality of groups of test data, each group of test data corresponds to the holding time length of a self-refresh command, each group of test data comprises at least one read-write state parameter, each read-write state parameter corresponds to the time delay time length of a self-refresh command, and each read-write state parameter is used for representing the success or failure of reading and writing of the memory to be tested under the corresponding holding time length and the time delay time length;

the time length determining module is used for determining a plurality of reference holding time lengths based on the read-write test result, wherein each reference holding time length is a holding time length corresponding to a group of test data with read-write state parameters representing read-write failure;

and the frequency determining module is used for determining the self-refresh frequency of the memory to be tested according to the plurality of reference holding time lengths.

According to still another aspect of the present disclosure, there is provided an electronic apparatus including: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the self-refresh frequency test method of the memory described above via execution of the executable instructions.

According to still another aspect of the present disclosure, there is provided a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements the self-refresh frequency test method of a memory described above.

According to yet another aspect of the present disclosure, there is provided a computer program product comprising a computer program which, when executed by a processor, implements the above-described method of self-refresh frequency testing of a memory.

The method, the device, the equipment and the medium for testing the self-refresh frequency of the memory can acquire the read-write test result of the memory to be tested, wherein multiple groups of test data of the read-write test result correspond to the holding time lengths of different self-refresh commands, and each group of test data comprises at least one read-write state data corresponding to the time delay time lengths of different self-refresh commands. Since the memory will be refreshed at least once in the self-refresh mode, if the refresh is not completed when the hold time and the delay time are reached, the read-write failure will be caused. Accordingly, with the change of the holding time of the self-refresh command of the memory and the change of the time delay time of exiting the self-refresh command, the memory will have a read-write failure during each self-refresh, so that the reference holding time corresponding to the read-write status parameter indicating the read-write failure can accurately indicate the self-refresh frequency of the memory to be tested. Accordingly, the self-refresh frequency of the memory can be accurately determined through the plurality of reference holding time lengths, and the detection accuracy of the self-refresh frequency is improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the disclosure and together with the description, serve to explain the principles of the disclosure. It will be apparent to those of ordinary skill in the art that the drawings in the following description are merely examples of the disclosure and that other drawings may be derived from them without undue effort.

FIG. 1 illustrates a system architecture diagram of a storage system provided by an embodiment of the present disclosure;

FIG. 2 shows a schematic diagram of a self-refresh process provided by an embodiment of the present disclosure;

FIG. 3 shows a flow diagram of a self-refresh process provided by an embodiment of the present disclosure;

FIG. 4 illustrates an exemplary shmoo plot provided by an embodiment of the disclosure;

FIG. 5 is a flow chart of a method for testing the self-refresh rate of a memory according to an embodiment of the disclosure;

FIG. 6 illustrates another exemplary shmoo plot provided by an embodiment of the disclosure;

FIG. 7 illustrates yet another exemplary shmoo plot provided by an embodiment of the disclosure;

FIG. 8 illustrates yet another exemplary shmoo plot provided by an embodiment of the disclosure;

FIG. 9 is a flow chart illustrating another method for testing the self-refresh rate of a memory according to an embodiment of the disclosure;

FIG. 10 is a flow chart illustrating another method for testing the self-refresh rate of a memory according to an embodiment of the disclosure;

FIG. 11 illustrates a schematic diagram of an operational command in an exemplary self-refresh test provided by an embodiment of the present disclosure;

FIG. 12 is a schematic diagram of a self-refresh frequency test device for a memory according to an embodiment of the disclosure;

FIG. 13 shows a block diagram of an electronic device in an embodiment of the disclosure; and

Fig. 14 shows a schematic diagram of a computer-readable storage medium in an embodiment of the disclosure.

Detailed Description

Example embodiments will now be described more fully with reference to the accompanying drawings. However, the exemplary embodiments may be embodied in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

Furthermore, the drawings are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale. The same reference numerals in the drawings denote the same or similar parts, and thus a repetitive description thereof will be omitted. Some of the block diagrams shown in the figures are functional entities and do not necessarily correspond to physically or logically separate entities. These functional entities may be implemented in software or in one or more hardware modules or integrated circuits or in different networks and/or processor devices and/or microcontroller devices.

It should be understood that the various steps recited in the method embodiments of the present disclosure may be performed in a different order and/or performed in parallel. Furthermore, method embodiments may include additional steps and/or omit performing the illustrated steps. The scope of the present disclosure is not limited in this respect.

It should be noted that the terms "first," "second," and the like in this disclosure are merely used to distinguish between different devices, modules, or units and are not used to define an order or interdependence of functions performed by the devices, modules, or units. And, the modification of "a", "an", and "the" are intended to be illustrative rather than limiting, and those of ordinary skill in the art will understand that "one or more" is intended to be interpreted as "one or more" unless the context clearly indicates otherwise.

Memories such as dynamic random access memory (Dynamic Random Access Memory, DRAM) tend to have data volatility. Thus, the memory can maintain data in the memory in a self-refresh manner in scenarios such as system power down abnormally and system entry into a low power mode.

In one related art, the self-refresh frequency of the memory may be tested by measuring the power supply current waveform of the memory during self-refresh with an oscilloscope (SELF REFRESH RATE).

However, this related art has at least one of the following problems.

(1) And the accuracy requirement on the current source is high, and a high-resolution oscilloscope is required to test the current waveform.

(2) When the current waveform frequency is high, the refresh frequency may not be accurately tested because the current waveforms of adjacent refresh cycles overlap.

(3) The oscilloscope and the memory need to be welded manually, and when the power transmission circuit generates noise, noise signals can generate interference on current waveforms.

(4) When the self-refresh frequency of the memory is high, current waveforms of adjacent refresh cycles at least partially overlap, and it is difficult to distinguish the refresh cycles, so that the self-refresh frequency cannot be accurately tested.

In another related art, the self-refresh frequency of a memory may be measured using the relationship of the self-refresh time and the data retention capability.

However, the related art has problems such as complicated testing method, low testing accuracy, and the like.

In order to facilitate the overall understanding of the technical solutions of the embodiments of the present disclosure, before starting to introduce the technical solutions of the embodiments of the present disclosure, the findings of the inventors will be described with reference to fig. 1 and fig. 2.

Fig. 1 illustrates a system architecture diagram of a storage system provided by an embodiment of the present disclosure. Fig. 2 shows a schematic diagram of a self-refresh process provided by an embodiment of the present disclosure. As shown in fig. 1, the memory system 10 may include a controller 11 and a memory under test 12.

The inventors found through studies that the controller 11 can control the memory 12 to be tested by sending instructions. Illustratively, as shown in FIG. 2, the controller 11 may send a self-refresh entry command M1 to the memory under test 12. After receiving the self-refresh entry command M1, the memory 12 to be tested enters a self-refresh mode, and performs one or more self-refresh operations on each memory module (bank) in the self-refresh mode. After the retention period tSR of the self-refresh command elapses, the controller 11 transmits a self-refresh exit command M2 to the memory under test 12, and the memory under test 11 exits the self-refresh mode in response to the self-refresh exit command. After the lapse of the delay period tXSR of the self-refresh command from the start of the transmission of the self-refresh exit command M2, the controller 11 transmits a read-write control command M3 such as an Activate (ACT) command to the memory 12 under test. If the memory 12 to be tested successfully exits the self-refresh mode, the read/write operation can be performed in response to the read/write control command M3. And if the memory 12 to be tested does not successfully exit the self-refresh mode, the read-write control command M3 cannot be effectively responded, and further the read-write failure is caused.

Illustratively, fig. 3 shows a schematic flow diagram of a self-refresh process provided by an embodiment of the present disclosure. As shown in fig. 3, after the self-refresh mode is entered, the memory under test begins to enter a refresh state. After one refresh is finished, the memory enters an idle state, then the next refresh is started after a certain time interval, and the process is repeated until the memory to be tested receives a self-refresh exit command. In one example, as indicated by the arrows shown by the dashed lines in fig. 3 and the arrows filled with patterns, if the memory to be tested issues a self-refresh exit command and a read-write control command during the refresh process, invalid read-write may be caused, and thus the read-write may fail. And as shown by black filled arrows in fig. 3, if the memory to be tested receives the self-refresh exit command and the read-write control command after the single refresh is finished, normal read-write can be performed on the memory to be tested, and the read-write is successful.

Based on this, the embodiments of the present disclosure provide a method, an apparatus, a device, and a medium for testing a self-refresh frequency of a memory, where the self-refresh frequency of the memory to be tested can be accurately represented by a reference retention period corresponding to a read-write status parameter indicating a read-write failure, so that the self-refresh frequency of the memory to be tested can be accurately determined by the retention period of a self-refresh command and a delay period for exiting the self-refresh command, and the detection accuracy of the self-refresh frequency is improved.

Before starting to describe the technical scheme provided by the embodiments of the present disclosure, technical terms related to the embodiments of the present disclosure are described.

(1) The hold duration (tXR) of the self-refresh command, which may, for example, characterize the minimum time that the self-refresh needs to be held.

In the disclosed embodiments, this may refer to the duration of the interval from the issue of the self-refresh entry command to the issue of the self-refresh exit command.

(2) The delay time (Exit Self-REFRESH DELAY TIME, TXSR) for exiting the Self-refresh command, i.e. the time that needs to wait after exiting the Self-refresh command, is longer than the time that the valid command can be sent.

In the embodiments of the present disclosure, it may refer to an interval time from issuing a self-refresh exit command to issuing a read-write control command.

(3) A Row address refresh period (Row REFRESH CYCLE TIME, TRFC) that defines the period time required to refresh all memory block (Bank) Row addresses. Illustratively, since the memory is a volatile memory, the charge of the capacitor in the memory cell (cell) is gradually lost, and thus the memory is refreshed at intervals for the row address of a Bank or banks in order to maintain the integrity of the data.

(4) The shmoo plot, a type of graph that can be obtained by a shmoo plot tool, can be used to analyze and evaluate the actual capabilities of the memory. The shmoo plot may include a plurality of image units that have visual identifiers that visually indicate success or failure of reading and writing.

Illustratively, fig. 4 shows an exemplary shmoo plot provided by an embodiment of the disclosure. Wherein the abscissa represents tXR (in microseconds (us)) and the ordinate represents tXSR (in us). Wherein the arrow indicates the direction of time increase.

Wherein each rectangular box in fig. 4 represents one image unit, and a plurality of image units in the column direction represent one image sequence, each image sequence corresponding to one tSR. Different picture elements on the same column correspond to different tXSR. And the black image unit identification memory fails to read and write under tXR and tXSR corresponding to the image unit, and the white image unit identification memory succeeds in reading and writing under tXR and tXSR corresponding to the image unit.

In the disclosed embodiment, as shown in fig. 4, after the memory starts to enter the self-refresh state at stage ①, if the hold period tXR of the self-refresh command is too short to meet the self-refresh time requirement, the memory continues to refresh after receiving the self-refresh exit command, and if the self-refresh is not completed before the next command (read-write control command) is reached, the command is invalidated, resulting in a read-write failure. At stage ②, as tXR increases, if tSR or the delay duration tXSR of the self-refresh command is sufficient, the memory can complete the refresh when the next command is reached, i.e. the read/write is successful. At stage ③, with a further increase in tXR, the memory is refreshed again, starting from the point in time when the refresh was entered a second time, if the refresh process is not completed until the self-refresh exit command and the next command are received, then the command is invalidated, resulting in a read-write failure.

Having described the technical terms above, the present exemplary embodiment will be described in detail below with reference to the accompanying drawings and examples.

Embodiments of the present disclosure provide a method for testing a self-refresh frequency of a memory, which may be performed by any electronic device having data processing capabilities.

Fig. 5 is a flowchart illustrating a method for testing the self-refresh frequency of a memory according to an embodiment of the disclosure, and as shown in fig. 5, the method for testing the self-refresh frequency of the memory according to the embodiment of the disclosure includes the following steps S510 to S530.

S510, obtaining a read-write test result of the memory to be tested.

For the memory under test, it may be a memory that requires a self-refresh frequency test. Illustratively, the memory may be any one of dynamic random access memories such as a fourth generation double-rate synchronous dynamic random access memory (DDR 4 SDRAM), a fourth generation low power consumption double-rate synchronous dynamic random access memory (LPDDR 4 SDRAM), a fifth generation double-rate synchronous dynamic random access memory (DDR 5 SDRAM), a fifth generation low power consumption double-rate synchronous dynamic random access memory (LPDDR 5 SDRAM), etc., which is not particularly limited. The memory may be a memory other than a dynamic random access memory, and is not particularly limited.

And for the read-write test result, the read-write test result is used for representing the change result of the read-write state (read-write success or read-write failure) along with the holding time length of the self-refresh command and the time delay time length of the self-refresh command. Specifically, the method may include multiple sets of test data, where each set of test data corresponds to a retention period of a self-refresh command, each set of test data includes at least one read-write state parameter, each read-write state parameter corresponds to a delay period for exiting the self-refresh command, and each read-write state parameter is used for indicating that the memory to be tested is successfully read and written under the corresponding retention period and delay period or for indicating that the memory to be tested is failed to read and write under the corresponding retention period and delay period.

For example, if a set of test data to which a certain read-write status parameter belongs corresponds to a retention period tXR of the self-refresh command and the read-write status parameter corresponds to a delay period tXSR of exiting the self-refresh command, the read-write status parameter characterizes that the memory to be tested is successfully read or fails to read when the retention period of the self-refresh command is tXR1 and the delay period of exiting the self-refresh command is tXSR.

And, as for the read-write test result of the memory to be tested, it may include the read-write test result of at least one memory module (bank) of the memory to be tested, without specific limitation.

After step S510 is described by the memory under test and the read/write test result, S520 is described next.

In some embodiments, the sum of the hold time of the self-refresh command and the latency time of the self-refresh command is less than or equal to the row address refresh period tRFC. The row address refresh period tRFC characterizes the minimum time that the data refresh is valid.

In this embodiment, by controlling the holding time of the self-refresh command and the delay time of the self-refresh command, it is ensured that the write command is an effective command, and further, the accuracy of the test result is ensured.

S520, determining a plurality of reference holding time periods based on the read-write test result.

The reference holding time periods are holding time periods corresponding to a group of test data with read-write status parameters (hereinafter referred to as read-write failure status parameters) representing read-write failure. For example, with continued reference to fig. 4, if the first several sets of test data have parameters indicating the status of failed reading and writing, one holding duration may be selected from holding durations corresponding to the first several sets of test data as the reference holding duration.

In some embodiments, to ensure accuracy of the test results, a reference retention period may represent a retention period corresponding to a set of test data in which a read-write failure status parameter occurs in a self-refresh cycle. Illustratively, fig. 6 shows another exemplary shmoo test plot provided by an embodiment of the disclosure. As shown in fig. 6, the holding period T11 of the self-refresh command may be selected as a first reference holding period, and the holding period T12 of the self-refresh command may be selected as a second reference holding period.

In one embodiment, if the read-write failure state parameter exists in all the continuous multiple sets of test data or the interval between the test data with the read-write failure state parameter is smaller than the preset data interval threshold, the holding duration corresponding to one set of test data may be selected as the reference holding duration according to a preset selection rule. The preset selection rule may be to select a holding time length corresponding to the last test data with the read-write failure status parameter as a reference holding time length, or select a holding time length corresponding to the test data in the middle position as a reference holding time length, which is not specifically limited.

In another embodiment, if the intervals between the consecutive sets of test data and the read-write status data representing the read-write failure or the test data having the read-write failure status parameter are smaller than the preset data interval threshold, the average value of the holding durations corresponding to the sets of test data may be used as a reference holding duration.

It should be noted that, the reference holding time period may also be selected according to other manners, for example, the holding time period corresponding to the test data with the read-write failure status parameter is taken as the preliminary reference holding time period, then the abnormal data is screened out by counting the time intervals between other adjacent reference holding time periods, and the screened reference holding time period is obtained, which is not limited specifically.

After the reference holding period is described, a specific embodiment of S520 will be described next.

In some embodiments, the plurality of reference retention periods may be derived based on a shmoo plot corresponding to the read-write test result. Accordingly, S520 may include the following steps A1 and A2.

And A1, generating a shmoo plot based on a read-write test result.

In step A1, the shmoo plot includes a plurality of image sequences, each image sequence corresponds to a set of test data in the read-write test result, each image sequence includes at least one image unit, each image unit corresponds to a read-write status parameter, and each image unit has a visual identifier, where the visual identifier is used to identify whether the read-write is successful or failed.

It should be noted that, for details of the shmoo plot, reference may be made to the above-mentioned portions of the embodiments of the disclosure and the related descriptions of fig. 4, which are not repeated herein.

Wherein for the visual identification it is used to visually identify different read-write status parameters. For example, the first visual identifier is used for identifying that the reading and writing are successful, and the second visual identifier is used for identifying that the reading and writing are failed. In some embodiments, the visual identifier may be a filling pattern, text, color, icon, or other visual identifier with an identifying effect, which is not particularly limited. For example, the read-write failure may be identified with red, and the read-write success may be identified with green.

And step A2, determining a plurality of reference holding time periods based on the shmoo test chart.

In one embodiment, with continued reference to fig. 6, after the shmoo plot is acquired, a first reference hold period T11 and a second reference hold period T12 may be determined based on boundaries between image units that correspond to different visual identifications.

It should be noted that, a specific manner how to determine the reference holding time may be referred to the related description of the reference holding time in the foregoing embodiments of the present disclosure, which is not repeated herein.

Through the step A1 and the step A2, the self-refreshing capability of the memory to be tested can be accurately evaluated through the shmoo test chart, the correlation between the retention time tSR of the self-refreshing command, the delay time tXSR for exiting the self-refreshing command and the read-write state can be intuitively displayed, the reference retention time can be accurately determined through the boundaries between the image units corresponding to different visual identifications, the self-refreshing frequency of the memory to be tested is accurately determined, and the testing precision and the ordering of the self-refreshing frequency are ensured.

In other embodiments, after the read-write test result is obtained, background data processing may be performed on the read-write test result to obtain a plurality of reference holding durations.

The specific manner how to determine the reference retention time may be referred to the relevant description of the reference retention time in the foregoing embodiments of the disclosure, which is not repeated herein.

After S520 is introduced, S530 is continued.

S530, determining the self-refresh frequency of the memory to be tested according to the plurality of reference holding time periods.

In S530, after the plurality of reference holding periods are acquired, the self-refresh frequency of the memory to be tested may be obtained by means of data processing.

In some embodiments, S530 may include the following steps A3 and A4.

And A3, determining the time interval between any two adjacent reference holding time periods for a plurality of reference holding time periods to obtain at least one self-refresh frequency value.

Illustratively, with continued reference to fig. 6, after the first reference retention period T11 and the second reference retention period T12 are acquired, a time interval therebetween may be calculated, resulting in a self-refresh frequency value F11. For example, if the time interval between the first reference holding period T11 and the second reference holding period T12 is 57.75us, the self-refresh frequency value F11 is 57.75us.

And step A4, determining the self-refresh frequency of the memory to be tested based on at least one self-refresh frequency value.

In one embodiment, if the number of self-refresh rate values is 1, the self-refresh rate value may be used as the self-refresh rate of the memory under test. For example, with continued reference to FIG. 6, the self-refresh frequency value F11 may be taken as the self-refresh frequency of the memory under test.

In another embodiment, if the number of self-refresh frequency values is an integer greater than or equal to 2, the self-refresh frequency of the memory under test may be determined from the plurality of self-refresh frequency values.

In one example, step A4 may include step a41 described below.

Step A41, a mean value of a plurality of self-refresh frequency values can be calculated to obtain the self-refresh frequency of the memory to be tested.

By means of the step a41, the calculation accuracy of the self-refresh frequency can be improved by means of calculating the mean value.

In another example, step A4 may include step a42 and step a43 described below.

And step A42, analyzing and processing the self-refresh frequency values to determine the occurrence times corresponding to the self-refresh frequency values. For example, a statistical analysis may be performed on the plurality of refresh frequencies to obtain the number of occurrences corresponding to each of the plurality of refresh frequency values.

And step A43, determining the self-refresh frequency value corresponding to the maximum occurrence number as the self-refresh frequency value of the memory to be tested.

Through the step A42 and the step A43, the influence of the abnormal self-refresh frequency value on the calculation result can be eliminated, so that the calculation accuracy of the self-refresh frequency value is improved.

In yet another example, step A4 may include step a44 described below.

Step a44, after calculating the time interval between the previous reference holding duration and the current reference holding duration, may determine whether the time interval is outside the preset reasonable value range, if so, may use the time interval as a self-refresh frequency value, and if so, may reject the time interval.

The preset reasonable value range may be set according to an actual scene and specific requirements, for example, may be an empirical value, which is not limited in particular.

In yet another example, step A4 may include step a45 described below.

Step A45, determining the self-refresh frequency of the memory to be tested according to the distribution characteristics of the self-refresh frequency values. For example, the gaussian distribution characteristics thereof may be determined, etc., and there is no particular limitation.

It should be noted that, after at least one self-refresh frequency value is obtained, the self-refresh frequency of the memory to be tested may also be calculated according to other data processing methods, which will not be described in detail.

Through the above steps A3 and A4, at least one self-refresh frequency value can be accurately obtained based on the time intervals between the plurality of reference holding periods. And the self-refresh frequency of the memory to be tested can be determined according to at least one self-refresh frequency value, so that the calculation accuracy of the self-refresh frequency value can be accurately calculated.

It should be noted that, other manners may be adopted to determine the self-refresh frequency of the memory to be tested according to the periodic variation rule among the multiple reference holding periods, which is not limited in particular.

According to the self-refresh frequency test method for the memory, the read-write test result of the memory to be tested can be obtained, wherein multiple groups of test data of the read-write test result correspond to the holding time lengths of different self-refresh commands, and each group of test data comprises at least one read-write state data corresponding to the time delay time lengths of different self-refresh commands. Since the memory will be refreshed at least once in the self-refresh mode, if the refresh is not completed when the hold time and the delay time are reached, the read-write failure will be caused. Accordingly, with the change of the holding time of the self-refresh command of the memory and the change of the time delay time of exiting the self-refresh command, the memory will have a read-write failure during each self-refresh, so that the reference holding time corresponding to the read-write status parameter indicating the read-write failure can accurately indicate the self-refresh frequency of the memory to be tested. Accordingly, the self-refresh frequency of the memory can be accurately determined through the plurality of reference holding time lengths, and the detection accuracy of the self-refresh frequency is improved.

And the self-refresh frequency testing method of the memory provided by the embodiment of the disclosure can realize the detection of the self-refresh frequency without using extra testing equipment such as a high-resolution oscilloscope and the like, thereby improving the detection precision, saving the detection cost and reducing the complexity of the test.

And the self-refresh frequency testing method of the memory provided by the embodiment of the disclosure can finish the self-refresh frequency testing of the memory without knowing the internal design information of the memory to be tested, thereby improving the universality of the self-refresh frequency testing method and realizing the analysis of various memories to be tested.

It should be noted that fig. 7 shows still another exemplary shmoo test chart provided by an embodiment of the disclosure, and fig. 8 shows still another exemplary shmoo test chart provided by an embodiment of the disclosure.

Fig. 7 shows a shmoo plot at an ambient temperature of 70 degrees celsius (°c), with a plurality of Self-refresh frequency values F21 to F26 of 10.7us, 10.175us, 10.175us, 10.45us, 10.175us, 10.45us, respectively, measured by a plurality of reference hold periods T21 to T27, and with a known Self-refresh frequency interval (Self-REFRESH INTERVAL) N of 10 at 70 ℃, the Self-refresh frequency specification value calculated by the calculation of "57.75 us/(54/N)" is 10.6us, which matches the plurality of Self-refresh frequency values F21 to F26 measured.

And, fig. 8 shows a shmoo plot at an ambient temperature of 90 degrees celsius (°c), and a plurality of self-refresh frequency values F31 to F39 obtained by testing for a plurality of reference holding periods T30 to T39 are 6.6us, 6.875us, 6.6us, 6.875us, 6.15us, 7.3us, respectively, and the self-refresh frequency specification value calculated by "57.75 us/(54/N)" is 6.41us, which matches the plurality of self-refresh frequency values F31 to F39 obtained by testing, given that N is 10 at 90 ℃.

As can be seen from fig. 7 and 8, the method for testing the self-refresh frequency of the memory according to the embodiments of the present disclosure measures the accuracy of the self-refresh frequency.

In some embodiments, the read-write test result may include a read-write test result corresponding to each of a plurality of test amounts under a preset self-refresh frequency test factor.

For a preset self-refresh frequency test factor, it may refer to a factor that affects the self-refresh frequency.

In one embodiment, the preset self-refresh frequency test factors may include, but are not limited to, an ambient temperature of the memory under test and/or a type of the memory under test. For example, in the case where the preset self-refresh frequency test factor includes an ambient temperature, the plurality of test amounts may be a plurality of ambient temperature values. For another example, in the case where the preset self-refresh frequency test factor includes a type, the plurality of test amounts may include a plurality of memory models. By the embodiment, the self-refresh frequency of the memory under different environment temperatures can be tested, and/or the self-refresh frequency of different types of memories can be tested, so that comprehensive analysis can be performed on the self-refresh performance of the memory to be tested.

Accordingly, in the case where the read-write test result may include the read-write test result corresponding to each of the plurality of test amounts under the preset self-refresh frequency test factor, S520 may include the following step A5, and S530 may include the following step A6.

And step A5, determining a plurality of reference holding time periods corresponding to each test quantity according to each test quantity.

In step A5, for each test amount, a plurality of reference holding periods corresponding to the test amount may be calculated in step S520 described above.

By way of example, with continued reference to fig. 7, a plurality of reference hold durations T21 to T27 may be determined at 70 ℃.

Still further exemplary, with continued reference to fig. 8, a plurality of reference hold durations T30 through T39 may be determined at 90 ℃.

And step A6, determining the self-refreshing frequency of the memory to be tested under a plurality of test quantities based on a plurality of reference holding time lengths corresponding to the test quantities.

In step A6, for each test amount, the self-refresh frequency of the memory under test at that test amount can be determined by step S530 described above.

By way of example, with continued reference to FIG. 7, the self-refresh frequency of the memory under test at 70℃may be determined from a plurality of self-refresh frequency values F21 through F26 at 70 ℃.

Still another example, with continued reference to FIG. 8, the self-refresh frequency of the memory under test at 90℃may be determined from a plurality of self-refresh frequency values F30 through F39 at 90 ℃.

Through the step A5 and the step A6, the self-refresh frequency of the memory to be tested under different test amounts can be verified, thereby improving the flexibility and the comprehensiveness of self-refresh frequency calculation,

In some embodiments, after S530, the self-refresh frequency test method of the memory may further include the following steps B1 and B2.

And step B1, acquiring a self-refresh frequency specification value specified by a preset standard protocol.

In step B1, the preset standard protocol may be a protocol that specifies a format of the refresh command. By way of example, a Joint Electron DEVICE ENGINEERING countil, JEDEC standard protocol may be used. It should be noted that other standard protocols are also possible, and the present invention is not limited in particular.

The self-refresh frequency standard value is a specified value of a preset standard protocol for self-refresh frequency.

In one embodiment, step B1 may include: the self-refresh frequency specification value is obtained from a mode register of the memory under test.

It should be noted that the self-refresh frequency specification value may be obtained in other manners, which is not particularly limited.

In another embodiment, step B1 may include: the self-refresh frequency interval N of the memory to be tested under the current test quantity is determined, and then the self-refresh frequency standard value is calculated according to 57.75 us/(54/N).

Illustratively, the self-refresh frequency interval N specified by the preset standard protocol may be as shown in table 1.

TABLE 1

Temperature (. Degree. C.)	-6	70	90
				Self-refresh frequency interval N	54	10	6

As shown in table 1, at-6 ℃, N specified by a preset standard protocol may be 54; at 70 ℃, N specified by a preset standard protocol can be 10; at 90 c, N as specified by the preset standard protocol may be 6. It should be noted that, N specified by the preset standard protocol may be set to other values according to different protocol versions, and the specific value of N is not limited.

And step B2, obtaining a verification result of the self-refresh function of the memory based on the determined self-refresh frequency and the self-refresh frequency specification value. Wherein the verification result characterizes whether the self-refresh function of the memory is abnormal.

In one embodiment, step B2 may include: and determining whether the absolute difference value of the self-refresh frequency and the self-refresh frequency standard value is smaller than or equal to a preset difference value tolerance threshold value or not to determine a verification result. The preset difference tolerance threshold value characterizes tolerance of error of self-refresh frequency, which can be set according to practical situation and specific requirement, for example, can be an empirical value or a fixed value, and is not limited in particular.

For example, if the absolute difference between the self-refresh frequency and the self-refresh frequency specification value is less than or equal to the preset difference tolerance threshold, a first verification result indicating that the self-refresh function is normal may be obtained. And if the absolute difference between the self-refresh frequency and the self-refresh frequency specification value is greater than the preset difference tolerance threshold, obtaining a second verification result representing the self-refresh function abnormality.

In one example, where the read-write test result may include read-write test results corresponding to each of a plurality of test amounts under the preset self-refresh frequency test factor, verification results for different test amounts may be obtained. For example, the results of the respective verifications at 70℃and 90℃can be verified.

Through the steps B1 and B2, the self-refresh characteristic of the memory to be tested can be effectively verified, so that the self-refresh characteristic of the memory to be tested can be accurately detected abnormally, and the self-refresh performance of the memory to be tested is further ensured.

Fig. 9 is a flowchart illustrating another method for testing the self-refresh frequency of a memory according to an embodiment of the disclosure. Embodiments of the present disclosure may be optimized based on the embodiments described above, and may be combined with various alternatives of one or more of the embodiments described above.

As shown in fig. 9, the self-refresh frequency test method of the memory may include the following steps S910 to S940.

S910, performing multiple self-refresh frequency tests on the memory to be tested to obtain read-write state parameters corresponding to the multiple self-refresh frequency tests. Wherein each self-refresh rate test corresponds to a retention period and a delay period, each self-refresh rate test being used to generate a read-write status parameter.

In this case, with continued reference to fig. 9, in each self-refresh frequency test, the following steps S911 to S915 are performed.

S911, controlling the memory to be tested to enter a self-refresh state. Illustratively, fig. 10 shows a flow chart of an exemplary method for testing the self-refresh frequency of a memory according to an embodiment of the present disclosure. As shown in S1002, a self-refresh state may be entered.

In some embodiments, the memory under test may be controlled to enter a self-refresh state by a self-refresh entry command. Accordingly, S911 may include the following step C1.

Step C1, a self-refresh entry command is sent to the memory to be tested, so that the memory to be tested enters a self-refresh state in response to the self-refresh entry command.

In step C1, the self-refresh rate test device of the memory may directly send a self-refresh entry command to the memory under test, or send a self-refresh entry command to the memory under test through the controller, which is not particularly limited.

The self-refresh entry command is used for indicating the memory to be tested to enter a self-refresh state. In one embodiment, FIG. 11 illustrates a schematic diagram of an operational command in an exemplary self-refresh test provided by embodiments of the present disclosure. As shown in fig. 11, the self-refresh entry command may include a first self-refresh entry sub-command SREFH and a second self-refresh entry sub-command SREFL.

In one embodiment, the memory to be tested includes a plurality of control signal terminals, and step C1 may include step C11 and step C12.

Step C11, determining a first target level state corresponding to the self-refresh entry command according to a preset standard protocol for each control signal terminal.

Illustratively, the first target level state corresponding to the self-refresh entry command may include: the level states of physical ports CA0-CA 4. For example, the level states of the physical ports CA0-CA4 corresponding to the first self-refresh entry subcommand SREFH are low, high. The second self-refresh entry sub-command SREFL does not require the level states of the physical ports CA0-CA 4.

In another example, the first target level state corresponding to the self-refresh entry command may include: a high state of the clock enable signal CKE, the chip select signal pin cs_n, the row address signal pin ras_n, the column address signal pin cas_n, a low state of the active signal pin act_n, the write enable signal pin we_n.

And step C12, setting the actual level state of each control signal end to be a first target level state corresponding to the control signal end, so that the memory to be tested can determine that a self-refresh entry command is received based on the actual level states of a plurality of control signal ends.

For example, physical ports CA0-CA2 may be set low and physical ports CA3-CA4 may be set high.

Through the steps C11 and C12, the memory to be tested can be accurately controlled to enter the self-refresh state through the control signal end, and therefore the test precision of the self-refresh frequency is improved.

Through the step C1, the memory to be tested can be controlled to enter a self-refresh state through a common working command specified by a preset standard protocol, and then the self-refresh frequency can be accurately tested through the common working command, so that the test cost and the test complexity are reduced.

S912, controlling the memory to be tested to exit from the self-refresh state under the condition that the real-time holding time length of the self-refresh state reaches the holding time length corresponding to the self-refresh frequency test. For example, with continued reference to fig. 10, after starting from entering the self-refresh state and waiting for the duration X corresponding to the present self-refresh frequency test to be reached in S1003, the memory under test is controlled to exit the self-refresh state in S1004.

In some embodiments, the memory under test may be controlled to exit the self-refresh state by a self-refresh exit command, and accordingly, S912 may include step C2.

And step C2, sending a self-refresh exit command to the controller to be tested so that the memory to be tested exits from the self-refresh state in response to the self-refresh exit command.

In step C2, the self-refresh rate test device of the memory may directly send a self-refresh exit command to the memory under test, or send the self-refresh exit command to the memory under test through the controller, which is not particularly limited.

The self-refresh exit command is used for indicating the memory to be tested to exit the self-refresh state. In one embodiment, with continued reference to FIG. 11, the self-refresh exit command may include a first self-refresh exit subcommand SREFXH and a second self-refresh exit subcommand SREFXL.

In one embodiment, step C2 may include steps C21 and C22 described below.

And step C21, determining a second target level state corresponding to the self-refresh exit command according to a preset standard protocol for each control signal terminal.

Illustratively, the second target level state corresponding to the self-refresh exit command may include: the level states of physical ports CA0-CA 4. For example, the level states of the physical ports CA0-CA4 corresponding to the first self-refresh exit subcommand SREFXH are low, high, low, high. The second self-refresh exit subcommand SREFXL does not require the level states of physical ports CA0-CA 4.

In another example, the second target level state corresponding to the self-refresh entry command may include: the clock enable signal CKE is set low for one period and then set high, and the chip select signal pin cs_n is set low, and the row address signal pin ras_n, the column address signal pin cas_n, the active signal pin act_n, and the write enable signal pin we_n are set high.

And step C22, setting the actual level state of each control signal end to be a second target level state corresponding to the control signal end, so that the memory to be tested can determine that the self-refresh exit command is received based on the actual level states of the control signal ends.

Through the step C21 and the step C22, the memory to be tested can be accurately controlled to exit from the self-refresh state through the control signal end, so that the test precision of the self-refresh frequency is improved.

And C2, the memory to be tested can be controlled to exit the self-refresh state through a common working command specified by a preset standard protocol, so that the self-refresh frequency can be accurately tested through the common working command, and the test cost and the test complexity are reduced.

And S913, under the condition that the duration of exiting the self-refresh state reaches the time delay duration corresponding to the self-refresh frequency test, writing the test data into the memory to be tested. For example, with continued reference to fig. 10, after waiting for the time delay period Y corresponding to the present self-refresh frequency test to be reached from the start of exiting the self-refresh state in S1005, the writing of the test data B into one or more memory arrays (arrays) of the memory under test may be controlled in S1006.

In some embodiments, S913 may include step C3.

And step C3, when the duration of the self-refresh state is up to the time delay duration corresponding to the self-refresh frequency test, sending a read-write control command to the memory to be tested, which is out of the self-refresh state, so as to control the memory to be tested to write test data through the read-write control command.

In one embodiment, the first read/write control command may be an Activate (ACT) command. For example, with continued reference to FIG. 11, the Activate (ACT) command may include a first ACT1H, a second ACT1L, a third ACT3H, and a second ACT4L.

The read-write control command may be transmitted by a control signal terminal, for example. For example, the edges of the physical ports CA0-CA5 and the differential clock signal port CK_t are used for transmitting read-write control commands.

And C3, the memory to be tested can be controlled to carry out read-write test through a common working command specified by a preset standard protocol, so that the self-refresh frequency can be accurately tested through the common working command, and the test cost and the test complexity are reduced.

For example, if the read-write control command is a valid command, the current read-write is successful, and if the read-write control command is an invalid command, the current read-write fails.

S914, data reading is carried out on the memory to be tested, in which the test data are written, so as to obtain read data. Illustratively, with continued reference to fig. 10, the readout data may be obtained through S1007.

S915, based on whether the test data and the read data are the same, generating the read-write state parameter corresponding to the self-refresh frequency test.

For example, it may be determined that the present self-refresh frequency test corresponds to a status parameter that characterizes the success of the present read-write in the case where the test data is the same as the read-out data. Accordingly, in the case where the test data is not identical to the read data, it is determined that the present self-refresh frequency test corresponds to a status parameter that characterizes the present read-write failure.

It should be noted that, the multiple self-refresh frequency test of the memory under test may be performed in other manners, which is not limited in particular.

S920, obtaining a read-write test result of the memory to be tested.

Wherein, S920 is similar to S510, and the specific content of S510 may be referred to, and will not be described herein.

S930, determining a plurality of reference holding periods based on the read-write test result.

Wherein, S930 is similar to S520, and the specific content of S520 may be referred to, and will not be described herein.

S940, according to the plurality of reference holding time periods, the self-refresh frequency of the memory to be tested is determined.

Wherein, S940 is similar to S530, and the specific content of S530 may be referred to, and will not be described herein.

And, through the embodiment of the disclosure, as shown in fig. 11, multiple self-refresh frequency tests can be sequentially implemented by controlling the retention time tSR and the time delay tXSR of the self-refresh command of each self-refresh frequency test, so that the accuracy of the test result is ensured.

In some embodiments, to ensure ordering of the tests, the plurality of self-refresh rate tests may be divided into multiple groups, each of the self-refresh rate tests in each group corresponding to the same retention period.

Accordingly, after S914, the self-refresh frequency test method of the memory may further include steps C4 to C6.

And C4, judging whether the self-refresh frequency test of the group is finished. With continued reference to fig. 10, as shown in S1008, it may be determined whether the test data is read out and then, if not, S1009 is performed and, if yes, S1010 is performed.

For example, whether the self-refresh frequency test is completed or not may be determined by determining whether the time delay period Y corresponding to the self-refresh frequency test reaches the maximum time delay period in the test. Alternatively, whether the set of self-refresh rate tests is completed may be determined based on the number of tested self-refresh rate tests, which is not particularly limited.

And step C5, under the condition that the self-refresh frequency test of the group is not completed, updating the time delay duration corresponding to the self-refresh frequency test of the time to obtain the time delay duration corresponding to the next refresh frequency test, and executing the next self-refresh frequency test based on the time delay duration corresponding to the next refresh frequency test. The update may be performed by accumulating or subtracting, for example, without any particular limitation.

Illustratively, as shown in S1009 in fig. 10, the delay period y+1 corresponding to the next self-refresh frequency test may be taken as the delay period Y corresponding to the new self-refresh frequency test, and then step S1001 is returned.

And step C6, under the condition that the self-refresh frequency test of the group is completed, updating the holding time length corresponding to the self-refresh frequency test of the group to obtain the holding time length corresponding to each self-refresh frequency test in the self-refresh frequency test of the group, and executing each self-refresh frequency test in the self-refresh frequency test of the group based on the holding time length corresponding to each self-refresh frequency test in the self-refresh frequency test of the group.

Illustratively, as shown in S1011 in fig. 10, the holding period x+1 corresponding to the next self-refresh frequency test may be taken as the holding period X corresponding to the new self-refresh frequency test, and then step S1001 may be returned. Optionally, in order to ensure the ordering of the test, as shown in S1010 of fig. 10, it may also be determined whether the self-refresh frequency test is completed, and if the determination result is completed, the self-refresh frequency test is ended; if the determination result is incomplete, S1011 is executed.

And, the retention time corresponding to the present self-refresh frequency test may be reset to an initial value when the retention time X is updated.

Through the steps C4 to C6, the self-refresh frequency test can be realized group by group in a mode of updating the holding time length and the time delay time length, the test order is improved, the subsequent generation of read-write test results such as a shmoo test chart is facilitated, and the test efficiency is improved.

In some embodiments, the self-refresh frequency test method of the memory may further include step C7 before S911.

And step C7, writing background data into the memory to be tested.

For example, to ensure accuracy of the read-write result, the background data and the write data may be different values.

For example, to improve test efficiency, background data may be written in a memory array or memory cell where test data is to be written.

Accordingly, step S911 may include step C8.

And step C8, controlling the memory to be tested, in which the background data are written, to enter a self-refresh state.

Through the steps C7 and C8, the accuracy of the self-refresh frequency test is ensured by writing background data in advance, and the test accuracy of the self-refresh frequency is further ensured.

Based on the same inventive concept, the embodiments of the present disclosure also provide a self-refresh frequency testing device for a memory, as shown in the following embodiments.

Fig. 12 is a schematic diagram of a self-refresh frequency testing device of a memory according to an embodiment of the disclosure, and as shown in fig. 12, the self-refresh frequency testing device 1200 of the memory includes a result acquisition module 1210, a duration determination module 1220, and a frequency determination module 1230.

The result obtaining module 1210 is configured to obtain a read-write test result of the memory to be tested, where the read-write test result includes multiple sets of test data, each set of test data corresponds to a retention period of a self-refresh command, each set of test data includes at least one read-write state parameter, each read-write state parameter corresponds to a delay period for exiting the self-refresh command, and each read-write state parameter is a value representing a success or failure of reading and writing of the memory to be tested under the corresponding retention period and the delay period.

The duration determining module 1220 is configured to determine a plurality of reference holding durations based on the read-write test result, where each reference holding duration is a holding duration corresponding to a set of test data having a read-write status parameter indicating a read-write failure.

The frequency determining module 1230 is configured to determine a self-refresh frequency of the memory under test according to the plurality of reference retention periods.

The self-refresh frequency testing device of the memory provided by the embodiment of the disclosure can obtain the read-write test result of the memory to be tested, wherein multiple groups of test data of the read-write test result correspond to the holding time lengths of different self-refresh commands, and each group of test data comprises at least one read-write state data corresponding to the time delay time lengths of different self-refresh commands. Since the memory will be refreshed at least once in the self-refresh mode, if the refresh is not completed when the hold time and the delay time are reached, the read-write failure will be caused. Accordingly, with the change of the holding time of the self-refresh command of the memory and the change of the time delay time of exiting the self-refresh command, the memory will have a read-write failure during each self-refresh, so that the reference holding time corresponding to the read-write status parameter indicating the read-write failure can accurately indicate the self-refresh frequency of the memory to be tested. Accordingly, the self-refresh frequency of the memory can be accurately determined through the plurality of reference holding time lengths, and the detection accuracy of the self-refresh frequency is improved.

In one embodiment, the frequency determination module 1230 is configured to:

For a plurality of reference retention periods, determining a time interval between any two adjacent reference retention periods to obtain at least one self-refresh frequency value.

In one embodiment, the memory self-refresh frequency test device 1200 further includes a test module.

The test module is used for carrying out multiple self-refresh frequency tests on the memory to be tested to obtain read-write state parameters corresponding to the multiple self-refresh frequency tests, each self-refresh frequency test corresponds to a holding time length and a delay time length, and each self-refresh frequency test is used for generating one read-write state parameter.

Wherein, test module includes:

The state entering unit is used for controlling the memory to be tested to enter a self-refresh state in each self-refresh frequency test;

The state exit unit is used for controlling the memory to be tested to exit the self-refresh state under the condition that the real-time holding time length of the self-refresh state in each self-refresh frequency test reaches the holding time length corresponding to the self-refresh frequency test;

The data writing unit is used for writing test data into the memory to be tested under the condition that the duration of exiting the self-refresh state in each self-refresh frequency test reaches the time delay duration corresponding to the self-refresh frequency test;

the data reading unit is used for reading data in the memory to be tested, which is written with the test data, in each self-refresh frequency test to obtain read data;

and the parameter generating unit is used for generating a read-write state parameter corresponding to the self-refresh frequency test based on whether the test data and the read-out data are the same or not in each self-refresh frequency test.

In one embodiment, the state entry unit is configured to:

And sending a self-refresh entry command to the memory to be tested so that the memory to be tested enters a self-refresh state in response to the self-refresh entry command.

In one embodiment, the state exit unit is configured to:

In one embodiment, the memory to be tested includes a plurality of control signal terminals, and accordingly, the state entry unit is configured to:

In one embodiment, the memory to be tested includes a plurality of control signal terminals, and accordingly, the state exiting unit is configured to:

In one embodiment, the data writing unit is configured to:

In one embodiment, the plurality of self-refresh rate tests are divided into a plurality of groups, each of the plurality of self-refresh rate tests corresponding to a same retention period.

The test module further comprises:

the judging unit is used for judging whether the self-refresh frequency test of the group is finished or not in each self-refresh frequency test;

The first updating unit is used for updating the time delay duration corresponding to the self-refresh frequency test at the present time under the condition that the self-refresh frequency test is not completed in each self-refresh frequency test, so as to obtain the time delay duration corresponding to the next refresh frequency test, and executing the next self-refresh frequency test based on the time delay duration corresponding to the next refresh frequency test;

And the second updating unit is used for updating the holding time length corresponding to the self-refresh frequency test under the condition of completing the self-refresh frequency test of the group in each self-refresh frequency test, so as to obtain the holding time length corresponding to each self-refresh frequency test in the self-refresh frequency test of the group, and executing each self-refresh frequency test in the self-refresh frequency test of the group based on the holding time length corresponding to each self-refresh frequency test in the self-refresh frequency test of the group.

In one embodiment, the test module further comprises:

The background data writing unit is used for writing background data into the memory to be tested in each self-refresh frequency test;

Accordingly, the state entry unit is configured to:

A duration determination module 1220 configured to: for each test amount, determining a plurality of reference holding periods corresponding to the test amount;

A frequency determination module 1230 configured to: and determining the self-refresh frequency of the memory to be tested under the plurality of test amounts based on the plurality of reference holding time lengths corresponding to the plurality of test amounts.

In one embodiment, the preset self-refresh frequency test factors include: the ambient temperature of the memory to be measured and/or the type of memory to be measured.

In one embodiment, the self-refresh frequency test device 1200 of the memory further includes a specification value acquisition module and a function verification module.

The standard value acquisition module is used for acquiring the self-refresh frequency standard value specified by the preset standard protocol.

And the function verification module is used for obtaining a verification result of the self-refresh function of the memory based on the determined self-refresh frequency and the self-refresh frequency standard value, and the verification result represents whether the self-refresh function of the memory is abnormal or not.

In one embodiment, the duration determination module 1220 includes a test pattern generation unit and a duration determination unit.

The test chart generating unit is used for generating a shmoo test chart based on a read-write test result, wherein the shmoo test chart comprises a plurality of image sequences, each image sequence corresponds to one group of test data in the read-write test result, each image sequence comprises at least one image unit, each image unit corresponds to one read-write state parameter, and each image unit is provided with a visual identifier which is used for identifying whether the read-write is successful or failed.

And the duration determining unit is used for determining a plurality of reference holding durations based on the shmoo test chart.

It should be noted that, the self-refresh frequency testing device 1200 of the memory shown in fig. 12 may perform the steps in the method embodiments shown in fig. 5 to 11, and implement the processes and effects in the method embodiments shown in fig. 5 to 11, which are not described herein.

Those skilled in the art will appreciate that the various aspects of the present disclosure may be implemented as a system, method, or program product. Accordingly, various aspects of the disclosure may be embodied in the following forms, namely: an entirely hardware embodiment, an entirely software embodiment (including firmware, micro-code, etc.) or an embodiment combining hardware and software aspects may be referred to herein as a "circuit," module "or" system.

An electronic device 1300 according to such an embodiment of the present disclosure is described below with reference to fig. 13. The electronic device 1300 shown in fig. 13 is merely an example and should not be construed to limit the functionality and scope of use of embodiments of the present disclosure in any way.

As shown in fig. 13, the electronic device 1300 is embodied in the form of a general purpose computing device. The components of the electronic device 1300 may include, but are not limited to: the at least one processing unit 1310, the at least one memory unit 1320, and a bus 1330 connecting the different system components (including the memory unit 1320 and the processing unit 1310).

Wherein the storage unit stores program code that is executable by the processing unit 1310 such that the processing unit 1310 performs steps according to various exemplary embodiments of the present disclosure described in the above section of the "exemplary method" of the present specification.

The storage unit 1320 may include readable media in the form of volatile storage units, such as Random Access Memory (RAM) 13201 and/or cache memory 13202, and may further include Read Only Memory (ROM) 13203.

The storage unit 1320 may also include a program/utility 13204 having a set (at least one) of program modules 13205, such program modules 13205 including, but not limited to: an operating system, one or more application programs, other program modules, and program data, each or some combination of which may include an implementation of a network environment.

Bus 1330 may be a local bus representing one or more of several types of bus structures including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or using any of a variety of bus architectures.

The electronic device 1300 may also communicate with one or more external devices 1340 (e.g., keyboard, pointing device, bluetooth device, etc.), one or more devices that enable a user to interact with the electronic device 1300, and/or any device (e.g., router, modem, etc.) that enables the electronic device 1300 to communicate with one or more other computing devices. Such communication may occur through an input/output (I/O) interface 1350.

Also, the electronic device 1300 may communicate with one or more networks such as a Local Area Network (LAN), a Wide Area Network (WAN) and/or a public network, for example, the Internet, through a network adapter 1360.

As shown in fig. 13, the network adapter 1360 communicates with other modules of the electronic device 1300 over the bus 1330.

It should be appreciated that although not shown, other hardware and/or software modules may be used in connection with electronic device 1300, including, but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, data backup storage systems, and the like.

From the above description of embodiments, those skilled in the art will readily appreciate that the example embodiments described herein may be implemented in software, or may be implemented in software in combination with the necessary hardware. Thus, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (may be a CD-ROM, a U-disk, a mobile hard disk, etc.) or on a network, including several instructions to cause a computing device (may be a personal computer, a server, a terminal device, or a network device, etc.) to perform the method according to the embodiments of the present disclosure.

In an exemplary embodiment of the present disclosure, a computer-readable storage medium, which may be a readable signal medium or a readable storage medium, is also provided. Fig. 14 illustrates a schematic diagram of a computer-readable storage medium in an embodiment of the present disclosure, as shown in fig. 14, on which a program product capable of implementing the method of the present disclosure is stored 1400.

In some possible implementations, various aspects of the disclosure may also be implemented in the form of a program product comprising program code for causing a terminal device to carry out the steps according to the various exemplary embodiments of the disclosure as described in the "exemplary methods" section of this specification, when the program product is run on the terminal device.

More specific examples of the computer readable storage medium in the present disclosure may include, but are not limited to: an electrical connection having one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

In this disclosure, a computer readable storage medium may include a data signal propagated in baseband or as part of a carrier wave, with readable program code embodied therein. Such a propagated data signal may take any of a variety of forms, including, but not limited to, electro-magnetic, optical, or any suitable combination of the foregoing.

A readable signal medium may also be any readable medium that is not a readable storage medium and that can communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device.

In some examples, program code embodied on a computer readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wireline, optical fiber cable, RF, etc., or any suitable combination of the foregoing.

In particular implementations, the program code for carrying out operations of the present disclosure may be written in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server.

In the case of remote computing devices, the remote computing device may be connected to the user computing device through any kind of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or may be connected to an external computing device (e.g., connected via the Internet using an Internet service provider).

Embodiments of the present disclosure provide a computer program product or computer program comprising computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions to cause the computer device to perform the method of self-refresh frequency testing of a memory provided in various alternatives in any of the embodiments of the disclosure.

It should be noted that although in the above detailed description several modules or units of a device for action execution are mentioned, such a division is not mandatory. Indeed, the features and functionality of two or more modules or units described above may be embodied in one module or unit in accordance with embodiments of the present disclosure. Conversely, the features and functions of one module or unit described above may be further divided into a plurality of modules or units to be embodied.

Furthermore, although the steps of the methods in the present disclosure are depicted in a particular order in the drawings, this does not require or imply that the steps must be performed in that particular order, or that all illustrated steps be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step to perform, and/or one step decomposed into multiple steps to perform, etc.

From the description of the above embodiments, those skilled in the art will readily appreciate that the example embodiments described herein may be implemented in software, or may be implemented in software in combination with the necessary hardware.

Thus, the technical solution according to the embodiments of the present disclosure may be embodied in the form of a software product, which may be stored in a non-volatile storage medium (may be a CD-ROM, a U-disk, a mobile hard disk, etc.) or on a network, including several instructions to cause a computing device (may be a personal computer, a server, a mobile terminal, or a network device, etc.) to perform the method according to the embodiments of the present disclosure.

Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein.

This disclosure is intended to cover any adaptations, uses, or adaptations of the disclosure following the general principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.

Claims

1. A method for testing a self-refresh frequency of a memory, the method comprising:

Obtaining a read-write test result of a memory to be tested, wherein the read-write test result comprises a plurality of groups of test data, each group of test data corresponds to the holding time length of a self-refresh command, each group of test data comprises at least one read-write state parameter, each read-write state parameter corresponds to the time delay time length of exiting the self-refresh command, and each read-write state parameter represents the success or failure of reading and writing of the memory to be tested under the corresponding holding time length and the time delay time length;

determining a plurality of reference holding time lengths based on the read-write test result, wherein each reference holding time length is a holding time length corresponding to a group of test data with read-write state parameters representing read-write failure;

and determining the self-refreshing frequency of the memory to be tested according to the reference holding time lengths.

2. The method of claim 1, wherein the determining the self-refresh frequency of the memory under test based on the plurality of reference retention time periods comprises:

For the multiple reference holding durations, determining a time interval between any two adjacent reference holding durations to obtain at least one self-refresh frequency value;

And determining the self-refresh frequency of the memory to be tested based on the at least one self-refresh frequency value.

3. The method of claim 1, wherein prior to obtaining the read-write test result of the memory under test, the method further comprises:

Controlling the memory to be tested to enter a self-refresh state;

writing test data into the memory to be tested under the condition that the duration of exiting the self-refresh state reaches the time delay duration corresponding to the self-refresh frequency test;

And generating a read-write state parameter corresponding to the self-refresh frequency test based on whether the test data and the read-out data are the same or not.

4. The method of claim 3, wherein the step of,

The controlling the memory to be tested to enter a self-refresh state includes:

sending a self-refresh entry command to the memory to be tested, so that the memory to be tested enters the self-refresh state in response to the self-refresh entry command;

and/or the number of the groups of groups,

The controlling the memory to be tested to exit the self-refresh state includes:

And sending a self-refresh exit command to the controller to be tested so that the memory to be tested exits the self-refresh state in response to the self-refresh exit command.

5. The method of claim 3 or 4, wherein the memory to be tested comprises a plurality of control signal terminals,

The sending the self-refresh entry command to the memory under test includes:

for each control signal terminal, determining a first target level state corresponding to the self-refresh entry command according to a preset standard protocol;

For each control signal end, setting the actual level state of the control signal end as a first target level state corresponding to the control signal end, so that the memory to be tested determines that the self-refresh entry command is received based on the actual level states of a plurality of control signal ends;

and/or the number of the groups of groups,

The sending the self-refresh exit command to the controller to be tested includes:

Determining a second target level state corresponding to the self-refresh exit command according to the preset standard protocol for each control signal end;

And setting the actual level state of each control signal end to be a second target level state corresponding to the control signal end aiming at each control signal end, so that the memory to be tested determines that the self-refresh exit command is received based on the actual level states of a plurality of control signal ends.

6. The method of claim 3, wherein the step of,

Under the condition that the duration of exiting the self-refresh state reaches the time delay duration corresponding to the self-refresh frequency test, writing test data into the memory to be tested, wherein the method comprises the following steps:

When the duration of exiting the self-refresh state reaches the time delay duration corresponding to the self-refresh frequency test, a read-write control command is sent to the memory to be tested, which exits the self-refresh state, so as to control the memory to be tested to write the test data through the read-write control command.

7. The method of claim 3, wherein the plurality of self-refresh rate tests are divided into a plurality of groups, each self-refresh rate test in each group corresponding to a same retention period;

After the data reading is performed on the memory to be tested, in which the test data are written, and the read data are obtained, the method further comprises:

8. The method of claim 3, wherein the step of,

Before the controlling the memory to be tested to enter the self-refresh state, the method further comprises:

Writing background data into the memory to be tested;

wherein, the controlling the memory to be tested to enter the self-refresh state includes:

and controlling the memory to be tested, in which the background data are written, to enter the self-refresh state.

9. The method of claim 1, wherein the read-write test result comprises: read-write test results corresponding to a plurality of test amounts under the test factors of the preset self-refresh frequency respectively;

the determining a plurality of reference holding durations based on the read-write test result includes:

The determining the self-refresh frequency of the memory to be tested according to the reference holding time periods comprises:

And determining self-refreshing frequency of the memory to be tested under the plurality of test quantities based on a plurality of reference holding time lengths corresponding to the plurality of test quantities.

10. The method of claim 9, wherein the predetermined self-refresh frequency test factor comprises:

The ambient temperature of the memory under test and/or the type of the memory under test.

11. The method of claim 1, wherein after determining the self-refresh frequency of the memory under test based on the plurality of reference retention time periods, the method further comprises:

And based on the determined self-refresh frequency and the self-refresh frequency specification value, obtaining a verification result of the self-refresh function of the memory, wherein the verification result represents whether the self-refresh function of the memory is abnormal or not.

12. The method according to any one of claims 1 to 11, wherein,

Generating a shmoo test chart based on the read-write test result, wherein the shmoo test chart comprises a plurality of image sequences, each image sequence corresponds to a group of test data in the read-write test result, each image sequence comprises at least one image unit, each image unit corresponds to a read-write state parameter, each image unit is provided with a visual identifier, and the visual identifier is used for identifying whether the read-write is successful or failed;

And determining the reference holding time periods based on the shmoo plot.

13. A self-refresh frequency test device for a memory, comprising:

The device comprises a result acquisition module, a data processing module and a data processing module, wherein the result acquisition module is used for acquiring a read-write test result of a memory to be tested, the read-write test result comprises a plurality of groups of test data, each group of test data corresponds to the holding time length of a self-refresh command, each group of test data comprises at least one read-write state parameter, each read-write state parameter corresponds to the time delay time length of a self-refresh command, and each read-write state parameter represents the success or failure of reading and writing of the memory to be tested under the corresponding holding time length and the time delay time length;

And the frequency determining module is used for determining the self-refreshing frequency of the memory to be tested according to the reference holding time lengths.

14. An electronic device, comprising:

A processor; and

A memory for storing executable instructions of the processor;

wherein the processor is configured to perform the method of self-refresh frequency testing of the memory of any one of claims 1-12 via execution of the executable instructions.

15. A computer readable storage medium having stored thereon a computer program, wherein the computer program when executed by a processor implements the method of self-refresh frequency testing of a memory as claimed in any of claims 1-12.