CN117912410A - Pixel driving circuit, control method thereof, display panel and display device - Google Patents

Abstract

The disclosure provides a pixel driving circuit, a control method thereof, a display panel and a display device, and relates to the technical field of display. The pixel driving circuit includes a driving sub-circuit, a second light emission control sub-circuit, and a first reset sub-circuit, the driving sub-circuit configured to: under the control of the signal of the first node, the second node and the third node are conducted; the second light-emitting control sub-circuit is electrically connected with the third node, the fourth node and the second light-emitting control end respectively, the fourth node is electrically connected with the anode of the light-emitting device, and the second light-emitting control sub-circuit is configured to: under the control of the signal of the second light-emitting control end, the third node and the fourth node are conducted; the first reset sub-circuit is electrically connected with the third node, the first control end and the first signal end respectively, and is configured to: and writing the signal of the first signal end into the third node under the control of the signal of the first control end so as to reset the third node.

Description

Pixel driving circuit, control method thereof, display panel and display device

Technical Field

The disclosure relates to the technical field of display, and in particular relates to a pixel driving circuit, a control method thereof, a display panel and a display device.

Background

An Organic Light-Emitting Diode (OLED) display panel has many outstanding advantages of bright color, fast response speed, high contrast ratio, low power consumption, and the like, and thus has been widely used. In particular, in medium and small-sized display devices, an OLED display panel gradually replaces a Liquid CRYSTAL DISPLAY (LCD) display panel.

Disclosure of Invention

Embodiments of the present disclosure provide a pixel driving circuit, a control method thereof, a display panel, and a display device, which improve a first frame luminance ratio.

In order to achieve the above object, the embodiments of the present disclosure adopt the following technical solutions:

In one aspect, a pixel driving circuit is provided that includes a driving sub-circuit, a second light emission control sub-circuit, and a first reset sub-circuit,

The drive sub-circuit is electrically connected to the first node, the second node, and the third node, respectively, the drive sub-circuit configured to: conducting between the second node and the third node under the control of the signal of the first node;

the second light-emitting control sub-circuit is electrically connected with the third node, the fourth node and the second light-emitting control end respectively, the fourth node is electrically connected with the anode of the light-emitting device, and the second light-emitting control sub-circuit is configured to: under the control of the signal of the second light-emitting control end, the third node and the fourth node are conducted;

The first reset sub-circuit is electrically connected with the third node, the first control terminal and the first signal terminal respectively, and is configured to: and writing the signal of the first signal end into the third node under the control of the signal of the first control end so as to reset the third node.

In some embodiments, the first reset sub-circuit and the second light emission control sub-circuit are further configured to: and under the control of the signals of the first control end and the second light-emitting control end, writing the signal of the first signal end into the anode of the light-emitting device so as to reset the anode of the light-emitting device.

In some embodiments, the pixel driving circuit further includes a compensation sub-circuit electrically connected to the third node, the first node, and the second control terminal, respectively,

The compensation subcircuit and the first reset subcircuit are further configured to: and writing the signal of the first signal end into the first node under the control of the signals of the first control end and the second control end so as to reset the first node.

In some embodiments, the pixel driving circuit further includes a third reset sub-circuit electrically connected to the first node, the fourth control terminal, and a third signal terminal, respectively, the third reset sub-circuit configured to: and writing the signal of the third signal end into the first node under the control of the signal of the fourth control end so as to reset the first node.

In some embodiments, the pixel driving circuit further includes a fourth reset sub-circuit electrically connected to the anode, the fifth control terminal, and the fourth signal terminal of the light emitting device, respectively, the fourth reset sub-circuit configured to: and writing the signal of the fourth signal end into the anode of the light emitting device under the control of the signal of the fifth control end so as to reset the anode of the light emitting device.

In some embodiments, the pixel driving circuit further includes a second reset sub-circuit electrically connected to the second node, the third control terminal, and the second signal terminal, respectively, the second reset sub-circuit configured to: and writing the signal of the second signal end into the second node under the control of the signal of the third control end so as to reset the second node.

In some embodiments, the pixel driving circuit further comprises a first light emitting control sub-circuit, a data writing sub-circuit, a storage sub-circuit,

The first light emitting control sub-circuit is electrically connected to a first voltage terminal, the second node, and a first light emitting control terminal, respectively, and is configured to: under the control of the signal of the first light emitting control end, the first voltage end and the second node are conducted;

The data writing sub-circuit is electrically connected with the second node, the data signal terminal and the sixth control terminal respectively, and is configured to: writing the signal of the data signal end into the second node under the control of the signal of the sixth control end;

The storage sub-circuit is electrically connected with the first voltage end and the first node respectively, and is configured to store signals of the first node.

In some embodiments, the first reset sub-circuit includes a first transistor having a first pole electrically connected to the first signal terminal, a second pole electrically connected to the third node, and a control pole electrically connected to the first control terminal.

In another aspect, there is provided a control method of a pixel driving circuit for controlling the pixel driving circuit, a drain reset phase being included in one light emitting period of a light emitting device, the control method comprising:

and in the drain electrode resetting stage, controlling the first resetting subcircuit to enable the signal of the first signal end to be written into the third node so as to reset the third node.

In some embodiments, the pixel driving circuit further includes a compensation sub-circuit electrically connected to the third node, the first node, and the second control terminal, respectively, and the one light emitting period of the light emitting device further includes a gate reset phase, and the control method further includes:

and in the grid resetting stage, controlling the first resetting subcircuit and the compensating subcircuit to enable the signal of the first signal end to be written into the first node so as to reset the first node.

In some embodiments, one light emitting period of the light emitting device further includes an anode reset phase, and the control method further includes:

And in the anode resetting stage, controlling a second light-emitting control sub-circuit and the first resetting circuit to enable signals of the first signal end to be written into the anode of the light-emitting device so as to reset the anode of the light-emitting device.

In yet another aspect, a display panel is provided that includes the pixel driving circuit.

In yet another aspect, a display device is provided, including the display panel.

According to the pixel driving circuit, the control method thereof, the display panel and the display device, the display panel comprises the plurality of conductive film layers which are stacked, parasitic capacitance is easy to form between the conductive film layers in the overlapping area, and the parasitic capacitance can influence the performance of the pixel driving circuit. Wherein, parasitic capacitance formed between the third node and other conductive film layers affects the first frame luminance ratio (FFR). Specifically, when a parasitic capacitance is formed between the third node and the other film layer, the parasitic capacitance is charged when the driving current flows through the third node, thereby affecting the light emitting time of the light emitting device. The pixel driving circuit provided by the embodiment of the disclosure is provided with the first reset sub-circuit, and the third node can be reset in advance (namely, parasitic capacitance formed at the third node is charged in advance) through the first reset sub-circuit, so that the charging time of driving current to the parasitic capacitance can be reduced or eliminated, and FFR is improved.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.

Fig. 1 is a schematic diagram of a display device according to an embodiment of the disclosure;

Fig. 2 is a schematic diagram of a display panel according to an embodiment of the present disclosure;

Fig. 3 is a block diagram of a pixel driving circuit according to an embodiment of the present disclosure;

FIG. 4 is a block diagram of another pixel driving circuit according to an embodiment of the present disclosure;

FIG. 5 is a block diagram of another pixel driving circuit according to an embodiment of the present disclosure;

FIG. 6 is a block diagram of another pixel driving circuit according to an embodiment of the present disclosure;

FIG. 7 is a block diagram of another pixel driving circuit according to an embodiment of the present disclosure;

FIG. 8 is a block diagram of another pixel driving circuit according to an embodiment of the present disclosure;

fig. 9 is a block diagram of another pixel driving circuit according to an embodiment of the present disclosure;

fig. 10 is a schematic circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure;

FIG. 11 is a schematic circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure;

Fig. 12 is a signal timing diagram of a portion of transistors in the pixel driving circuit shown in fig. 10.

Detailed Description

The following description of the technical solutions in the embodiments of the present disclosure will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person of ordinary skill in the art would obtain without making any inventive effort are within the scope of protection of this disclosure.

In the embodiments of the present disclosure, the words "first," "second," "third," "fourth," etc. are used to distinguish between the same item or similar items that have substantially the same function and function, but merely for clarity of description of the technical solutions of the embodiments of the present disclosure, and are not to be construed as indicating or implying a relative importance or implying an indication of the number of technical features indicated.

In the embodiments of the present disclosure, the meaning of "a plurality" means two or more, and the meaning of "at least one" means one or more, unless specifically defined otherwise.

In the embodiments of the present disclosure, the azimuth or positional relationship indicated by the terms "upper", "lower", etc., are based on the azimuth or positional relationship shown in the drawings, and are merely for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present disclosure.

Fig. 1 is a schematic diagram of a display device according to an embodiment of the disclosure. As shown in fig. 1, some embodiments of the present disclosure provide a display device 100, and the display device 100 may display an image. The displayed image may be a moving image (e.g., video), a still image (e.g., picture, slide show, etc.), or text. For example, the display device 100 may be a mobile phone, a Personal Data Assistant (PDA), a handheld or portable computer, a GPS receiver/navigator, a camera, an MP4 video player, a video camera, a game console, a watch, a clock, a calculator, a television monitor, a flat panel display, a computer monitor, an automotive display (e.g., odometer display, etc.), a navigator, a cockpit controls and/or display, a display of a camera view (e.g., a display of a rear view camera in a vehicle), an electronic photograph, an electronic billboard or sign, a projector, architectural structures, packaging, and aesthetic structures (e.g., a display of images for a piece of jewelry), and the like. In fig. 1, a display device 100 is illustrated as a mobile phone.

The display device 100 includes a display panel 110. The display panel 110 may be a Liquid crystal display panel (LCD), an electroluminescent display panel, or a photoluminescent display panel. In the case where the display panel 110 is an electroluminescent display panel, the electroluminescent display panel may be an Organic Light-Emitting Diode (OLED) display panel or a Quantum Dot LIGHT EMITTING Diode (QLED) display panel. In the case where the display panel 110 is a photoluminescent display panel, the photoluminescent display panel may be a quantum dot photoluminescent display panel.

Some embodiments of the present disclosure are illustrated with the display panel 110 being an Organic Light-Emitting Diode (OLED) display panel.

Fig. 2 is a schematic diagram of a display panel according to an embodiment of the present disclosure. As shown in fig. 2, the display panel 110 may have a display area AA and a non-display area NA connected to the display area AA. The non-display area NA may be located at one side, two sides, or three sides of the display area AA, or the non-display area NA may be disposed around the display area AA.

The display area AA is provided with a plurality of sub-pixels P, a plurality of gate lines GL and a plurality of data lines DL.

Illustratively, a plurality of subpixels P are arranged in an array. For example, a plurality of sub-pixels P are arranged in an array to form a plurality of sub-pixel rows and a plurality of sub-pixel columns, and the plurality of sub-pixels P in one sub-pixel row are arranged along the first direction X, and the plurality of sub-pixels P in one sub-pixel column are arranged along the second direction Y.

Wherein the first direction X and the second direction Y cross each other. The included angle between the first direction X and the second direction Y can be selected and set according to actual needs. Illustratively, the angle between the first direction X and the second direction Y may be 85 °, 88 °, 90 °, 92 °, 95 °, or the like.

The sub-pixel P may include a pixel driving circuit and a light emitting device electrically connected to the pixel driving circuit. When the display panel 110 is operated, the light emitting device may emit light under the driving of the pixel driving circuit.

Illustratively, a plurality of pixel driving circuits in the same sub-pixel column are electrically connected to the same data line DL, and a plurality of pixel driving circuits in the same sub-pixel row are electrically connected to the same gate line GL.

The display panel 110 is further provided with a scan driving circuit, which may be disposed in the non-display area NA. Of course, in the practical application process, in order to reduce the frame size of the display panel 110, at least part of the structure of the scan driving circuit may be disposed in the display area AA.

The scan driving circuit includes a plurality of cascaded shift registers GOA, the shift registers GOA include output terminals, and the output terminals of the shift registers GOA may be electrically connected to the gate lines GL. When the scan driving circuit works, the plurality of cascaded shift registers GOA output control signals step by step through the output end, so that a plurality of sub-pixels P of the display panel 110 are lighted up row by row.

Fig. 3 is a block diagram of a pixel driving circuit according to an embodiment of the present disclosure. As shown in fig. 3, the pixel driving circuit includes a driving sub-circuit, a second light emission control sub-circuit, and a first reset sub-circuit.

The driving sub-circuit is electrically connected to the first node N1, the second node N2, and the third node N3, respectively. The drive subcircuit is configured to: the second node N2 and the third node N3 are turned on under the control of the signal of the first node N1. For example, when the signal of the first node N1 is a low level signal, the second node N2 and the third power saving are turned on by the driving sub-circuit.

The light emitting period of the light emitting device OLED includes a light emitting period. In the light emitting stage, the second node N2 and the third node N3 are turned on by the driving sub-circuit and form a driving current corresponding to the signal of the first node N1.

The second light emission control sub-circuit is electrically connected to the third node N3, the fourth node and the second light emission control terminal EM2, respectively, and the fourth node is electrically connected to the anode of the light emitting device OLED. The second light emission control sub-circuit is configured to: the third node N3 and the fourth node are turned on under the control of the signal of the second emission control terminal EM 2. For example, when the signal of the second light emission control terminal EM2 is a low level signal, the third node N3 and the fourth node are turned on by the second light emission control sub-circuit.

In the light emitting stage, the third node N3 is turned on by the second light emitting control sub-circuit, and the driving current flows into the light emitting device OLED through the driving sub-circuit and the second light emitting control sub-circuit in sequence, so that the light emitting device OLED is driven to emit light.

The first reset sub-circuit is electrically connected to the third node N3, the first control terminal S1, and the first signal terminal V1, respectively. The first reset subcircuit is configured to: under the control of the signal of the first control terminal S1, the signal of the first signal terminal V1 is written into the third node N3 to reset the third node N3. For example, when the signal of the first control terminal S1 is a low level signal, the first signal terminal V1 and the third node N3 are turned on by the first reset sub-circuit, so that the signal of the first signal terminal V1 is written into the third node N3, and the third node N3 is reset.

The light emitting device OLED includes a drain reset phase in one light emitting period. In the drain reset stage, the first signal terminal V1 and the third node N3 are turned on by the first reset sub-circuit, so that the signal of the first signal terminal V1 is written into the third node N3, thereby resetting the third node N3.

The display panel 110 includes a plurality of conductive film layers stacked, and parasitic capacitance is easily formed between the conductive film layers having an overlapping region, and affects the performance of the pixel driving circuit. The parasitic capacitance formed between the third node N3 and other conductive film layers affects the first frame luminance ratio (FFR). Specifically, when a parasitic capacitance is formed between the third node N3 and other film layers, the parasitic capacitance is charged when the driving current flows through the third node N3, thereby affecting the light emitting time of the light emitting device OLED. The pixel driving circuit provided by the embodiment of the disclosure is provided with the first reset sub-circuit, and the third node N3 can be reset in advance (that is, parasitic capacitance formed at the third node N3 is charged in advance) through the first reset sub-circuit, so that the charging time of driving current to the parasitic capacitance can be reduced or eliminated, and FFR is improved.

In some implementations, the first reset sub-circuit and the second light emission control sub-circuit may be further configured to: under the control of the signals of the first control terminal S1 and the second light emission control terminal EM2, the signal of the first signal terminal V1 is written to the anode of the light emitting device OLED to reset the anode of the light emitting device OLED. For example, when the signals of the first control terminal S1 and the second light emitting control terminal EM2 are low level signals, the first reset sub-circuit and the second light emitting control sub-circuit are turned on, and the signal of the first signal terminal V1 is written into the anode of the light emitting device OLED, thereby resetting the anode of the light emitting device OLED.

The light emitting device OLED may further include an anode reset phase within one light emitting period. In the anode reset stage, the first signal terminal V1 is turned on with the anode of the light emitting device OLED through the first reset sub-circuit and the second light emission control sub-circuit, and the signal of the first signal terminal V1 is written into the anode of the light emitting device OLED, so that the anode of the light emitting device OLED is reset.

Note that the signal for resetting the anode of the light emitting device OLED may be different from the signal for resetting the third node N3. At this time, the first signal terminal V1 may have different signals at different stages. For example, in the drain reset phase, the signal of the first signal terminal V1 is a signal for resetting the third node N3; in the anode reset phase, the signal of the first signal terminal V1 is a signal for resetting the anode of the light emitting device OLED.

The first reset sub-circuit can be used for resetting the third node N3 and resetting the anode of the light emitting device OLED, so that the number of sub-circuits in the pixel driving circuit is reduced, and the process complexity of the display panel is reduced. In addition, after the number of the sub-circuits is reduced, the leakage path of the pixel driving circuit is reduced, and the display effect at low frequency is improved.

Fig. 4 is a block diagram of another pixel driving circuit according to an embodiment of the present disclosure. As shown in fig. 4, in some embodiments, the pixel driving circuit further includes a compensation sub-circuit electrically connected to the third node N3, the first node N1, and the second control terminal S2, respectively. The compensation subcircuit is configured to: the third node N3 is turned on with the first node N1 under the control of the signal of the second control terminal S2. For example, when the signal of the second control terminal S2 is a low level signal, the third node N3 and the first node N1 are turned on.

The light emitting device OLED may further include a gate reset period within one light emitting period. In the gate reset stage, the first signal terminal V1 and the third node N3 are turned on by the first reset sub-circuit, and the third node N3 and the first node N1 are turned on by the compensation sub-circuit, that is, the first signal terminal V1 and the first node N1 are turned on, so that the signal of the first signal terminal V1 is written into the first node N1 to reset the first node N1.

Note that the signal for resetting the first node N1 may be different from the signal for resetting the anode of the light emitting device OLED and the signal for resetting the third node N3. At this time, the first signal terminal V1 may have different signals at different stages. For example, in the drain reset phase, the signal of the first signal terminal V1 is a signal for resetting the third node N3; in the anode resetting stage, the signal of the first signal end V1 is a signal for resetting the anode of the light-emitting device OLED; in the gate reset phase, the signal of the first signal terminal V1 is a signal for resetting the first node N1.

The first reset sub-circuit can be used for resetting the third node N3 and also can be used for the first node N1, so that the number of sub-circuits in the pixel driving circuit is reduced, and the process complexity of the display panel is reduced. In addition, after the number of the sub-circuits is reduced, the leakage path of the pixel driving circuit is reduced, and the display effect at low frequency is improved.

Fig. 5 is a block diagram of another pixel driving circuit according to an embodiment of the present disclosure. As shown in fig. 5, the pixel driving circuit may further include a data writing sub-circuit. The data writing sub-circuit is electrically connected to the second node N2, the data signal terminal, and the sixth control terminal S6, respectively. The data write sub-circuit is configured to: the signal of the data signal terminal is written into the second node N2 under the control of the signal of the sixth control terminal S6. For example, when the signal of the sixth control terminal S6 is a low level signal, the data signal terminal is turned on with the second node N2.

The light emitting device OLED may further include a data writing period within one light emitting period. In the data writing stage, the data signal end is conducted with the second node N2 through a data writing sub-circuit, the second node N2 is conducted with the third node N3 through a driving sub-circuit, and the third node N3 is conducted with the first node N1 through a compensation sub-circuit, so that the data signal of the data signal end and compensation data are written into the first node N1.

Fig. 6 is a block diagram of another pixel driving circuit according to an embodiment of the present disclosure. As shown in fig. 6, in some embodiments, the pixel drive circuit further includes a third reset sub-circuit. The third reset sub-circuit is electrically connected to the first node N1, the fourth control terminal S4, and the third signal terminal V3, respectively. The third reset sub-circuit is configured to: under the control of the signal of the fourth control terminal S4, the signal of the third signal terminal V3 is written into the first node N1 to reset the first node N1. For example, when the signal of the fourth control terminal S4 is a low level signal, the third signal terminal V3 and the first node N1 are turned on through the third reset sub-circuit.

The third reset sub-circuit is used for resetting the first node N1, and the first reset sub-circuit is not needed to reset the first node N1, so that the control complexity of the pixel driving circuit is reduced.

Fig. 7 is a block diagram of another pixel driving circuit according to an embodiment of the present disclosure. As shown in fig. 7, in some embodiments, the pixel drive circuit further includes a fourth reset sub-circuit. The fourth reset sub-circuit is electrically connected to the anode of the light emitting device OLED, the fifth control terminal S5, and the fourth signal terminal V4, respectively. The fourth reset sub-circuit is configured to: under the control of the signal of the fifth control terminal S5, the signal of the fourth signal terminal V4 is written to the anode of the light emitting device OLED to reset the anode of the light emitting device OLED. For example, when the signal of the fifth control terminal S5 is a low level signal, the fourth signal terminal V4 is turned on with the anode of the light emitting device OLED through the fourth reset sub-circuit.

The fourth reset sub-circuit is used to reset the anode of the light emitting device OLED without resetting the first node N1 by the first reset sub-circuit, reducing the control complexity of the pixel driving circuit.

In practical application, the fourth reset sub-circuit and the third reset sub-circuit may be set at the same time, or only one of them may be set.

Fig. 8 is a block diagram of another pixel driving circuit according to an embodiment of the present disclosure. As shown in fig. 8, in some embodiments, the pixel drive circuit further includes a second reset sub-circuit. The second reset sub-circuit is electrically connected to the second node N2, the third control terminal S3, and the second signal terminal V2, respectively. The second reset sub-circuit is configured to: under the control of the signal of the third control terminal S3, the signal of the second signal terminal V2 is written into the second node N2 to reset the second node N2. For example, when the signal of the third control terminal S3 is a low level signal, the second signal terminal V2 and the second node N2 are turned on through the second reset sub-circuit.

The light emitting device OLED may further include a source reset period within one light emitting period. In the source reset stage, the second signal terminal V2 and the second node N2 are turned on by the second reset sub-circuit, so that the signal of the second signal terminal V2 is written into the second node N2 to reset the second node N2.

The display panel 110 includes a plurality of conductive film layers stacked, and parasitic capacitance is easily formed between the conductive film layers having an overlapping region, and affects the performance of the pixel driving circuit. The parasitic capacitance formed between the second node N2 and other conductive film layers affects the first frame luminance ratio (FFR). Specifically, when a parasitic capacitance is formed between the second node N2 and other film layers, the parasitic capacitance is charged when the driving current flows through the second node N2, thereby affecting the light emitting time of the light emitting device OLED. The pixel driving circuit provided by the embodiment of the disclosure is provided with the second reset sub-circuit, and the second node N2 can be reset in advance (that is, parasitic capacitance formed at the second node N2 is charged in advance) through the second reset sub-circuit, so that the charging time of driving current to the parasitic capacitance can be reduced or eliminated, and FFR is improved.

Fig. 9 is a block diagram of another pixel driving circuit according to an embodiment of the present disclosure. As shown in fig. 9, in some embodiments, the pixel driving circuit further includes a first light emitting control sub-circuit and a storage sub-circuit.

The first light emitting control sub-circuit is electrically connected to the first voltage terminal ELVDD, the second node N2, and the first light emitting control terminal EM1, respectively. The first light emitting control sub-circuit is configured to: the first voltage terminal ELVDD and the second node N2 are turned on under the control of the signal of the first light emitting control terminal EM 1. For example, when the signal of the first light emitting control terminal EM1 is a low level signal, the first voltage terminal ELVDD and the second node N2 are turned on through the first light emitting control terminal EM 1.

In the light emitting stage, the first voltage terminal ELVDD and the second node N2 are turned on through the first light emitting control sub-circuit.

The memory sub-circuit is electrically connected to the first voltage terminal ELVDD and the first node N1, respectively. The storage subcircuit is configured to store the signal of the first node N1.

During a data writing phase, the data signal and the compensation signal are stored in the memory sub-circuit.

Fig. 10 is a schematic circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure. As shown in fig. 10, the first light emitting control sub-circuit may include a fifth transistor M5, a first pole of the fifth transistor M5 is electrically connected to the first voltage terminal ELVDD, a second pole of the fifth transistor M5 is electrically connected to the second node N2, and a gate of the fifth transistor M5 is electrically connected to the first light emitting control terminal EM 1. The driving sub-circuit may include a driving transistor M3, a first pole of the driving transistor M3 is electrically connected to the second node N2, a second pole of the driving transistor M3 is electrically connected to the third node N3, and a gate of the driving transistor M3 is electrically connected to the first node N1. The second light emission control sub-circuit may include a sixth transistor M6, a first electrode of the sixth transistor M6 being electrically connected to the third node N3, a second electrode of the sixth transistor M6 being electrically connected to an anode of the light emitting device OLED, and a gate electrode of the sixth transistor M6 being electrically connected to the second light emission control terminal EM 2. The data writing sub-circuit may include a fourth transistor M4, a first pole of the fourth transistor M4 is electrically connected to the data signal terminal, a second pole of the fourth transistor M4 is electrically connected to the second node N2, and a gate of the fourth transistor M4 is electrically connected to the sixth control terminal S6. The second reset sub-circuit may include a seventh transistor M7, a first pole of the seventh transistor M7 is electrically connected to the second signal terminal V2, a second pole of the seventh transistor M7 is electrically connected to the second node N2, and a gate of the seventh transistor M7 is electrically connected to the third control terminal S3. The first reset sub-circuit may include a first transistor M1, a first pole of the first transistor M1 is electrically connected to the first signal terminal V1, a second pole of the first transistor M1 is electrically connected to the third node N3, and a control pole of the first transistor M1 is electrically connected to the first control terminal S1. The compensation sub-circuit may include a second transistor M2, a first pole of the second transistor M2 is electrically connected to the third node N3, a second pole of the second transistor M2 is electrically connected to the first node N1, and a gate of the second transistor M2 is electrically connected to the second control terminal S2. The storage sub-circuit may include a storage capacitor C having one plate electrically connected to the first node N1 and the other plate electrically connected to the first voltage terminal ELVDD.

Fig. 11 is a schematic circuit diagram of a pixel driving circuit according to an embodiment of the present disclosure. As shown in fig. 11, the third reset sub-circuit may include an eighth transistor M8, a first pole of the eighth transistor M8 is electrically connected to the third signal terminal V3, a second pole of the eighth transistor M8 is electrically connected to the first node N1, and a gate of the eighth transistor M8 is electrically connected to the fourth control terminal S4. The fourth reset sub-circuit may include a ninth transistor M9, a first pole of the ninth transistor M9 being electrically connected to the fourth signal terminal V4, a second pole of the ninth transistor M9 being electrically connected to the anode of the light emitting device OLED, and a gate of the ninth transistor M9 being electrically connected to the fifth control terminal S5.

The transistors shown in fig. 10 and 11 are P-type transistors, and may be N-type transistors or P-type transistors in practical application, and N-type transistors in some applications.

The embodiment of the disclosure also provides a control method of the pixel driving circuit, which is used for controlling the pixel driving circuit. Fig. 12 is a signal timing diagram of a portion of transistors in the pixel driving circuit shown in fig. 10, and a control method of the pixel driving circuit according to an embodiment of the disclosure is described below with reference to fig. 10 and 12.

As shown in fig. 12, the light emitting device OLED may include an anode reset period t1, a gate reset period t2, a data writing period t3, a source reset period t4, an anode reset period t5, a drain reset period t6, and a light emitting period t7 within one light emitting period.

The control method of the pixel driving circuit comprises the following steps:

in the drain reset stage t6, the first reset sub-circuit is controlled to write the signal of the first signal terminal V1 into the third node N3 to reset the third node N3.

Illustratively, in the drain reset phase t6, a low level signal is sent to the first control terminal S1 to turn on the first transistor M1, and the first signal terminal V1 is turned on with the third node N3 through the first transistor M1. The signal of the first signal terminal V1 is written into the third node N3, so that the third node N3 is reset.

The display panel comprises a plurality of conductive film layers which are stacked, and parasitic capacitance is easy to form between the conductive film layers with overlapped areas, and the parasitic capacitance can influence the performance of the pixel driving circuit. The parasitic capacitance formed between the third node N3 and other conductive film layers affects the first frame luminance ratio (FFR). Specifically, when a parasitic capacitance is formed between the third node N3 and other film layers, the parasitic capacitance is charged when the driving current flows through the third node N3, thereby affecting the light emitting time of the light emitting device OLED. The pixel driving circuit provided by the embodiment of the disclosure is provided with the first reset sub-circuit, and the third node N3 can be reset in advance (that is, parasitic capacitance formed at the third node N3 is charged in advance) through the first reset sub-circuit, so that the charging time of driving current to the parasitic capacitance can be reduced or eliminated, and FFR is improved.

In some embodiments, the control method of the pixel driving circuit further includes the steps of:

in the gate reset phase t2, the first reset sub-circuit and the compensation sub-circuit are controlled to write the signal of the first signal terminal V1 into the first node N1 to reset the first node N1.

Illustratively, in the gate reset phase t2, a low level signal is sent to the first control terminal S1 and the second control terminal S2, so that the first transistor M1 and the second transistor M2 are turned on, and the first node N1 is turned on by the first transistor M1 and the second transistor M2 between the first node N1 and the first signal terminal V1, and the signal of the first signal terminal V1 is written into the first node N1, so that the first node N1 is reset.

The first reset sub-circuit can be used for resetting the third node N3 and also can be used for the first node N1, so that the number of sub-circuits in the pixel driving circuit is reduced, and the process complexity of the display panel is reduced. In addition, after the number of the sub-circuits is reduced, the leakage path of the pixel driving circuit is reduced, and the display effect at low frequency is improved.

In some embodiments, the control method of the pixel driving circuit further includes the steps of:

in the anode reset stage, the second light emission control sub-circuit and the first reset circuit are controlled to write the signal of the first signal terminal V1 into the anode of the light emitting device OLED to reset the anode of the light emitting device OLED.

The anode reset phase may be a t2 phase or a t5 phase.

Illustratively, in the anode reset phase, a low level signal is sent to the first control terminal S1 and the second emission control terminal EM2, so that the first transistor M1 and the sixth transistor M6 are turned on, and the first signal terminal V1 is turned on with the anode of the light emitting device OLED through the first transistor M1 and the sixth transistor M6, and the signal of the first signal terminal V1 is written into the anode of the light emitting device OLED, so that the anode of the light emitting device OLED is reset.

The first reset sub-circuit can be used for resetting the third node N3 and resetting the anode of the light emitting device OLED, so that the number of sub-circuits in the pixel driving circuit is reduced, and the process complexity of the display panel is reduced. In addition, after the number of the sub-circuits is reduced, the leakage path of the pixel driving circuit is reduced, and the display effect at low frequency is improved.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (13)

1. A pixel driving circuit is characterized by comprising a driving sub-circuit, a second light-emitting control sub-circuit and a first reset sub-circuit,

The drive sub-circuit is electrically connected to the first node, the second node, and the third node, respectively, the drive sub-circuit configured to: conducting between the second node and the third node under the control of the signal of the first node;

the second light-emitting control sub-circuit is electrically connected with the third node, the fourth node and the second light-emitting control end respectively, the fourth node is electrically connected with the anode of the light-emitting device, and the second light-emitting control sub-circuit is configured to: under the control of the signal of the second light-emitting control end, the third node and the fourth node are conducted;

The first reset sub-circuit is electrically connected with the third node, the first control terminal and the first signal terminal respectively, and is configured to: and writing the signal of the first signal end into the third node under the control of the signal of the first control end so as to reset the third node.

2. The pixel drive circuit of claim 1, wherein the first reset sub-circuit and the second light emission control sub-circuit are further configured to: and under the control of the signals of the first control end and the second light-emitting control end, writing the signal of the first signal end into the anode of the light-emitting device so as to reset the anode of the light-emitting device.

3. The pixel driving circuit according to claim 1, further comprising a compensation sub-circuit electrically connected to the third node, the first node and the second control terminal, respectively,

The compensation subcircuit and the first reset subcircuit are further configured to: and writing the signal of the first signal end into the first node under the control of the signals of the first control end and the second control end so as to reset the first node.

4. The pixel drive circuit of claim 1, further comprising a third reset sub-circuit electrically connected to the first node, the fourth control terminal, and a third signal terminal, respectively, the third reset sub-circuit configured to: and writing the signal of the third signal end into the first node under the control of the signal of the fourth control end so as to reset the first node.

5. A pixel driving circuit according to claim 1 or 4, further comprising a fourth reset sub-circuit electrically connected to the anode of the light emitting device, the fifth control terminal and the fourth signal terminal, respectively, the fourth reset sub-circuit being configured to: and writing the signal of the fourth signal end into the anode of the light emitting device under the control of the signal of the fifth control end so as to reset the anode of the light emitting device.

6. The pixel drive circuit of claim 1, further comprising a second reset sub-circuit electrically connected to the second node, the third control terminal, and the second signal terminal, respectively, the second reset sub-circuit configured to: and writing the signal of the second signal end into the second node under the control of the signal of the third control end so as to reset the second node.

7. The pixel driving circuit according to claim 1, further comprising a first light emitting control sub-circuit, a data writing sub-circuit, a storage sub-circuit,

The first light emitting control sub-circuit is electrically connected to a first voltage terminal, the second node, and a first light emitting control terminal, respectively, and is configured to: under the control of the signal of the first light emitting control end, the first voltage end and the second node are conducted;

The data writing sub-circuit is electrically connected with the second node, the data signal terminal and the sixth control terminal respectively, and is configured to: writing the signal of the data signal end into the second node under the control of the signal of the sixth control end;

The storage sub-circuit is electrically connected with the first voltage end and the first node respectively, and is configured to store signals of the first node.

8. A pixel driving circuit according to any one of claims 1 to 7, wherein the first reset sub-circuit comprises a first transistor, a first pole of the first transistor being electrically connected to the first signal terminal, a second pole of the first transistor being electrically connected to the third node, a control pole of the first transistor being electrically connected to the first control terminal.

9. A control method of a pixel driving circuit for controlling the pixel driving circuit according to any one of claims 1 to 8, wherein a drain reset phase is included in one light emitting period of the light emitting device, the control method comprising:

and in the drain electrode resetting stage, controlling the first resetting subcircuit to enable the signal of the first signal end to be written into the third node so as to reset the third node.

10. The method of claim 9, further comprising a compensation sub-circuit electrically connected to the third node, the first node, and the second control terminal, respectively, wherein one light emitting period of the light emitting device further comprises a gate reset phase, the method further comprising:

and in the grid resetting stage, controlling the first resetting subcircuit and the compensating subcircuit to enable the signal of the first signal end to be written into the first node so as to reset the first node.

11. The control method of a pixel driving circuit according to claim 9, wherein one light emitting period of the light emitting device further includes an anode reset phase, the control method further comprising:

And in the anode resetting stage, controlling a second light-emitting control sub-circuit and the first resetting circuit to enable signals of the first signal end to be written into the anode of the light-emitting device so as to reset the anode of the light-emitting device.

12. A display panel comprising a pixel driving circuit according to any one of claims 1 to 18.

13. A display device comprising the display panel according to claim 12.