CN117198217A

CN117198217A - Pixel driving circuit, control method thereof and display panel

Info

Publication number: CN117198217A
Application number: CN202311182820.2A
Authority: CN
Inventors: 马永龙; 叶新; 刘翔鹏; 周茂林; 杨波
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2023-09-13
Filing date: 2023-09-13
Publication date: 2023-12-08

Abstract

The disclosure provides a pixel driving circuit, a control method thereof and a display panel, and relates to the technical field of display. The pixel driving circuit includes: the writing unit is electrically connected with the data signal end, the second node and the first control end; the driving unit is electrically connected with the second node, the third node and the first node; the compensation unit is electrically connected with the third node, the first node and the second control end; the storage unit is electrically connected with the fourth node and the first node; the control unit is electrically connected with the first voltage end, the fourth node and the reset control end and is configured to write the signal of the first voltage end into the fourth node under the control of the signal of the reset control end; and the write-in unit is electrically connected with the second node, the fourth node and the third control end and is configured to write the signal of the second node into the fourth node under the control of the signal of the third control end. The problem that bright spots appear when the display panel displays a black picture is solved.

Description

Pixel driving circuit, control method thereof and display panel

Technical Field

The disclosure relates to the technical field of display, and in particular relates to a pixel driving circuit, a control method thereof and a display panel.

Background

Organic Light-Emitting Diode (OLED) display panels are becoming more and more widely used due to their high brightness, low power consumption, high contrast ratio, and the like. However, when the OLED display panel displays a black screen, bright spots often appear, which affects the display effect.

Disclosure of Invention

The embodiment of the disclosure provides a pixel driving circuit, a control method thereof and a display panel, which improve the problem that the display panel has bright spots when displaying a black picture.

In order to achieve the above object, the embodiments of the present disclosure adopt the following technical solutions:

in one aspect, there is provided a pixel driving circuit including:

the writing unit is electrically connected with the data signal end, the second node and the first control end and is configured to write signals of the data signal end into the second node under the control of signals of the first control end;

a driving unit electrically connected with the second node, the third node and the first node and configured to write a signal of the second node into the third node under the control of a signal of the first node;

the compensation unit is electrically connected with the third node, the first node and the second control end and is configured to write the signal of the third node into the first node under the control of the signal of the second control end;

a storage unit electrically connected to a fourth node and the first node and configured to store a voltage between the fourth node and the first node;

the control unit is electrically connected with the first voltage end, the fourth node and the reset control end and is configured to write the signal of the first voltage end into the fourth node under the control of the signal of the reset control end;

and the write-in unit is electrically connected with the second node, the fourth node and the third control end and is configured to write the signal of the second node into the fourth node under the control of the signal of the third control end.

In some embodiments, the control unit includes a ninth transistor having a first pole electrically connected to the fourth node, a second pole electrically connected to the first voltage terminal, and a control pole electrically connected to the reset control terminal.

In some embodiments, the control unit further includes a first capacitor, one of the plates of the first capacitor is electrically connected to the first voltage terminal, and the other plate of the first capacitor is electrically connected to the fourth node.

In some embodiments, the write-back unit includes an eighth transistor, a first pole of the eighth transistor is electrically connected to the fourth node, a second pole of the eighth transistor is electrically connected to the second node, and a control pole of the eighth transistor is electrically connected to the third control terminal.

In some embodiments, the memory cell includes a second capacitor, one of the plates of the second capacitor is electrically connected to the first node, and the other plate of the second capacitor is electrically connected to the fourth node.

In some embodiments, the light emitting device further comprises a first reset unit, a second reset unit and a light emitting control unit;

the first reset unit is electrically connected with the first node, a first reset end and the reset control end, and is configured to write a signal of the first reset end into the first node under the control of a signal of the reset control end;

the second reset unit is electrically connected with a second reset end, an anode of the light emitting device and the first control end, and is configured to write a signal of the second reset end into the anode of the light emitting device under the control of a signal of the first control end;

the light-emitting control unit is electrically connected with the first voltage terminal, the second node, the third node, an anode of the light-emitting device and the light-emitting control terminal, and is configured to conduct between the first voltage terminal and the second node and conduct between the third node and the anode of the light-emitting device under the control of signals of the light-emitting control terminal.

In another aspect, a control method of a pixel driving circuit is provided, for controlling the pixel driving circuit, where a working period of the pixel driving circuit includes a reset phase, a data writing phase, and the control method includes:

writing a first reset signal to a first node and a first voltage signal to a fourth node in the reset phase;

controlling the fourth node to hold the first voltage signal during the data writing stage, writing a data signal and a compensation signal to the first node;

and in the data supplementing and writing stage, writing the data signal into the fourth node.

In some embodiments, the pixel driving circuit further includes a first reset unit electrically connected to the first reset terminal and the first node, and writing the first reset signal to the first node includes: controlling the first reset unit to conduct between the first reset terminal and the first node so as to enable the first reset signal of the first reset terminal to be written into the first node;

the writing the first voltage signal to the fourth node includes: and controlling the control unit to conduct between a first voltage terminal and the fourth node so as to enable the first voltage signal of the first voltage terminal to be written into the fourth node.

In some embodiments, the writing the data signal to the fourth node comprises: and controlling the write-in unit to conduct between a data signal end and a second node, and controlling the write-in unit to conduct between the second node and a fourth node so as to write the data signal of the data signal end into the fourth node.

In still another aspect, there is provided a display panel including:

a substrate;

a plurality of light emitting devices disposed on a first side of the substrate;

the pixel driving circuit is arranged on the first side of the substrate and is electrically connected with at least one light emitting device.

Drawings

In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to a person of ordinary skill in the art.

FIG. 1 illustrates an application scenario diagram of a display panel;

fig. 2 exemplarily shows a schematic structural view of a display panel;

fig. 3 shows a circuit schematic of a pixel driving circuit in the related art;

fig. 4 exemplarily shows a partial block diagram of a pixel driving circuit;

fig. 5 exemplarily shows a block diagram of a structure of a pixel driving circuit;

fig. 6 exemplarily shows a circuit schematic of a pixel driving circuit;

fig. 7 exemplarily shows a partial signal timing diagram of a pixel driving circuit;

fig. 8 exemplarily shows a circuit schematic of another pixel driving circuit;

fig. 9 exemplarily shows a partial signal timing diagram of another pixel driving circuit;

fig. 10 exemplarily shows a block diagram of steps of a control method of a pixel driving circuit.

Detailed Description

The following description of the technical solutions in the embodiments of the present disclosure will be made clearly and completely with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person of ordinary skill in the art would obtain without making any inventive effort are within the scope of protection of this disclosure.

In the embodiments of the present disclosure, the words "first," "second," "third," "fourth," etc. are used to distinguish between the same item or similar items that have substantially the same function and function, but merely for clarity of description of the technical solutions of the embodiments of the present disclosure, and are not to be construed as indicating or implying a relative importance or implying an indication of the number of technical features indicated.

In the embodiments of the present disclosure, the meaning of "a plurality" means two or more, and the meaning of "at least one" means one or more, unless specifically defined otherwise.

In the embodiments of the present disclosure, the azimuth or positional relationship indicated by the terms "upper", "lower", etc., are based on the azimuth or positional relationship shown in the drawings, and are merely for convenience of description and simplification of the description, and do not indicate or imply that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus should not be construed as limiting the present disclosure.

In the circuit provided by the embodiment of the present disclosure, the first node, the second node, the third node, the fourth node, the fifth node, and other nodes do not represent actually existing components, but represent junction points of related electrical connections in the circuit diagram, that is, the nodes are equivalent nodes of junction points of related electrical connections in the circuit diagram.

The control of each transistor is the gate of the transistor, one of the source and drain of the first transistor, and the second transistor is the other of the source and drain of the transistor. Since the source and drain of a transistor may be symmetrical in structure, the source and drain thereof may be indistinguishable in structure, that is, the first and second poles of the transistor in embodiments of the present disclosure may be indistinguishable in structure. Illustratively, in the case where the transistor is a P-type transistor, the first pole of the transistor is the source and the second pole is the drain; illustratively, in the case where the transistor is an N-type transistor, the first pole of the transistor is the drain and the second pole is the source.

Fig. 1 shows an exemplary application scenario diagram of a display device. As shown in fig. 1, some embodiments of the present disclosure provide a display device 100 that may display devices whether in motion (e.g., video) or stationary (e.g., still image) and whether textual or image. For example, the display device 100 may be a mobile phone, a wireless device, a Personal Data Assistant (PDA), a handheld or portable computer, a GPS receiver/navigator, a camera, an MP4 video player, a video camera, a game console, a watch, a clock, a calculator, a television monitor, a flat panel display, a computer monitor, an automotive display (e.g., an odometer display, etc.), a navigator, a cabin controller and/or display, a display of a camera view (e.g., a display of a rear view camera in a vehicle), an electronic photo, an electronic billboard or sign, a projector, a building structure, packaging, and aesthetic structures (e.g., a display of an image for a piece of jewelry), and the like. In fig. 1, the display device 100 is schematically illustrated as an in-vehicle center control.

The display device 100 includes a display panel, and the display panel 110 may be an electroluminescent display panel or a photoluminescent display panel. In the case where the display panel 110 is an electroluminescent display panel, the electroluminescent display panel may be an Organic Light-Emitting Diode (OLED) display panel or a quantum dot electroluminescent (Quantum Dot Light Emitting Diode, QLED) display panel. In the case where the display panel 110 is a photoluminescent display panel, the photoluminescent display panel may be a quantum dot photoluminescent display panel.

Some embodiments of the present disclosure are illustrated with the display panel 110 being an Organic Light-Emitting Diode (OLED) display panel.

Fig. 2 schematically illustrates a schematic view of a display panel, and as illustrated in fig. 2, the display panel 110 includes a substrate 111, and a plurality of sub-pixels P, a plurality of gate lines GL, and a plurality of data lines DL disposed on a first side of the substrate 111.

The substrate 111 may be a rigid substrate or a flexible substrate, and may be selectively arranged according to actual needs.

Illustratively, the substrate 111 is a rigid substrate. For example, the rigid substrate may be a glass substrate or a PMMA (Polymethyl methacrylate ) substrate or the like.

Illustratively, the substrate 111 may be a flexible substrate. For example, the flexible substrate may be a PET (polyethylene terephthalate) substrate, a PEN (Polyethylene naphthalate twoformic acid glycol ester, polyethylene naphthalate) substrate, a PI (Polyimide) substrate, or the like.

The display panel 110 may have a display area AA and a non-display area NA electrically connected to the display area AA. The non-display area NA may be located at one side, two sides, or three sides of the display area AA, or the non-display area NA may be disposed around the display area AA. The plurality of subpixels P, the plurality of gate lines GL, and the plurality of data lines DL may be located in the display area AA.

Illustratively, the plurality of subpixels P may be arranged in an array. For example, a plurality of sub-pixels P are arranged in an array to form a plurality of sub-pixel rows and a plurality of sub-pixel columns, and the plurality of sub-pixels P in one sub-pixel row are arranged along the first direction X, and the plurality of sub-pixels P in one sub-pixel column are arranged along the second direction Y.

Wherein the first direction X and the second direction Y cross each other. The included angle between the first direction X and the second direction Y can be selected and set according to actual needs. Illustratively, the angle between the first direction X and the second direction Y may be 85 °, 88 °, 90 °, 92 °, 95 °, or the like.

The sub-pixel P may include a pixel driving circuit and a light emitting device electrically connected to the pixel driving circuit. When the display panel 110 is operated, the light emitting device may emit light under the driving of the pixel driving circuit.

For example, one data line DL may be electrically connected to a plurality of pixel driving circuits in the same sub-pixel column, and one gate line GL may be electrically connected to a plurality of pixel driving circuits in the same sub-pixel row. In practical application, a plurality of pixel driving circuits in the same sub-pixel row may be electrically connected to a plurality of gate lines GL. The number of the gate lines GL electrically connected to the plurality of pixel driving circuits in the same sub-pixel row may be determined according to the structure of the pixel driving circuits.

With continued reference to fig. 2, one side of the substrate 111 is further provided with a scan driving circuit, which includes a plurality of cascaded shift registers 112, where the shift registers 112 include output terminals, and the output terminals of the shift registers 112 may be electrically connected to the gate lines GL. When the scan driving circuit works, the output ends of the plurality of cascaded shift registers 112 output scan signals to the pixel driving circuit step by step through the gate lines GL.

Illustratively, the scan driving circuit is disposed within the non-display area NA. Of course, in the practical application process, in order to reduce the frame size of the display panel 110, at least part of the structure of the scan driving circuit may be disposed in the display area AA.

Fig. 3 shows a circuit schematic of a pixel driving circuit in the related art. As shown in fig. 3, the pixel driving circuit in the related art includes a transistor M4, a driving transistor M3, a transistor M2, and a capacitor C. In the data writing stage t2, the data signal Vdata is written into the node n1 via the transistor M4, the driving transistor M3, and the transistor M2 in order, and stored in the capacitor C. In the light emitting stage, the data signal written through the node n1 controls the driving transistor M3, thereby controlling the driving circuit flowing into the light emitting device OLED, and thus controlling the light emission of the light emitting device OLED.

However, the path of the transistor M4 to the node n1 is loaded more (for example, the path of the transistor M4 to the node n1 includes a via hole, and the resistance of the via hole is larger), so that the data signal written in the node n1 is smaller than the theoretical value, and a display defect occurs. Especially when the display panel is a large-size display panel such as a folded product or a vehicle-mounted product, the display defect is more obvious.

For example, the threshold voltage of the driving transistor M3 is vth= -2.5V, when the display panel displays a black picture, the data signal vdata=7v, the theoretical value of the writing signal at the node n1 is vdata+vth=7v-2.5v=4.5v, and when the signal at the node n1 is 4.5V, the driving transistor M3 can be controlled to be turned off. In practice, however, vdata passes through the driving transistor M3 and the driving transistor M2 to reach the node n1. In this process, vdata is lost in the wiring and the via hole, the voltage value actually written into the node n1 is smaller than 4.5V, if the process fluctuates, the wiring design is too narrow, the hole etching is abnormal, and the like, the voltage value is smaller, which can cause Vgs < Vth of the driving transistor M3, the driving transistor M3 is turned on, and the pixel emits light. The specific expression is that bright spots are generated when a black picture is displayed, the picture display quality is affected, and the bright spots are named as bright spots caused by 'n 1-point writing shortage'. In actual product bright spot data statistics, the occupancy of such bright spots in all types of bright spots is 25%.

In view of this, the embodiments of the present disclosure provide a pixel driving circuit that improves bright spots due to insufficient writing of the gate voltage of the driving transistor.

Fig. 4 exemplarily shows a partial block diagram of a pixel driving circuit. As shown in fig. 4, the pixel driving circuit includes a writing unit 10, a driving unit 20, a compensation unit 30, a storage unit 40, a control unit 50, and a compensation unit 50.

The writing unit 10 is electrically connected to the data signal terminal Vdata, the second node N2, and the first control terminal G1. The writing unit 10 is configured to write a signal of the data signal terminal Vdata to the second node N2 under the signal control of the first control terminal G1.

The data signal terminal Vdata may be electrically connected to the data line DL to receive the data signal in the data line DL. The first control terminal G1 may be electrically connected to one of the gate lines GL such that the first control terminal G1 receives the scan signal output from the shift register 112 through the gate line GL.

For example, when the signal of the first control terminal G1 is a low level signal, the data signal terminal Vdata and the second node N2 are turned on by the writing unit 10, so that the data signal of the data signal terminal Vdata is written into the second node N2.

Fig. 6 exemplarily shows a circuit schematic of a pixel driving circuit. Illustratively, as shown in fig. 6, the writing unit 10 includes a fourth transistor T4, a first electrode of the fourth transistor T4 is electrically connected to the second node N2, a second electrode of the fourth transistor T4 is electrically connected to the data signal terminal Vdata, and a control electrode of the fourth transistor T4 is electrically connected to the first control terminal G1. The fourth transistor T4 is a P-type transistor, and when the first control terminal G1 is a low level signal, the fourth transistor T4 is turned on.

The driving unit 20 is electrically connected to the second node N2, the third node N3, and the first node N1. The driving unit 20 is configured to write the signal of the second node N2 to the third node N3 under the control of the signal of the first node N1.

For example, when the signal of the first node N1 is a low level signal, the second node N2 and the third node N3 are turned on by the driving unit 20 so that the signal of the second node N2 is written into the third node N3.

Illustratively, with continued reference to fig. 6, the driving unit 20 includes a driving transistor T3, a first pole of the driving transistor T3 is electrically connected to the third node N3, a second pole of the driving transistor T3 is electrically connected to the second node N2, and a control pole of the driving transistor T3 is electrically connected to the first node N1. The driving transistor T3 is a P-type transistor, and when the first node N1 is a low level signal, the driving transistor T3 is turned on.

The compensation unit 30 is electrically connected to the third node N3, the first node N1, and the second control terminal G2. The compensation unit 30 is configured to write the signal of the third node N3 to the first node N1 under the control of the signal of the second control terminal G2.

For example, when the second control terminal G2 is a low level signal, the third node N3 and the first node N1 are turned on by the compensation unit 30, so that the signal of the third node N3 is written into the first node N1.

Illustratively, with continued reference to fig. 6, the compensation unit 30 includes a second transistor T2, a first pole of the second transistor T2 is electrically connected to the first node N1, a second pole of the second transistor T2 is electrically connected to the third node N3, and a control pole of the second transistor T2 is electrically connected to the second control terminal G2. The second transistor T2 is a P-type transistor, and when the second control terminal G2 is a low level signal, the second transistor T2 is turned on.

The memory cell 40 is electrically connected to the fourth node N4 and the first node N1. The storage unit 40 is configured to store the signal of the first node N1.

Illustratively, with continued reference to FIG. 6, the memory cell 40 includes a second capacitor C2, one plate of the second capacitor C2 being electrically connected to the fourth node N4, and the other plate of the second capacitor C2 being electrically connected to the first node N1.

The control unit 50 is electrically connected to the first voltage terminal VDD, the fourth node N4, and the Reset control terminal Reset. The control unit 50 is configured to write a signal of the first voltage terminal VDD to the fourth node N4 under the control of a signal of the Reset control terminal Reset.

The signal of the first voltage terminal VDD is a first voltage signal, which may be a constant voltage signal. For example, the first voltage signal is a constant high level signal.

For example, when the Reset control terminal Reset is a low level signal, the control unit 50 is turned on between the first voltage terminal VDD and the fourth node N4, so that the first voltage signal of the first voltage terminal VDD is written into the fourth node N4.

Illustratively, with continued reference to fig. 6, the control unit 50 includes a ninth transistor T9 and a first capacitor C1, a first pole of the ninth transistor T9 is electrically connected to the fourth node N4, a second pole of the ninth transistor T9 is electrically connected to the first voltage terminal VDD, a control pole of the ninth transistor T9 is electrically connected to the Reset control terminal Reset, one of the plates of the first capacitor C1 is electrically connected to the first voltage terminal VDD, and the other plate of the first capacitor C1 is electrically connected to the fourth node N4. The ninth transistor T9 may be a P-type transistor, and the ninth transistor T9 is turned on when the signal of the reset signal terminal is a low level signal.

The write-up unit 50 is electrically connected to the second node N2, the fourth node N4, and the third control terminal DW. The write-up unit 50 is configured to write the signal of the second node N2 to the fourth node N4 under the control of the signal of the third control terminal DW.

For example, when the third control terminal DW is a low level signal, the second node N2 and the fourth node N4 are turned on by the write-complement unit 50, so that the signal of the second node N2 is written into the fourth node N4.

Illustratively, with continued reference to fig. 6, the write-up unit 50 includes an eighth transistor T8, a first pole of the eighth transistor T8 is electrically connected to the fourth node N4, a second pole of the eighth transistor T8 is electrically connected to the second node N2, and a control pole of the eighth transistor T8 is electrically connected to the third control terminal DW. The eighth transistor T8 may be a P-type transistor, and the eighth transistor T8 is turned on when the third control terminal DW is a low level signal.

Fig. 5 exemplarily shows a block diagram of a structure of a pixel driving circuit. As shown in fig. 5, in the practical application process, the pixel driving circuit may further include a first reset unit 70, a second reset unit 80, and a light emission control unit 9050.

The first Reset unit 70 is electrically connected to the first node N1, the first Reset terminal Vinit1, and the Reset control terminal Reset. The first Reset unit 70 is configured to write a signal of the first Reset terminal Vinit1 to the first node N1 under the control of a signal of the Reset control terminal Reset.

For example, when the Reset control terminal Reset is a low level signal, the first Reset unit 70 is turned on between the first Reset terminal Vinit1 and the first node N1, and the first Reset signal of the first Reset terminal Vinit1 is written into the first node N1 to Reset the first node N1.

Illustratively, with continued reference to fig. 6, the first Reset unit 70 includes a first transistor T1, a first pole of the first transistor T1 is electrically connected to the first node N1, a second pole of the first transistor T1 is electrically connected to the first Reset terminal Vinit1, and a control pole of the first transistor T1 is electrically connected to the Reset control terminal Reset. The first transistor T1 may be a P-type transistor, and the first transistor T1 is turned on when the Reset control terminal Reset is a low level signal.

The second reset unit 80 is electrically connected to the second reset terminal Vinit2, the anode of the light emitting device OLED, and the first control terminal G1. The second reset unit 80 is configured to write a signal of the second reset terminal Vinit2 to the anode of the light emitting device OLED under the control of the signal of the first control terminal G1.

For example, when the first control terminal G1 is a low level signal, the second reset terminal Vinit2 is turned on with the anode of the light emitting device OLED through the second reset unit 80, and the second reset signal of the second reset terminal Vinit2 is written into the anode of the light emitting device OLED to reset the anode of the light emitting device OLED.

Illustratively, with continued reference to fig. 6, the second reset unit 80 includes a seventh transistor T7, a first electrode of the seventh transistor T7 is electrically connected to the anode of the light emitting device OLED, a second electrode of the seventh transistor T7 is electrically connected to the second reset terminal Vinit2, and a control electrode of the seventh transistor T7 is electrically connected to the first control terminal G1. The seventh transistor T7 may be a P-type transistor, and the seventh transistor T7 is turned on when the first control terminal G1 is a low level signal.

The light emission control unit 90 is electrically connected to the first voltage terminal VDD, the second node N2, the third node N3, the anode of the light emitting device OLED, and the light emission control terminal EM, and the light emission control unit 90 is configured to conduct between the first voltage terminal VDD and the second node N2 and conduct between the third node N3 and the anode of the light emitting device OLED under the signal control of the light emission control terminal EM.

For example, when the emission control terminal EM is a low level signal, the first voltage terminal VDD and the second node N2 and the third node N3 and the anode of the light emitting device OLED are turned on by the emission control unit 90.

Illustratively, with continued reference to fig. 6, the light emission control unit 90 includes a fifth transistor T5 and a sixth transistor T6, the first pole of the fifth transistor T5 is electrically connected to the second node N2, the second pole of the fifth transistor T5 is electrically connected to the first voltage terminal VDD, the control pole of the fifth transistor T5 is electrically connected to the light emission control terminal EM, the first pole of the sixth transistor T6 is electrically connected to the anode of the light emitting device OLED, the second pole of the sixth transistor T6 is electrically connected to the third node N3, and the control pole of the sixth transistor T6 is electrically connected to the light emission control terminal EM. The fifth and sixth transistors T5 and T6 may be P-type transistors, and the fifth and sixth transistors T5 and T6 are turned on when the light emission control terminal EM is a low level signal.

The disclosure also provides a control method of the pixel driving circuit, which is used for controlling the pixel driving circuit. The operation of the pixel drive circuit may include a plurality of duty cycles, each of which may be one image frame. Fig. 7 exemplarily shows a partial signal timing diagram of a pixel driving circuit. As shown in fig. 7, one duty cycle includes a reset phase t1, a data writing phase t2, a data writing phase t3, and a light emitting phase t5.

Fig. 10 exemplarily shows a block diagram of steps of a control method of a pixel driving circuit. As shown in fig. 10, the control method of the pixel driving circuit includes the following steps.

Step S100: in the reset phase, a first reset signal is written to the first node and a first voltage signal is written to the fourth node.

The first reset signal is written into the first node N1, and the signal written into the first node N1 in the previous working period can be covered, so that the reset of the first node N1 is realized.

In some embodiments, when the pixel driving circuit further includes the first reset unit 70, writing the first reset signal to the first node in step S100 includes the following sub-steps.

Step S110: the first reset unit 70 is controlled to conduct between the first reset terminal Vinit1 and the first node N1, so that the first reset signal of the first reset terminal Vinit1 is written into the first node N1.

As illustrated in fig. 6 and 7, the first Reset unit 70 includes a first transistor T1, a first electrode of the first transistor T1 is electrically connected to the first node N1, a second electrode of the first transistor T1 is electrically connected to the first Reset terminal Vinit1, and a control electrode of the first transistor T1 is electrically connected to the Reset control terminal Reset. When the first transistor T1 is a P-type transistor, the Reset control terminal Reset is turned on with a low level signal, and the first transistor T1 is turned on, so that the first Reset signal of the first Reset terminal Vinit1 is written into the first node N1.

Writing the first voltage signal to the fourth node N4 may cause the first voltage signal to be stored in the memory cell 40.

In some embodiments, in step 100, the first voltage signal is written to the fourth node, including the following substeps.

Step S120: the control unit 50 is controlled to conduct between the first voltage terminal VDD and the fourth node N4 so that the first voltage signal of the first voltage terminal VDD is written into the fourth node N4.

Illustratively, with continued reference to fig. 6, the control unit 50 includes a ninth transistor T9, a first pole of the ninth transistor T9 being electrically connected to the fourth node N4, a second pole of the ninth transistor T9 being electrically connected to the first voltage terminal VDD, and a control pole of the ninth transistor T9 being electrically connected to the Reset control terminal Reset. When the ninth transistor T9 is a P-type transistor, the Reset control terminal Reset is a low level signal, and the ninth transistor T9 is turned on to write the first voltage signal of the first voltage terminal VDD into the fourth node N4.

As shown in fig. 6 and fig. 7, in the actual application process, in the Reset stage T1, the Reset control terminal Reset is a low level signal, the light emitting control terminal EM, the first control terminal G1, the second control terminal G2, and the third control terminal DW are all high level signals, the first transistor T1 and the ninth transistor T9 are turned on, and the other transistors are turned off.

Step S200: in the data writing stage, the fourth node is controlled to maintain the first voltage signal, and the data signal and the compensation signal are written into the first node.

The compensation signal may be a threshold voltage Vth of the driving transistor T3.

As shown in fig. 6 and 7, in the data writing period T2, the first control terminal G1 and the second control terminal G2 are low-level signals, the light emitting control terminal EM, the Reset control terminal Reset, and the third control terminal DW are high-level signals, the fourth transistor T4, the driving transistor T3, and the second transistor T2 are turned on, and the other transistors are turned off. The data signal is written into the first node N1 through the fourth transistor T4, the driving transistor T3, and the second transistor T2 in this order. Let the data signal be Vdata, vgs of the driving transistor T3 be the level V1 of the first node N1 minus the level V2 of the second node N2, i.e., vgs=v1-V2. Vgs=vth when the first node N1 is no longer writing a signal, since vgs=v1-V2, i.e., v1=vgs+v2, i.e., v1=vth+vdata.

In the data writing period t2, the level V4 of the fourth node N4 maintains the first voltage signal VDD, so the voltage across the memory cell 40 is v4—v1=vdd-Vth-Vdata. For example, the memory cell 40 includes a second capacitor C2, and the voltage across the second capacitor C2 is VDD-Vth-Vdata.

For example, with continued reference to fig. 6 and 7, the control unit 50 may further include a first capacitor C1, one plate of the first capacitor C1 is electrically connected to the first voltage terminal VDD, and the other plate of the first capacitor C1 is electrically connected to the fourth node N4. In the data writing stage T2, the Reset control terminal Reset is a high level signal, the ninth transistor T9 is turned off, and the fourth node N4 maintains the first voltage signal VDD under the action of the first capacitor C1.

Illustratively, referring to fig. 8 and 9, the control unit 50 includes a ninth transistor T9 that does not include the first capacitor C1. In the data writing stage T2, the Reset control terminal Reset is a low level signal, the ninth transistor T9 is turned on, and the first voltage signal VDD of the first voltage terminal VDD is written into the fourth node N4 through the ninth transistor T9, so that the fourth node N4 maintains the first voltage signal VDD.

Step S300: in the data write-in phase, a data signal is written to the fourth node.

When the fourth node N4 writes the data signal Vdata, the level V4 of the fourth node N4 is Vdata. Since the voltage V4-V1 between the two plates of the second capacitor C2 cannot be suddenly changed, the VDD-Vth-Vdata is maintained for a certain period of time. Thus, the level v1=v4- (VDD-Vth-Vdata) =vdata- (VDD-Vth-Vdata) =2vdata+vth-VDD of the first node N1.

For example, vdd=4.6v, vth= -2.5V, vdata=7v when displaying a black screen, v1= 2*7-2.5-4.6=6.9V. In the related art, the level of the first node N1 is vdata+vth=7-2.5=4.5V, and when the first node N1 has insufficient writing, the level of the first node N1 is less than 4.5V.

As can be seen, in the embodiment of the present disclosure, when displaying a black screen, the level V1 of the first node N1 is higher than the level of the first node N1 in the related art, reducing the probability that the driving transistor T3 is turned on, thereby preventing bright spots from occurring when displaying a black screen.

In some embodiments, writing the data signal to the fourth node N4 includes the following substeps.

Step S310: the write unit 10 is controlled to conduct between the data signal terminal Vdata and the second node N2, and the write unit 50 is controlled to conduct between the second node N2 and the fourth node N4, so that the data signal of the data signal terminal Vdata is written into the fourth node N4.

Illustratively, with continued reference to fig. 6 and 8, the write unit 10 includes a fourth transistor T4 and the write complement unit 50 includes an eighth transistor T8. In the data writing stage T3, the first control terminal G1 and the third control terminal DW are low level signals, and the fourth transistor T4 and the eighth transistor T8 are turned on, so that the data signals are written into the fourth node N4 sequentially through the fourth transistor T4 and the eighth transistor T8.

As shown in fig. 6 to 9, in the light emitting stage T5, the light emitting control terminal EM is a low level signal, the other signal terminals are high level signals, the fifth transistor T5 and the sixth transistor T6 are turned on, and when the driving transistor T3 is turned on, a driving current for driving the light emitting device OLED to emit light is formed between the first voltage terminal VDD and the second voltage terminal VSS; when a black picture is displayed, the driving transistor T3 is turned off.

In the embodiment of the disclosure, when the driving transistor T3 is turned on, the driving current is I1.

In the related art, when the driving transistor T3 is turned on, the driving current is I2.

As can be seen from this, i1=4xi2, i.e. the display brightness of the picture is higher in the embodiment of the present disclosure.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A pixel driving circuit, comprising:

2. The pixel driving circuit according to claim 1, wherein the control unit includes a ninth transistor, a first pole of the ninth transistor is electrically connected to the fourth node, a second pole of the ninth transistor is electrically connected to the first voltage terminal, and a control pole of the ninth transistor is electrically connected to the reset control terminal.

3. The pixel driving circuit according to claim 2, wherein the control unit further comprises a first capacitor, one of the plates of the first capacitor is electrically connected to the first voltage terminal, and the other plate of the first capacitor is electrically connected to the fourth node.

4. The pixel driving circuit according to claim 1, wherein the write-up unit includes an eighth transistor, a first pole of the eighth transistor is electrically connected to the fourth node, a second pole of the eighth transistor is electrically connected to the second node, and a control pole of the eighth transistor is electrically connected to the third control terminal.

5. The pixel driving circuit according to claim 1, wherein the memory cell comprises a second capacitor, one of the plates of the second capacitor is electrically connected to the first node, and the other plate of the second capacitor is electrically connected to the fourth node.

6. The pixel driving circuit according to any one of claims 1 to 5, further comprising a first reset unit, a second reset unit, a light emission control unit;

7. A control method of a pixel driving circuit for controlling the pixel driving circuit according to any one of claims 1 to 8, wherein one duty cycle of the pixel driving circuit includes a reset phase, a data writing phase, the control method comprising:

8. The method of claim 7, further comprising a first reset unit electrically connected to the first reset terminal and the first node, wherein writing the first reset signal to the first node comprises: controlling the first reset unit to conduct between the first reset terminal and the first node so as to enable the first reset signal of the first reset terminal to be written into the first node;

9. The method according to claim 7, wherein the writing the data signal to the fourth node includes: and controlling the write-in unit to conduct between a data signal end and a second node, and controlling the write-in unit to conduct between the second node and a fourth node so as to write the data signal of the data signal end into the fourth node.

10. A display panel, comprising:

a substrate;

a pixel driving circuit according to any one of claims 1 to 9, disposed on a first side of the substrate and electrically connected to at least one of the light emitting devices.