CN113903301A

CN113903301A - Shift register, scanning driving circuit, driving method, display panel and device

Info

Publication number: CN113903301A
Application number: CN202111204248.6A
Authority: CN
Inventors: 冯雪欢; 李永谦
Original assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Hefei BOE Zhuoyin Technology Co Ltd
Priority date: 2021-10-15
Filing date: 2021-10-15
Publication date: 2022-01-07
Anticipated expiration: 2041-10-15
Also published as: CN113903301B

Abstract

The embodiment of the disclosure provides a shift register, a scanning driving circuit, a driving method, a display panel and a device, and relates to the technical field of display, so as to improve the phenomenon of dynamic image smear and improve the image display effect. The driving method of the shift register comprises a plurality of line scanning periods, wherein each line scanning period comprises a scanning stage and a black insertion stage; the plurality of line scanning periods comprises at least M line scanning period groups, each line scanning period group comprises N line scanning periods, and the time sequences of the scanning phases of the N line scanning periods are the same; the black insertion phase of the line scan period begins at a time after the scan phase of the last line scan period; the duration of the black insertion phase is less than or equal to the reference time difference of the starting time of two scanning phases in the condition that scanning signals are output row by row in two adjacent row scanning periods, and the black insertion phase comprises M (N-1) time sequences at most. The driving method of the shift register of the embodiment of the disclosure is used for the shift register.

Description

Shift register, scanning driving circuit, driving method, display panel and device

Technical Field

The present disclosure relates to the field of display technologies, and in particular, to a shift register, a scan driving circuit, a driving method, a display panel, and a display device.

Background

The scan driving circuit is an important component in the display device. The scan driving circuit may include a plurality of cascaded shift registers, and each of the cascaded shift registers may be electrically connected to a row of traces in the display device. The scan driving circuit may input a scan signal line by line to a plurality of wirings (e.g., a gate line or an enable signal line, etc.) in the display device to enable the display device to perform a picture display.

However, when the display device switches from one frame to another frame during the display of the display device, an image smear phenomenon occurs, that is, when the display device switches from one frame to another frame, the viewer feels the image smear of the previous frame (also referred to as a moving image smear), thereby affecting the image display effect.

Disclosure of Invention

The present disclosure provides a shift register, a scan driving circuit, a driving method, a display panel and a device, so as to improve the phenomenon of dynamic image smear and improve the image display effect.

In one aspect, a method of driving a shift register is provided. The shift register includes a plurality of sub-shift registers, each sub-shift register corresponding to a line scanning period in one frame period, the line scanning period including a scanning phase and a black insertion phase. The plurality of line scanning periods corresponding to the plurality of sub-shift registers comprise at least M line scanning period groups, each line scanning period group comprises N line scanning periods, and the time sequences of the scanning stages of the N line scanning periods are the same; m is more than or equal to 1, N is more than or equal to 2, and M and N are integers. A time at which a black insertion phase of the line scanning period starts is after a scanning phase of a last line scanning period of the plurality of line scanning periods; the duration of the black insertion phase is less than or equal to the reference time difference of the starting times of two scanning phases in the condition that scanning signals are output row by row in two adjacent row scanning periods, and the black insertion phase of the plurality of row scanning periods comprises M (N-1) time sequences at most.

In some embodiments, the timing of the black insertion phases of the plurality of row scan periods is the same; or the black insertion stages of the plurality of line scanning periods comprise at least two time sequences, and the time sequences of the black insertion stages of at least two line scanning periods are the same; or the black insertion phases of the plurality of line scanning periods comprise at least two time sequences, and the time of the black insertion phase of the relatively earlier line scanning period is earlier than that of the black insertion phase of the relatively later line scanning period.

In some embodiments, the shift register includes eight sub-shift registers corresponding to eight row scan periods in one frame period, respectively. The eight line scanning periods comprise a line scanning period group, each line scanning period group comprises two line scanning periods, and the time sequences of eight black insertion phases of the eight line scanning periods are the same; or, the eight line scanning periods comprise two line scanning period groups, each line scanning period group comprising two line scanning periods; the eight black insertion stages of the eight line scanning periods comprise two time sequences, the time sequences of the black insertion stages of the first four line scanning periods are the same, and the time sequences of the black insertion stages of the last four line scanning periods are the same; or, the eight line scanning periods comprise four line scanning period groups, each line scanning period group comprising two line scanning periods; the eight black insertion phases of the eight row scanning periods comprise four time sequences, and the time sequences of the black insertion phases of each row scanning period group are the same.

In some embodiments of the present disclosure, in a frame period, time sequences of scanning phases of at least two line scanning periods are the same, so as to save idle time, and perform black insertion by using the saved idle time. Therefore, some embodiments of the present disclosure provide a driving method of a shift register, which can increase the black insertion period without compressing the Time of each scan period under the condition of a constant refresh frequency, that is, a black frame is inserted during the sub-pixel emitting light to perform normal image display, so as to increase the MPRT (Motion Picture Response Time), improve the phenomenon of Motion image smear, and improve the image display effect.

In another aspect, a shift register is provided. The shift register is used for executing the driving method of the shift register according to any one of the above embodiments. The shift register comprises a plurality of sub shift registers, and each sub shift register is electrically connected with a row of sub pixels. The sub shift register includes an input circuit and an output circuit. The input circuit is coupled with an input signal end and a first node; the input circuit is configured to transmit a scan input signal to the first node in response to the scan input signal being received at the input signal terminal; and transmitting the black inserted input signal to the first node in response to a black inserted input signal received at the input signal terminal. The output circuit is coupled to the first node, a first clock signal terminal CLKE and a first output signal terminal; the output circuit is configured to transmit a scan clock signal received at the first clock signal terminal to the first output signal terminal to cause the first output signal terminal to output a scan signal in a case where the scan input signal is transmitted to the first node; and transmitting the black insertion clock signal received at the first clock signal terminal to the first output signal terminal so that the first output signal terminal outputs a black insertion signal, in a case where the black insertion input signal is transmitted to the first node.

The shift register comprises M sub-shift register groups, each sub-shift register group comprises N adjacent sub-shift registers, M is not less than 1, N is not less than 2, and M and N are integers; the N sub-shift registers are configured to receive scanning clock signals with the same timing to output scanning signals with the same timing. The black insertion signal starts to be output after the data signal writing of a row of sub-pixels connected with the last sub-shift register in the plurality of sub-shift registers is finished; the duration of the black insertion signal is less than or equal to the reference time difference of the start time of two scanning signals under the condition that the scanning signals are output by two adjacent sub-shift registers line by line; the black insertion signals output by the plurality of sub shift registers include M (N-1) kinds of time sequences at most.

In yet another aspect, a scan driving circuit is provided. The scan driving circuit includes a plurality of shift registers as described in the above embodiments in cascade.

In some embodiments, each of the shift registers includes X sub-shift registers, X ≧ 2, and X is an integer. The scan driving circuit further includes a plurality of first clock signal line groups, each of the first clock signal line groups including at least X-M X (N-1) first clock signal lines. The plurality of first clock signal terminals of each shift register are coupled to the plurality of first clock signal lines of one first clock signal line group.

In some embodiments, the shift registers have the first clock signal terminals of the N sub-shift registers of each sub-shift register group coupled to the same first clock signal line, and different sub-shift register groups are coupled to different first clock signal lines. In the shift register, the first clock signal ends of all the other sub-shift registers except the M sub-shift register groups are respectively coupled with different first clock signal lines.

In another aspect, a driving method of a scan driving circuit is provided. The driving method is applied to the scanning driving circuit in any one of the above embodiments. Each frame period includes a plurality of line scanning periods, each line scanning period including a scanning phase and a black insertion phase; each sub-shift register of each shift register of the scan driving circuit is for performing one row scan period. In the scanning stage, the sub-shift register receives a scanning input signal and a scanning clock signal and outputs a scanning signal to control a row of sub-pixels electrically connected with the sub-shift register to emit light. And in the black insertion stage, the input circuit receives a black insertion input signal and a black insertion clock signal and outputs a black insertion signal so as to control a row of sub-pixels electrically connected with the sub-shift register to stop emitting light.

In some embodiments, the black insertion phase of the row scanning period performed by each sub-shift register of the shift register is after the scanning phase of the plurality of row scanning periods performed by the plurality of sub-shift registers of the shift register and before writing of a row of sub-pixel data signals corresponding to the row scanning period performed by one sub-shift register of the other shift registers.

In some embodiments, the black insertion phase of the row scan period performed by any of the sub-shift registers follows the scan phase of the row scan period performed by the last sub-shift register in the cascaded plurality of shift registers.

In still another aspect, a method of driving a shift register is provided. The shift register includes a plurality of sub-shift registers, each sub-shift register corresponding to a line scanning period in one frame period, the line scanning period including a scanning phase and a black insertion phase. The starting time of the black insertion phase is the same as the starting time of writing data signals of a row of sub-pixels driven by a set row scanning period, and the ratio of the duration of the black insertion phase to the duration of writing data signals of a row of sub-pixels driven by the set row scanning period is less than or equal to 1/2; the set line scanning time interval is a line scanning time interval corresponding to one sub-shift register of other shift registers.

In yet another aspect, a shift register is provided. The shift register is used for executing the driving method of the shift register according to the above embodiment. The shift register comprises a plurality of sub shift registers, and each sub shift register is electrically connected with a row of sub pixels. The sub-shift register includes a scan input circuit, a black insertion input circuit, and an output circuit. The scanning input circuit is coupled with a scanning input signal end and a first node; the scan-in circuit is configured to transmit a scan-in signal to the first node in response to a scan-in signal received at the scan-in signal terminal. The black insertion input circuit is coupled with a black insertion signal end and the first node; the black insertion input circuit is configured to transmit the black insertion input signal to the first node in response to a black insertion input signal received at the black insertion input signal terminal. The output circuit is coupled to the first node, a first clock signal terminal CLKE and a first output signal terminal; the output circuit is configured to transmit a scan clock signal received at the first clock signal terminal to the first output signal terminal to cause the first output signal terminal to output a scan signal in a case where the scan input signal is transmitted to the first node; and transmitting the black insertion clock signal received at the first clock signal terminal to the first output signal terminal so that the first output signal terminal outputs a black insertion signal, in a case where the black insertion input signal is transmitted to the first node.

The time for starting to output the black insertion signal is the same as the time for starting to write the data signals into the sub-pixels in one row connected with the setting sub-shift register, and the ratio of the duration of the black insertion signal to the duration of the data signals into the sub-pixels in one row connected with the setting sub-shift register is less than or equal to 1/2; the setting sub shift register is one sub shift register in other shift registers.

In yet another aspect, a display panel is provided. The display panel comprises the scanning driving circuit of any one of the embodiments.

In yet another aspect, a display device is provided. The display device comprises the display panel of the embodiment.

The advantageous effects of the shift register, the scan driving circuit, the driving method of the scan driving circuit, the display panel and the display device provided in some embodiments of the present disclosure are the same as the advantageous effects of the driving method of the shift register provided in the above technical solutions, and are not described herein again.

Drawings

In order to more clearly illustrate the technical solutions in the present disclosure, the drawings needed to be used in some embodiments of the present disclosure will be briefly described below, and it is apparent that the drawings in the following description are only drawings of some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art according to the drawings. Furthermore, the drawings in the following description may be regarded as schematic diagrams, and do not limit the actual size of products, the actual flow of methods, the actual timing of signals, and the like, involved in the embodiments of the present disclosure.

FIG. 1 is a block diagram of a display device according to some embodiments;

FIG. 2 is a block diagram of a display panel according to some embodiments;

FIG. 3 is a block diagram of another display panel according to some embodiments;

FIG. 4 is a circuit diagram of a subpixel according to some embodiments;

FIG. 5 is a timing diagram corresponding to the sub-pixel shown in FIG. 4 according to one of the related art;

FIG. 6 is a timing diagram corresponding to the sub-pixel of FIG. 4 according to some embodiments;

FIG. 7 is a block diagram of a shift register according to some embodiments;

FIG. 8 is a circuit diagram of a sub-shift register according to some embodiments;

FIG. 9 is a circuit diagram of another seed shift register according to some embodiments;

FIG. 10 is a circuit diagram of yet another sub-shift register according to some embodiments;

FIG. 11 is a block diagram of another shift register according to some embodiments;

FIG. 12 is a circuit diagram of a black insertion input circuit of a sub-shift register according to some embodiments;

FIG. 13 is a circuit diagram of yet another seed shift register according to some embodiments;

FIG. 14 is a block diagram of a scan driver circuit according to some embodiments;

FIG. 15 is a block diagram of another scan driver circuit according to some embodiments;

FIG. 16 is a timing diagram of a partial sub-shift register of a scan driver circuit according to some embodiments;

FIG. 17 is a timing diagram of clock signal lines of the scan driving circuit shown in FIG. 16;

FIG. 18 is a timing diagram of a portion of a sub-shift register of another scan driver circuit according to some embodiments;

FIG. 19 is a timing diagram of clock signal lines of the scan driving circuit shown in FIG. 18;

FIG. 20 is a timing diagram of a partial sub-shift register of yet another scan driver circuit according to some embodiments;

FIG. 21 is a timing diagram of clock signal lines of the scan driving circuit shown in FIG. 20;

FIG. 22 is a timing diagram of another scan driving circuit according to some embodiments;

FIG. 23 is a timing diagram of clock signal lines of the scan driving circuit shown in FIG. 22;

FIG. 24 is a timing diagram of still another scan driving circuit according to some embodiments;

fig. 25 is a timing chart of clock signal lines of the scan driver circuit shown in fig. 24.

Detailed Description

Technical solutions in some embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings, and it is obvious that the described embodiments are only a part of the embodiments of the present disclosure, and not all of the embodiments. All other embodiments obtained by a person of ordinary skill in the art based on the embodiments provided by the present disclosure belong to the protection scope of the present disclosure.

Unless the context requires otherwise, throughout the description and the claims, the term "comprise" and its other forms, such as the third person's singular form "comprising" and the present participle form "comprising" are to be interpreted in an open, inclusive sense, i.e. as "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "example", "specific example" or "some examples" and the like are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be included in any suitable manner in any one or more embodiments or examples.

In the following, the terms "first", "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of the present disclosure, "a plurality" means two or more unless otherwise specified.

In describing some embodiments, the expression "connected" and its derivatives may be used. For example, the term "connected" may be used in describing some embodiments to indicate that two or more elements are in direct physical or electrical contact with each other. The embodiments disclosed herein are not necessarily limited to the contents herein.

"at least one of A, B and C" has the same meaning as "A, B or at least one of C," each including the following combination of A, B and C: a alone, B alone, C alone, a and B in combination, a and C in combination, B and C in combination, and A, B and C in combination.

"A and/or B" includes the following three combinations: a alone, B alone, and a combination of A and B.

As used herein, the term "if" is optionally to be interpreted to mean "when … …" or "at … …" or "in response to a determination" or "in response to a detection", depending on the context. Similarly, the phrase "if determined … …" or "if [ stated condition or event ] is detected" is optionally to be construed to mean "upon determination … …" or "in response to determination … …" or "upon detection of [ stated condition or event ] or" in response to detection of [ stated condition or event ] ", depending on the context.

The use of "adapted to" or "configured to" herein is meant to be an open and inclusive language that does not exclude devices adapted to or configured to perform additional tasks or steps.

Additionally, the use of "based on" means open and inclusive, as a process, step, calculation, or other action that is "based on" one or more stated conditions or values may in practice be based on additional conditions or values beyond those stated.

As used herein, "about" or "approximately" includes the stated values as well as average values within an acceptable deviation range for the particular value, as determined by one of ordinary skill in the art in view of the measurement in question and the error associated with the measurement of the particular quantity (i.e., the limitations of the measurement system).

The transistors used in the circuits provided in the embodiments of the present disclosure may be thin film transistors, field effect transistors (e.g., oxide thin film transistors), or other switching devices with the same characteristics, and the thin film transistors are all taken as examples in the embodiments of the present disclosure for description.

In some embodiments, the control electrode of each transistor employed in the shift register is a gate electrode of the transistor, the first electrode is one of a source electrode and a drain electrode of the transistor, and the second electrode is the other of the source electrode and the drain electrode of the transistor. Since the source and the drain of the transistor may be symmetrical in structure, the source and the drain thereof may not be different in structure, that is, the first and the second poles of the transistor in the embodiment of the present disclosure may not be different in structure. Exemplarily, in case the transistor is a P-type transistor, the first pole of the transistor is a source and the second pole is a drain; illustratively, in the case where the transistor is an N-type transistor, the first pole of the transistor is the drain and the second pole is the source.

In the circuit provided by the embodiment of the present disclosure, the nodes do not represent actually existing components, but represent junctions of the relevant electrical connections in the circuit diagram, that is, the nodes are nodes equivalent to the junctions of the relevant electrical connections in the circuit diagram.

In embodiments of the present disclosure, the term "pull-up" means charging a node or an electrode of a transistor such that the absolute value of the level of the node or the electrode is raised, thereby achieving operation (e.g., conduction) of the corresponding transistor. The term "pull-down" means discharging a node or an electrode of a transistor such that the absolute value of the level of the node or the electrode is lowered, thereby achieving operation (e.g., turning off) of the corresponding transistor.

In the circuits provided in the embodiments of the present disclosure, the transistors are all exemplified by N-type transistors.

Some embodiments of the present disclosure provide a display device 2000, as shown in fig. 1, which display device 2000 may be any device that displays images, whether in motion (e.g., video) or stationary (e.g., still images), and whether textual or textual. More particularly, it is contemplated that the embodiments may be implemented in or associated with a variety of electronic devices such as, but not limited to, mobile telephones, wireless devices, Personal Data Assistants (PDAs), hand-held or portable computers, GPS receivers/navigators, cameras, MP4 video players, camcorders, game consoles, wrist watches, clocks, calculators, television monitors, flat panel displays, computer monitors, auto displays (e.g., odometer display, etc.), navigators, cockpit controls and/or displays, displays of camera views (e.g., of a rear view camera in a vehicle), electronic photographs, electronic billboards or signs, projectors, architectural structures, packaging, and aesthetic structures (e.g., a display of images for a piece of jewelry), and so forth.

In some embodiments, as shown in fig. 1. The display device 2000 includes the display panel 1000 described above.

The display device 2000 may further include a frame, a circuit board, a source driving chip, other electronic components, and the like. Wherein the display panel 1000 may be disposed within the frame.

The types of the display panel 1000 include various types, and the setting can be selected according to actual needs.

For example, the display panel 1000 may be: any one of an Organic Light Emitting Diode (OLED) display panel, a Quantum Dot Light Emitting Diode (QLED) display panel, a Micro Light Emitting Diode (Micro LED) display panel, and the like, which is not limited in this disclosure.

Some embodiments of the disclosure are schematically illustrated below by taking the display panel 1000 as an OLED display panel as an example.

In some embodiments, as shown in fig. 2 and fig. 3, the display panel 1000 has a display area a and a frame area B disposed beside the display area a. Here, the "side" refers to one side, two sides, three sides, or a peripheral side of the display area a, that is, the bezel area B may be located on one side, two sides, or three sides of the display area a, or the bezel area B may be disposed around the display area a.

In some embodiments, as shown in fig. 2 and 3, the display panel 1000 may include: a scan driving circuit 100 and a substrate 200. The substrate 200 is used to carry the scan driving circuit 100.

Here, the scan driving circuit 100 may be located in the frame region B or the display region a. The present disclosure is not limited thereto.

The types of the substrate 200 include various types, and the arrangement can be selected according to actual needs.

Illustratively, the substrate 200 may be a rigid substrate. The rigid substrate may be, for example, a glass substrate or a PMMA (Polymethyl methacrylate) substrate.

Illustratively, the substrate 200 may be a flexible substrate. The flexible substrate may be, for example, a PET (Polyethylene terephthalate) substrate, a PEN (Polyethylene naphthalate) substrate, a PI (Polyimide) substrate, or the like. In this case, the display panel 1000 may be a flexible display panel.

Here, the scanning driving circuit 100 may be, for example, a light emission control circuit or a gate driving circuit. In the disclosure, the scan driving circuit 100 is taken as a gate driving circuit for illustration.

In some embodiments, as shown in fig. 2 and 3, the display panel 1000 may further include: and a plurality of sub-pixels P disposed at one side of the substrate 200 and positioned at the display area a. The plurality of sub-pixels P may be arranged in a plurality of rows in the first direction X and a plurality of columns in the second direction Y, for example. Each row of the sub-pixels P may include a plurality of sub-pixels P, and each column of the sub-pixels P may include a plurality of sub-pixels P.

Here, the first direction X and the second direction Y intersect each other. The included angle between the first direction X and the second direction Y can be set according to actual needs. Exemplarily, the included angle between the first direction X and the second direction Y may be 85 °, 89 °, or 90 °, and the like.

In some embodiments, as shown in fig. 2 and 3, the display panel 1000 may further include: a plurality of gate lines GL and a plurality of data lines DL disposed at one side of the substrate 200 and positioned in the display area a. The gate lines GL extend along a first direction X, and the data lines DL extend along a second direction Y.

For example, the sub-pixels P arranged in a row along the first direction X may be referred to as the same row sub-pixels P, and the sub-pixels P arranged in a column along the second direction Y may be referred to as the same column sub-pixels P. The same row of subpixels P may be electrically connected to one gate line GL, and the same column of subpixels P may be electrically connected to one data line DL.

In some embodiments, as shown in fig. 4, each of the plurality of sub-pixels P may include a pixel driving circuit and a light emitting device electrically connected to the pixel driving circuit. The light emitting device may be an OLED.

For example, one gate line GL may be electrically connected to a plurality of pixel driving circuits in the same row of sub-pixels P, and one data line DL may be electrically connected to a plurality of pixel driving circuits in the same column of sub-pixels P.

The pixel driving circuit has various structures, and can be selectively arranged according to actual needs. For example, the structure of the pixel driving circuit may include a structure of "2T 1C", "3T 1C", "6T 1C", "7T 1C", "6T 2C", or "7T 2C". Where "T" represents a transistor, the number preceding "T" represents the number of transistors, "C" represents a storage capacitor, and the number preceding "C" represents the number of storage capacitors.

Here, during the use of the display panel 1000, the stability of the transistors and the light emitting devices in the pixel driving circuit may be reduced (e.g. the threshold voltage of the driving transistor is shifted), which may affect the display effect of the display panel 1000, and thus the sub-pixel P needs to be compensated.

The compensation method for the sub-pixel P can include various methods, and the arrangement can be selected according to actual needs. For example, a pixel compensation circuit may be provided in the sub-pixel P to internally compensate the sub-pixel P with the pixel compensation circuit. For another example, the driving transistor or the light emitting device may be sensed by a transistor inside the sub-pixel P, and the sensed data is transmitted to the external sensing circuit, so as to calculate a driving voltage value to be compensated by using the external sensing circuit and perform feedback, thereby implementing external compensation on the sub-pixel P.

The present disclosure schematically illustrates the structure and operation process of the sub-pixel P by taking the external compensation method (sensing the driving transistor) and the pixel driving circuit adopting the structure of "3T 1C" as an example.

Illustratively, as shown in fig. 4, the pixel driving circuit may include: a switching transistor T1, a driving transistor T2, a sensing transistor T3, and a storage capacitor Cst.

For example, as shown in fig. 4, the control electrode of the switching transistor T1 is electrically connected to the first scan signal terminal G1, the first electrode of the switching transistor T1 is electrically connected to the Data signal terminal Data, and the second electrode of the switching transistor T1 is electrically connected to the second node G. Wherein the switching transistor T1 is configured to transmit the Data signal received at the Data signal terminal Data to the second node G in response to the first scan signal received at the first scan signal terminal G1.

Here, the data signal may include, for example, a detection data signal, a display data signal, and a black insertion data signal. Wherein the detection data signal is used in a blanking period, the display data signal is used in a display period, and the black insertion data signal is used in a black insertion writing phase. Regarding the black insertion writing phase, the display period, and the blank period, reference may be made to the following description in some embodiments, which is not repeated herein.

For example, as shown in fig. 4, the control electrode of the driving transistor T2 is electrically connected to the second node G, the first electrode of the driving transistor T2 is electrically connected to the fourth voltage signal terminal ELVDD, and the second electrode of the driving transistor T2 is electrically connected to the third node S. Wherein the driving transistor T2 is configured to transmit the fourth voltage signal received at the fourth voltage signal terminal ELVDD to the third node S under the control of the voltage of the second node G.

For example, as shown in fig. 4, a first terminal of the storage capacitor Cst is electrically connected to the second node G, and a second terminal of the storage capacitor Cst is electrically connected to the third node S. Wherein the switching transistor T1 charges the storage capacitor Cst at the same time as the second node G is charged.

For example, as shown in fig. 4, the anode of the light emitting device is electrically connected to the third node S, and the cathode of the light emitting device is electrically connected to the fifth voltage signal terminal ELVSS. The light emitting device is configured to emit light under the cooperation of the fourth voltage signal from the third node S and the fifth voltage signal transmitted from the fifth voltage signal terminal ELVSS.

For example, as shown in fig. 4, the control electrode of the sensing transistor T3 is electrically connected to the second scan signal terminal G2, the first electrode of the sensing transistor T3 is electrically connected to the third node S, and the second electrode of the sensing transistor T3 is electrically connected to the sensing signal terminal Sense. Wherein the sensing transistor T3 is configured to detect an electrical characteristic of the driving transistor T2 in response to the second scan signal received at the second scan signal terminal G2 to achieve external compensation. The electrical characteristics include, for example, the threshold voltage and/or the carrier mobility of the driving transistor T2.

Here, the sensing signal terminal Sense may provide a reset signal for resetting the third node S or a sensing signal for sensing a threshold voltage of the driving transistor T2.

Based on the structure of the pixel driving circuit, as shown in fig. 2, a plurality of pixel driving circuits in the same row of sub-pixels P may be electrically connected to two gate lines GL (i.e., a first gate line and a second gate line). For example, each of the first scan signal terminals G1 may be electrically connected to a first gate line and receive a first scan signal transmitted by the first gate line; each of the second scan signal terminals G2 may be electrically connected to the second gate line and receive the second scan signal transmitted by the second gate line.

Note that one frame period may include, for example, a display period, a black insertion period, and a blanking period, which are performed in this order. In the display period, the sub shift register 10 may drive the corresponding sub pixel P for image display; in the black insertion period, the sub-shift register 10 may drive the corresponding sub-pixel P to display a black picture; in the blanking period, the sub-shift register 10 may drive the corresponding sub-pixel P for external compensation. Only the display period therein will be schematically described below.

In the display period, as shown in fig. 5, the operation process of the sub-pixel P may include, for example, a reset phase P1, a data write phase P2, and a light emission phase P3.

In the reset phase P1, the level of the second scan signal provided by the second scan signal terminal G2 is high, and the Sense signal terminal Sense provides a reset signal (the level of which is, for example, low). The sensing transistor T3 is turned on under the control of the second scan signal, receives a reset signal, and transmits the reset signal to the third node S, resetting the third node S.

In the Data writing phase P2, the level of the first scan signal provided by the first scan signal terminal G1 is at a high level, and the level of the display Data signal provided by the Data signal terminal Data is at a high level. The switching transistor T1 is turned on under the control of the first scan signal, receives the display data signal, and transmits the display data signal to the second node G while charging the storage capacitor Cst.

In the light emitting period P3, the level of the first scan signal provided by the first scan signal terminal G1 is at a low level, the level of the second scan signal provided by the second scan signal terminal G2 is at a low level, and the level of the fourth voltage signal provided by the fourth voltage signal terminal ELVDD is at a high level. The switching transistor T1 is turned off under the control of the first scan signal, and the sensing transistor T3 is turned off under the control of the second scan signal. The storage capacitor Cst starts discharging so that the voltage of the second node G is maintained at a high level. The driving transistor T2 is turned on under the control of the voltage of the second node G, receives the fourth voltage signal, and transmits the fourth voltage signal to the third node S, so that the light emitting device emits light under the cooperation of the fourth voltage signal and the fifth voltage signal transmitted from the fifth voltage signal terminal ELVSS.

In some embodiments, the scan driving circuit 100 and the plurality of sub-pixels P are located on the same side of the substrate 200. The scan driving circuit 100 may include a plurality of shift registers 1 cascaded, and one shift register 1 may be electrically connected to a plurality of pixel driving circuits in at least one row of the sub-pixels P. Illustratively, one shift register 1 includes a plurality of sub-shift registers 10, and each sub-shift register 10 is electrically connected to a plurality of pixel driving circuits in a row of sub-pixels P.

It should be noted that the first scan signal transmitted by the first scan signal terminal G1 and the second scan signal transmitted by the second scan signal terminal G2 are both provided by the scan driving circuit 100. That is, each sub-shift register 10 in the scan driving circuit 100 may be electrically connected to the first scan signal terminal G1 through a first gate line through which a first scan signal is transmitted to the first scan signal terminal G1, and electrically connected to the second scan signal terminal G2 through a second gate line through which a second scan signal is transmitted to the second scan signal terminal G2.

Of course, as shown in fig. 3, a plurality of pixel driving circuits in the same row of sub-pixels P may also be electrically connected to the same gate line GL. In this case, the first scan signal and the second scan signal are the same. In the scan driving circuit 100, each sub-shift register 10 is electrically connected to the first scan signal terminal G1 and the second scan signal terminal G2 through a corresponding gate line GL, and transmits signals to the first scan signal terminal G1 and the second scan signal terminal G2 through the gate line GL.

In the related art, during the display of the display panel 1000, an image smear phenomenon occurs during the process of switching the dynamic image, that is, when the display panel 1000 switches from one frame of image to another frame of image, the viewer may feel the image smear (also called dynamic image smear) of the previous frame, thereby affecting the image display effect.

Based on this, some embodiments of the present disclosure provide a driving method of shift registers, as shown in fig. 7, each shift register 1 includes a plurality of sub shift registers 10. Each sub-shift register 10 electrically connects a plurality of pixel driving circuits in one row of sub-pixels P (see fig. 2 and 3), and in conjunction with fig. 18 and 22, each sub-shift register 10 corresponds to one row scanning period in one frame period, each row scanning period including a scanning phase P6 and a black insertion phase P7.

It should be noted that, the scanning phase P6 in one row scanning period corresponding to each sub shift register 10 corresponds to the reset phase P1 and the data writing phase P2 of the plurality of pixel driving circuits electrically connected to one row of sub pixels P; for the description of the reset phase P1 and the data write phase P2, reference is made to the above description, which is not repeated herein. The black insertion phase P7 in a row scanning period corresponding to each sub-shift register 10 corresponds to the black insertion writing phase P4 electrically connected to a plurality of pixel driving circuits in a row of sub-pixels P, and the following description of the black insertion writing phase P4 can be referred to, which is not repeated herein.

In some embodiments, the plurality of line scan periods corresponding to the plurality of sub-shift registers 10 includes at least M line scan period groups, each line scan period group includes N line scan periods, and the timings of the scan phases P6 of the N line scan periods are the same; m is more than or equal to 1, N is more than or equal to 2, and M and N are integers. In this case, in the shift register 1, each group of the row scanning periods can save at least a reference time difference of times at which two scanning stages start in the case where N-1 adjacent two row scanning periods output scanning signals row by row. For example, each group of row scanning periods may save the duration of the data writing phase P2 for N-1 subpixels P. In this way, in one frame period, the M groups of row scanning periods in the shift register 1 can save at least the duration of the data writing phase P2 of the M × (N-1) sub-pixel P. Fig. 18 illustrates an example in which one row scanning period group 20 includes two row scanning periods, and fig. 22 illustrates an example in which two row scanning period groups 20 include two row scanning periods, respectively.

Wherein, the black insertion phase P7 of the row scanning period starts at a time after the scanning phase P6 of the last row scanning period of the plurality of row scanning periods, and the duration of each black insertion phase P7 is less than or equal to the reference time difference of the start times of two scanning phases P6 in the case that the scanning signals are output row by row in the adjacent two row scanning periods. For example, the duration of each black insertion phase P7 is less than or equal to the duration of the data writing phase P2 of the adjacent subpixel P. Further, the black insertion phase P7 of the plurality of row scanning periods includes M × (N-1) kinds of timings at most. That is, the black insertion phase P7 in the shift register 1 occupies at most the duration of the data writing phase P2 of the M × (N-1) subpixel P in one frame period.

As can be seen from the above description, some embodiments of the present disclosure provide a driving method of a shift register, in one frame period, to make the timings of the scan phases P6 of at least two line scan periods the same, so as to save idle time, and perform black insertion by using the saved idle time. Therefore, some embodiments of the present disclosure provide a driving method of a shift register, which can increase the Time of the black insertion phase P7, that is, insert a black Picture during the process of emitting light to perform normal image display of the sub-pixel P, on the basis of not compressing the Time of each scan phase P6, under the condition that the refresh frequency is constant, thereby increasing the MPRT (Motion Picture Response Time), improving the phenomenon of Motion Picture smear, and improving the image display effect.

In some embodiments, in each shift register 1, referring to fig. 18 and 20, the timing of the black insertion phase P7 of the plurality of row scanning periods is the same.

Illustratively, the shift register 1 includes eight sub-shift registers 10, and the eight sub-shift registers 10 correspond to eight line scanning periods in one frame period, respectively. Here, as shown in fig. 18 and 20, the eight row scanning periods include one row scanning period group, each of the row scanning period groups includes two row scanning periods, and the timings of the eight black insertion phases P7 of the eight row scanning periods are the same.

In other embodiments, in each shift register 1, referring to fig. 22, the black insertion phase P7 of the plurality of row scanning periods includes at least two timings, and the black insertion phase P7 of the relatively earlier row scanning period is earlier in time than the black insertion phase P7 of the relatively later row scanning period.

Illustratively, the shift register 1 includes eight sub-shift registers 10, and the eight sub-shift registers 10 correspond to eight line scanning periods in one frame period, respectively. Here, as shown in fig. 22, eight line scanning periods include two line scanning period groups, each of which includes two line scanning periods. The eight black insertion phases P7 of the eight row scanning periods include two timings, the timing of the black insertion phase P7 of the first four row scanning periods is the same, the timing of the black insertion phase P7 of the last four row scanning periods is the same, and the timing of the black insertion phase P7 of the first four row scanning periods is earlier than the timing of the black insertion phase P7 of the last four row scanning periods.

In still other embodiments, referring to fig. 24, the black insertion phase P7 of the plurality of row scan periods includes at least two timings, and the timings of the black insertion phase P7 of at least two row scan periods are the same.

Illustratively, as shown in fig. 24, the shift register 1 includes eight sub-shift registers 10, and the eight sub-shift registers 10 correspond to eight line scanning periods in one frame period, respectively. The eight line scanning periods comprise four line scanning period groups, and each line scanning period group comprises two line scanning periods; the eight black insertion phases P7 of the eight row scanning periods include four timings, and the timings of the black insertion phases P7 of each row scanning period group are the same.

Some embodiments of the present disclosure further provide a shift register 1, configured to perform the driving method of the shift register according to any one of the above embodiments. As shown in fig. 7 and 8, each shift register 1 includes a plurality of sub shift registers 10. Each sub shift register 10 electrically connects a plurality of pixel driving circuits in one row of sub pixels P (see fig. 2 and 3). The sub shift register 10 includes an input circuit 11 and an output circuit 12.

In some embodiments, as shown in fig. 7 and 8, the Input circuit 11 is coupled to an Input signal terminal Input (abbreviated as Iput in the figures and below) and a first node N1. Wherein the input circuit 11 is configured to transmit the scan-in signal to the first node N1 in response to the scan-in signal received at the input signal terminal Iput; and transmitting the black inserted input signal to the first node N1 in response to the black inserted input signal received at the input signal terminal Iput.

For example, in a case where the level of the input signal terminal Iput is a high level, the input circuit 11 may be turned on by the scan input signal or the black insertion input signal and transmit the scan input signal or the black insertion input signal to the first node N1, charging the first node N1, and causing the voltage of the first node N1 to rise.

It should be noted that, in the embodiment of the present disclosure, the scan input signal and the black insertion input signal are respectively transmitted to the input circuit 11 at different times.

In some embodiments, as shown in fig. 7 and 8, the Output circuit 12 is coupled to the first node N1, the first clock signal terminal CLKE, and the first Output signal terminal Output1 (abbreviated as Oput1 in the drawings and below). Wherein the output circuit 12 is configured to transmit the scan clock signal received at the first clock signal terminal CLKE to the first output signal terminal Oput1 in case that the scan input signal is transmitted to the first node, so that the first output signal terminal Oput1 outputs the scan signal; and, in case that the black inserted input signal is transmitted to the first node N1, the black inserted clock signal received at the first clock signal terminal CLKE is transmitted to the first output signal terminal Oput1, so that the first output signal terminal Oput1 outputs the black inserted signal.

For example, in the case where the voltage of the first node N1 is at a high level, the output circuit 12 may be turned on under the control of the voltage of the first node N1 to output the first clock signal received at the first clock signal terminal CLKE as a scan signal from the first output signal terminal Oput 1. And, in case that the voltage of the first node N1 is a high level, the output circuit 12 may be turned on under the control of the voltage of the first node N1 to output the first clock signal received at the first clock signal terminal CLKE as a black inserted signal from the first output signal terminal Oput 1.

It should be noted that, in the embodiment of the present disclosure, the scan signal and the black insertion signal are respectively output from the first output signal terminal Oput1 at different times.

In this case, the plurality of pixel driving circuits in the same row of the sub-pixels P are electrically connected to the same gate line GL. The first output signal terminal Oput1 of one sub-shift register 10 can be electrically connected to the first scan signal terminal G1 and the second scan signal terminal G2 of the plurality of pixel driving circuits in the corresponding row of sub-pixels P through the gate line GL, and the scan signal and the black insertion signal outputted from the first output signal terminal Oput1 can also be transmitted to the first scan signal terminal G1 and the second scan signal terminal G2 of the plurality of pixel driving circuits through the gate line GL.

In some embodiments, referring to FIG. 7, the shift register 1 includes M sub-shift register groups 20, M ≧ 1, and M is an integer. Each sub-shift register group 20 comprises N adjacent sub-shift registers 10, wherein N is more than or equal to 2, and N is an integer. Among them, the N sub-shift registers 10 are configured to receive scan clock signals with the same timing to output scan signals with the same timing (see fig. 18).

In addition, the black insertion signal starts to be output after the pixel driving circuit of the row of sub-pixels P connected to the last sub-shift register 10 in the X sub-shift registers 10 completes writing of the data signal, so as to avoid interference between the black insertion signal and the scan signal.

The beneficial effects of the shift register provided in some embodiments of the present disclosure are the same as the beneficial effects of the driving method of the shift register provided in the above technical solution, and are not described herein again.

As shown in fig. 3, the first scanning signal terminal G1 and the second scanning signal terminal G2 of the plurality of pixel driving circuits in the same row of sub-pixels P are electrically connected to the same gate line GL.

As described above, the pixel drive circuit in the sub-pixel P, as shown in fig. 6, may include, for example, a display period, a black insertion period, and a blanking period, which are sequentially performed. The black insertion period includes a black insertion writing phase P4 and a black insertion maintaining phase P5.

In the display period, the voltage of the first node N1 is first raised by the input circuit 11. In response to the scan input signal received at the input signal terminal Iput, the input circuit 11 is turned on and charges the first node N1, and the output circuit 12 may be turned on under the control of the voltage of the first node N1 to output the first clock signal as the scan signal from the first output signal terminal Oput 1.

In the reset phase P1 and the data write phase P2, the input circuit 11 is turned off, the voltage of the first node N1 is maintained at a high level, the output circuit 12 maintains an on state by the voltage of the first node N1, and the level of the first clock signal output from the first output signal terminal Oput1 is at a high level. In the light emitting period P3, the voltage of the first node N1 is at a low level, the output circuit 12 is turned off, the level of the signal output from the first output signal terminal Oput1 is at a low level, and the driving transistor T2 is turned on under the control of the voltage of the first node G, driving the light emitting device to emit light.

At a certain time during the light emitting process of the light emitting device (i.e., at a time when the light emitting period P3 and the black insertion writing period P4 alternate in fig. 6), after the input circuit 11 is turned on and charges the first node N1 in response to the black insertion input signal received at the input signal terminal Iput, the output circuit 12 may be turned on under the control of the voltage of the first node N1 to output the first clock signal as the black insertion signal from the first output signal terminal Oput 1.

At this time, the black insertion signal is transmitted to the first and second scan signal terminals G1 and G2 of the corresponding pixel driving circuit. The level of the black insertion signal is high, the switching transistor T1 is turned on under the control of the black insertion signal, and a data signal of low level or lower level (which may also be referred to as a black insertion data signal) is transmitted to the second node G; the sensing transistor T3 is turned on under the control of the black insertion signal, and transmits a reset signal of a low level to the third node S. At this time Vgs (i.e., the voltage difference between the second node G and the third node S) is less than Vth (i.e., the threshold voltage of the driving transistor T2), the sub-pixel P stops emitting light and switches to a black picture. In the black insertion holding period t5, the sub-pixel P continues to be displayed as a black screen.

That is, the present disclosure may insert a black frame in the process of emitting light to perform normal image display of the subpixel P, so that the MPRT (Motion Picture Response Time) may be increased without increasing the refresh frequency, thereby improving the phenomenon of Motion Picture smear and improving the image display effect.

In addition, by controlling the writing time of the black insertion signal and the black insertion data signal, the ratio of the time length of the sub-pixel P for normally emitting light to the time length of keeping the sub-pixel P as a black picture can be controlled, so that the MPRT can be conveniently adjusted, the phenomenon of smear of a dynamic image can be improved, and the image display effect can be improved.

In the case where the shift register 1 includes eight sub-shift registers 10, and the eight line scanning periods include one line scanning period group, each line scanning period group includes two line scanning periods, and the timings of the eight black insertion phases P7 of the eight line scanning periods are the same, as shown in fig. 7 and 18, the shift register 1 includes eight sub-shift registers 10, the eight sub-shift registers 10 includes one sub-shift register group 20, each sub-shift register group 20 includes two adjacent sub-shift registers 10, and the timings of the eight black insertion signals output by the eight sub-shift registers 10 are the same.

In the case where the shift register 1 includes eight sub-shift registers 10, and the eight black insertion phases P7 of the eight row scanning periods include two timings, the timings of the black insertion phases P7 of the first four row scanning periods are the same, and the timings of the black insertion phases P7 of the last four row scanning periods are the same, referring to fig. 7 and 22, the shift register 1 includes eight sub-shift registers 10, the eight sub-shift registers 10 include two sub-shift register groups 20, each sub-shift register group 20 includes two adjacent sub-shift registers 10, and the eight black insertion signals output by the eight sub-shift registers 10 include two timings. The time sequences of four black insertion signals output by the eight sub shift registers 10 and the first four sub shift registers 10 are the same; the time sequences of the four black insertion signals output by the last four sub-shift registers 10 are the same, and the time of the black insertion signal output by the first four sub-shift registers 10 is earlier than the time of the black insertion signal output by the last four sub-shift registers 10.

The shift register 1 includes eight sub-shift registers 10, and the eight line scanning periods include four line scanning period groups, each of which includes two line scanning periods; in the case where the eight black insertion phases P7 of the eight row scanning periods include four timings, and the timings of the black insertion phases P7 of each row scanning period group are the same, referring to fig. 7 and 24, the shift register 1 includes eight sub shift registers 10, the eight sub shift registers 10 include four sub shift register groups 20, and the eight black insertion signals output by the eight sub shift registers 10 include four timings. In the eight sub shift registers 10, each sub shift register group 20 includes two black insertion signals output by two adjacent sub shift registers 10, and the time for outputting the black insertion signal by the sub shift register group 20 relatively ahead is earlier than the time for outputting the black insertion signal by the sub shift register group 20 relatively behind.

In some embodiments, as shown in fig. 7 and 8, the output circuit 12 is further coupled to the second clock signal terminal CLKD and the cascade signal terminal CR. Wherein, the output circuit 12 is further configured to transmit the second clock signal received at the second clock signal terminal CLKD to the cascade signal terminal CR in a case where the scan input signal is transmitted to the first node N1, so that the cascade signal terminal CR outputs the scan cascade signal.

For example, in a case where the voltage of the first node N1 is at a high level, the output circuit 12 may be turned on under the control of the voltage of the first node N1 to output the second clock signal received at the second clock signal terminal CLKD as a scanning cascade signal from the cascade signal terminal CR.

In some embodiments, as shown in fig. 8 and 9, the input circuit 11 described above includes a scan input circuit 111 and a black insertion input circuit 112.

Illustratively, as shown in fig. 9 and 10, the scan-in circuit 111 is coupled to a scan-in signal terminal GI and a first node N1. Therein, the scan-in circuit 111 is configured to transmit a scan-in signal to the first node N1 in response to a scan-in signal received at a scan-in signal terminal GI.

For example, in a case where the level of the scan input signal terminal GI is a high level, the scan input circuit 11 may be turned on by the scan input signal and transmit the scan input signal to the first node N1, and charge the first node N1, so that the voltage of the first node N1 is raised.

Illustratively, as shown in fig. 9 and 10, the black insertion input circuit 112 is coupled to the black insertion input signal terminal BI and the first node N1. Wherein the black insertion input circuit 112 is configured to transmit the black insertion input signal to the first node N1 in response to the black insertion input signal received at the black insertion input signal terminal BI.

For example, in a case where the level of the black insertion input signal terminal BI is a high level, the black insertion input circuit 112 may be turned on by the scan input signal and transmit the scan input signal to the first node N1 to charge the first node N1, so that the voltage of the first node N1 is raised.

It should be noted that, in the embodiment of the present disclosure, the scan input circuit 111 and the black insertion input circuit 112 are turned on at different times.

In the shift register 1, in the case where 1 ≦ L, and L is an integer, the scan input signal terminal GI of the preceding L-stage sub-shift register 10 is configured to be coupled to the scan initialization signal line STV2 (see fig. 15); the scan input signal terminal GI of the remaining sub-shift registers 10 is coupled to the cascade signal terminal CR of the previous sub-shift register 10, so that the scan cascade signal output by each sub-shift register 10 can be used as the scan input signal of the next sub-shift register 10, thereby implementing cascade display.

Accordingly, in the shift register 1, in the case where 1 ≦ S and S is an integer, the black insertion input signal terminal BI of the previous S-stage sub-shift register 10 is configured to be coupled to the black insertion initialization signal line STV1 (see fig. 15); the black insertion input signal terminals BI of the remaining sub-shift registers 10 are coupled to the first node N1 of the previous sub-shift register 10, so that the high level received at the first node N1 of each sub-shift register 10 can be used as the black insertion input signal of the next sub-shift register 10.

Note that, the cascade signal output at the cascade signal end CR is used as the black insertion input signal of a certain sub shift register 10; alternatively, the high level received at the first node N1 may be used as the black insertion input signal of a subsequent sub shift register 10, and the disclosure is not limited in this respect.

In some embodiments, one shift register 1 includes a plurality of sub shift registers 10, and each sub shift register 10 includes one black insertion input circuit 112.

In other embodiments, as shown in fig. 11 and 12, among a plurality of sub shift registers 10 included in one shift register 1, the sub shift registers 10 having the same black insertion timing may share one black insertion input circuit 112. Illustratively, one sub shift register group 20 includes two sub shift registers 10, and the two sub shift registers 10 may share one black insertion input circuit 112.

Here, by sharing one black insertion input circuit 112 with the sub shift registers 10 included in the sub shift register group 20, the number of black insertion input circuits 112 can be reduced, the structure of the shift register 1 can be simplified, and the yield of the shift register 1 can be improved.

Moreover, with the above arrangement, a small number of black insertion input circuits 112 can be used to control the plurality of sub shift registers 10 that perform black insertion at the same timing, which is beneficial to reducing the difficulty of controlling the plurality of sub shift registers 10 to perform black insertion signal output at the same time.

In some embodiments, as shown in fig. 10, the black insertion input circuit 112 includes a black insertion control sub-circuit 113, a black insertion input sub-circuit 114, and a black insertion transmission sub-circuit 115.

Illustratively, as shown in fig. 10, the black insertion control sub-circuit 113 is electrically connected to the third clock signal terminal BCK1, the black insertion input signal terminal BI, the first voltage signal terminal VGL1, and the first black insertion node M. Wherein the black insertion control sub-circuit 113 is configured to transmit the black insertion input signal received at the black insertion input signal terminal BI to the first black insertion node M under the control of the third clock signal.

Here, the first voltage signal terminal VGL1 may be configured to transmit a dc low level signal (e.g., lower than or equal to a low level portion of the clock signal). Illustratively, the first voltage signal terminal VGL1 is connected to ground.

For example, in the case where the level of the third clock signal is high, the black insertion control sub-circuit 113 is turned on under the control of the third clock signal, transmits the black insertion input signal received at the black insertion input signal terminal BI to the first black insertion node M, and charges the first black insertion node M such that the voltage of the first black insertion node M is increased.

Illustratively, as shown in fig. 10, the black insertion input sub-circuit 114 is electrically connected to the first black insertion node M, the fourth clock signal terminal BCK2 and the second black insertion node K. Wherein the black insertion input sub-circuit 114 is configured to transmit the fourth clock signal received at the fourth clock signal terminal BCK2 to the second black insertion node K under the control of the voltage of the first black insertion node M.

For example, in a case where the black insertion input sub-circuit 114 is turned on and charges the first black insertion node M such that the voltage of the first black insertion node M is increased, the black insertion input sub-circuit 114 may be turned on under the control of the voltage of the first black insertion node M, and receive and transmit the fourth clock signal to the second black insertion node K.

Illustratively, as shown in fig. 10, the black insertion transmission sub-circuit 115 is electrically connected to the fourth clock signal terminal BCK2, the second black insertion node K, and the first node N1. Wherein the black insertion transmission sub-circuit 115 is configured to transmit the fourth clock signal from the second black insertion node K to the first node N1 under the control of the fourth clock signal.

For example, in a case where the level of the fourth clock signal is a high level, the black insertion transmission sub-circuit 115 may be turned on under the control of the fourth clock signal to transmit the fourth clock signal from the second black insertion node K to the first node N1. Since the level of the fourth clock signal from the second black inserted node K is also high, the first node N1 may be charged such that the voltage of the first node N1 is increased.

In consideration of the structure of the black insertion input circuit 112, the arrangement of the black insertion input circuit 112 shared by the same shift register group 10 includes a plurality of ways, and the arrangement can be specifically selected according to actual needs.

Here, the example is schematically illustrated in which a plurality of sub shift registers 10 included in the same sub shift register group 20 share one black insertion input circuit 112.

In some embodiments, black insertion input circuit 112 includes a black insertion transmission subcircuit 115. The black insertion transmission sub-circuit 115 is electrically connected to the first nodes N1 of the sub shift registers 10 included in the same sub shift register group 20.

In other embodiments, as shown in fig. 10 and 12, the black insertion input circuit 112 includes a plurality of black insertion transmission sub-circuits 115, the number of black insertion transmission sub-circuits 115 is the same as the number of sub-shift registers 10 included in the sub-shift register group 20, and one black insertion transmission sub-circuit 115 is electrically connected to the first node N1 of one sub-shift register 10 of the sub-shift register group 20.

Here, the configurations of the scan input circuit 111, the black insertion input circuit 112, and the output circuit 12 include a plurality of types, and can be selectively provided according to actual needs. The following schematically illustrates the structures of the scan input circuit 111, the black insertion input circuit 112, and the output circuit 12.

In some embodiments, as shown in fig. 10, the input circuit 111 includes a first transistor M1.

Illustratively, as shown in fig. 10, the control electrode of the first transistor M1 is electrically connected to the scan input signal terminal GI, the first electrode of the first transistor M1 is electrically connected to the scan input signal terminal GI, and the second electrode of the first transistor M1 is electrically connected to the first node N1.

For example, in the case where the level of the scan input signal is a high level, the first transistor M1 may be turned on under the control of the scan input signal, receive the scan input signal, and transmit the scan input signal to the first node N1, so that the voltage of the first node N1 is raised.

In some embodiments, as shown in fig. 10, the black insertion control sub-circuit 113 includes a second transistor M2 and a first capacitor C1.

Illustratively, as shown in fig. 10, a control electrode of the second transistor M2 is electrically connected to the third clock signal terminal BCK1, a first electrode of the second transistor M2 is electrically connected to the black insertion input signal terminal BI, and a second electrode of the second transistor M2 is electrically connected to the first black insertion node M.

For example, in a case where the level of the first clock signal is a high level, the second transistor M2 may be turned on under the control of the third clock signal, transmit the black insertion input signal received at the black insertion input signal terminal BI to the first black insertion node M, and charge the first black insertion node M such that the voltage of the first black insertion node M is raised.

Illustratively, as shown in fig. 10, a first terminal of the first capacitor C1 is electrically connected to the first black inserted node M, and a second terminal of the first capacitor C1 is electrically connected to the first voltage signal terminal VGL 1.

For example, the first capacitor C1 is also charged while the second transistor M2 is turned on and the first black insertion node M is charged. After the second transistor M2 is turned off, the first capacitor C1 may be discharged such that the voltage of the first black inserted node M is maintained at a high voltage.

In some embodiments, as shown in fig. 10, the black insertion input sub-circuit 114 includes a third transistor M3.

Illustratively, as shown in fig. 10, a control electrode of the third transistor M3 is electrically connected to the first black insertion node M, a first electrode of the third transistor M3 is electrically connected to the fourth clock signal terminal BCK2, and a second electrode of the third transistor M3 is electrically connected to the second black insertion node K.

For example, in a case where the second transistor M2 is turned on and charges the first black inserted node M such that the voltage of the first black inserted node M is increased, the third transistor M3 may be turned on under the control of the voltage of the first black inserted node M, and receive and transmit the fourth clock signal to the second black inserted node K.

In some embodiments, as shown in fig. 10, the black insertion transmission sub-circuit 115 includes a fourth transistor M4.

Illustratively, as shown in fig. 10, a control electrode of the fourth transistor M4 is electrically connected to the fourth clock signal terminal BCK2, a first electrode of the fourth transistor M4 is electrically connected to the second black insertion node K, and a second electrode of the fourth transistor M4 is electrically connected to the first node N1.

For example, in a case where the level of the second clock signal is a high level, the fourth transistor M4 may be turned on under the control of the fourth clock signal, transmit the fourth clock signal from the second black inserted node K to the first node N1, and charge the first node N1 such that the voltage of the first node N1 is raised.

In some embodiments, as shown in fig. 10, the output circuit 12 includes a fifth transistor M5, a sixth transistor M6, and a second capacitor C2.

Illustratively, as shown in fig. 10, a control electrode of the fifth transistor M5 is electrically connected to the first node N1, a first electrode of the fifth transistor M5 is electrically connected to the second clock signal terminal CLKD, and a second electrode of the fifth transistor M5 is electrically connected to the cascade signal terminal CR.

For example, in a case where the voltage of the first node N1 is a high potential, the fifth transistor M5 may be turned on under the control of the first node N1, and the second clock signal received from the second clock signal terminal CLKD may be output from the cascade signal terminal CR as the scanning cascade signal.

Illustratively, as shown in fig. 10, a control electrode of the sixth transistor M6 is electrically connected to the first node N1, a first electrode of the sixth transistor M6 is electrically connected to the first clock signal terminal CLKE, and a second electrode of the sixth transistor M6 is electrically connected to the first output signal terminal Oput 1.

For example, in the case where the voltage of the first node N1 is a high potential, the sixth transistor M6 may be turned on under the control of the first node N1, outputting the first clock signal received from the first clock signal terminal CLKE as a scan signal or a black insertion signal from the first output signal terminal Oput 1. In different time periods, the signals output by the first output signal terminal Oput1 have different functions, and reference may be made to the description in some embodiments above, and details are not described here again.

Illustratively, as shown in fig. 10, a first terminal of the second capacitor C2 is electrically connected to the first node N1, and a second terminal of the second capacitor C2 is electrically connected to the first output signal terminal Oput 1.

For example, during the process that the first transistor M1 is turned on and charges the first node N1, the second capacitor C2 is also charged. After the first transistor M1 is turned off, the second capacitor C2 may be discharged such that the voltage of the first node N1 is maintained at a high voltage.

For another example, during the black insertion input circuit 112 is turned on and the first node N1 is charged, the second capacitor C2 is also charged. After the black insertion input circuit 112 is turned off, the second capacitor C2 may be discharged such that the voltage of the first node N1 remains at a high voltage.

In some embodiments, in the case where each sub-shift register 10 in the scan driving circuit 100 may be electrically connected to the first scan signal terminal G1 through a first gate line and to the second scan signal terminal G2 through a second gate line, as shown in fig. 13, the output circuit 12 may be further electrically connected to the fifth clock signal terminal CLKF and the second output signal terminal Oput2, the first signal output terminal Oput1 may be electrically connected to the first scan signal terminal G1 through a first gate line, and the second output signal terminal Oput2 may be electrically connected to the second scan signal terminal G2 through a second gate line.

In the case where the output circuit 12 is also electrically connected to the fifth clock signal terminal CLKF and the second output signal terminal Oput2, the output circuit 12 further includes a seventh transistor M7 and a third capacitor C3.

Illustratively, as shown in fig. 13, a control electrode of the seventh transistor M7 is electrically connected to the first node N1, a first electrode of the seventh transistor M7 is electrically connected to the fifth clock signal terminal CLKF, and a second electrode of the seventh transistor M7 is electrically connected to the second output signal terminal Oput 2.

For example, in case that the voltage of the first node N1 is a high potential, the seventh transistor M7 may be turned on under the control of the first node N1, outputting the fifth clock signal received from the fifth clock signal terminal CLKF from the second output signal terminal Oput 2.

Illustratively, as shown in fig. 13, a first terminal of the third capacitor C3 is electrically connected to the first node N1, and a second terminal of the third capacitor C3 is electrically connected to the second output signal terminal Oput 2.

For example, during the process that the first transistor M1 is turned on and charges the first node N1, the third capacitor C3 is also charged. After the first transistor M1 is turned off, the third capacitor C3 may be discharged such that the voltage of the first node N1 is maintained at a high voltage.

For another example, the third capacitor C3 is also charged while the black insertion input circuit 112 is turned on and the first node N1 is charged. After the black insertion input circuit 112 is turned off, the third capacitor C3 may be discharged such that the voltage of the first node N1 remains at a high voltage.

In some embodiments, the sub-shift register 10 may further include other circuit structures, and the arrangement may be selected according to actual needs.

In some embodiments, as shown in fig. 13, the sub shift register 10 may further include: a control circuit 13 and a second voltage signal terminal VDD.

Illustratively, as shown in fig. 13, the control circuit 13 is electrically connected to the second voltage signal terminal VDD, the first node N1, the first voltage signal terminal VGL1 and the fourth node N4. Wherein the control circuit 13 is configured to transmit the second voltage signal to the fourth node N4 in response to the second voltage signal received at the second voltage signal terminal VDD, and to transmit the first voltage signal received at the first voltage signal terminal VGL1 to the fourth node N4 under the control of the voltage of the first node N1.

Here, the second voltage signal terminal VDD may be configured to transmit a direct current high level signal (e.g., higher than or equal to a high level portion of the clock signal). References herein to "high" and "low" are relative terms. Illustratively, the voltage value of the second voltage signal is greater than the voltage value of the first voltage signal.

For example, the control circuit 13 may receive and transmit the second voltage signal to the fourth node N4 under the control of the second voltage signal. In a case where the voltage of the first node N1 is at a high level, the control circuit 13 may receive and transmit the first voltage signal to the fourth node N4 under the control of the voltage of the first node N1, and perform a pull-down reset on the fourth node N4.

In some embodiments, as shown in fig. 13, the sub shift register 10 may further include a first reset circuit 14 and a first reset signal terminal STD.

Illustratively, as shown in fig. 13, the first reset circuit 14 is electrically connected to the first reset signal terminal STD, the first node N1, and the first voltage signal terminal VGL 1. Wherein the first reset circuit 14 is configured to transmit the first voltage signal to the first node N1 under the control of the first reset signal transmitted by the first reset signal terminal STD.

For example, in a case where the level of the first reset signal is a high level, the first reset circuit 14 may be turned on under the control of the first reset signal, transmit the first voltage signal received at the first voltage signal terminal VGL1 to the first node N1, and pull-down reset the first node N1.

It should be noted that, except for the last sub-shift registers 10 (for example, the last sub-shift register 10 or the last four sub-shift registers 10, etc.), the first reset signal terminal STD of each sub-shift register 10 may be electrically connected to the cascade signal terminal CR of a next sub-shift register 10, and then the scanning cascade signal output by the cascade signal terminal CR of the next sub-shift register 10 is used as the first reset signal of the sub-shift register 10 to implement cascade reset.

Accordingly, the first reset signal terminals STD of the last several sub-shift registers 10 (e.g., the last sub-shift register 10 or the last four sub-shift registers 10, etc.) may be electrically connected to the display reset signal line so as to receive the display reset signal transmitted by the display reset signal line as the first reset signal.

In some embodiments, as shown in fig. 13, the sub shift register 10 may further include a second reset circuit 15 and a second reset signal terminal BTRST.

Illustratively, as shown in fig. 13, the second reset circuit 15 is electrically connected to the first black inserted node M, the second reset signal terminal BTRST, the first node N1 and the first voltage signal terminal VGL 1. The second reset circuit 15 is configured to transmit the first voltage signal to the first node N1 under the control of the voltage of the first black insertion node M and the second reset signal transmitted by the second reset signal terminal BTRST.

For example, when the voltage of the first black inserted node M is at a high level and the level of the second reset signal is at a high level, the second reset circuit 15 may be turned on under the control of the voltage of the first black inserted node M and the second reset signal, transmit the first voltage signal received at the first voltage signal terminal VGL1 to the first node N1, and perform pull-down reset on the first node N1.

Here, the second reset circuit 15 may reset the first node N1 after black insertion, for example.

In some embodiments, as shown in fig. 13, the sub shift register 10 may further include a third reset circuit 16.

For example, as shown in fig. 13, the third reset circuit 16 is electrically connected to the fourth node N4, the first node N1 and the first voltage signal terminal VGL 1. Wherein the third reset circuit 16 is configured to transmit the first voltage signal to the first node N1 under the control of the voltage of the fourth node N4.

For example, in a case where the voltage of the fourth node N4 is at a high level, the third reset circuit 16 may be turned on under the control of the voltage of the fourth node N4, transmit the first voltage signal received at the first voltage signal terminal VGL1 to the first node N1, and pull-down reset the first node N1.

In some embodiments, as shown in fig. 13, the sub shift register 10 may further include a fourth reset circuit 17 and a third voltage signal terminal VGL 2.

Illustratively, as shown in fig. 13, the fourth reset circuit 17 is electrically connected to the first node N1, the cascade signal terminal CR, the first output signal terminal Oput1, the first voltage signal terminal VGL1, and the third voltage signal terminal VGL 2. Wherein the fourth reset circuit 17 is configured to transmit the first voltage signal to the cascade signal terminal CR and transmit the third voltage signal to the first output signal terminal Oput1 under the control of the first node N1.

For example, in the case where the voltage of the first node N1 is at a high level, the fourth reset circuit 17 may be turned on under the control of the voltage of the first node N1, transfer the first voltage signal received at the first voltage signal terminal VGL1 to the cascade signal terminal CR, pull-down reset the cascade signal terminal CR, and transfer the third voltage signal received at the third voltage signal terminal VGL2 to the first output signal terminal Oput1, pull-down reset the first output signal terminal Oput 1.

Here, the third voltage signal terminal VGL2 may be configured to transmit a dc low level signal (e.g., lower than or equal to a low level portion of the clock signal). Illustratively, the third voltage signal terminal VGL2 is connected to ground. And the voltage value of the second voltage signal is greater than that of the third voltage signal. The voltage value of the first voltage signal and the voltage value of the third voltage signal may be equal or unequal.

Exemplarily, as shown in fig. 13, in the case where the output circuit 12 is also electrically connected to the fifth clock signal terminal CLKF and the second output signal terminal Oput2, the fourth reset circuit 17 is also electrically connected to the second output signal terminal Oput 2. Wherein the fourth reset circuit 17 is further configured to transmit the third voltage signal to the second output signal terminal Oput2 under the control of the first node N1.

For example, in the case where the voltage of the first node N1 is at a high level, the fourth reset circuit 17 may be turned on under the control of the voltage of the first node N1, transfer the third voltage signal received at the third voltage signal terminal VGL2 to the second output signal terminal Oput2, and pull-down reset the second output signal terminal Oput 2.

The control circuit 13, the first reset circuit 14, the second reset circuit 15, the third reset circuit 16, and the fourth reset circuit 17 have various configurations, and may be selectively provided according to actual needs. The following schematically describes the configurations of the control circuit 13, the first reset circuit 14, the second reset circuit 15, the third reset circuit 16, and the fourth reset circuit 17.

In some embodiments, as shown in fig. 13, the control circuit 13 includes an eighth transistor M8 and a ninth transistor M9.

Illustratively, as shown in fig. 13, a control electrode of the eighth transistor M8 is electrically connected to the second voltage signal terminal VDD, a first electrode of the eighth transistor M8 is electrically connected to the second voltage signal terminal VDD, and a second electrode of the eighth transistor M8 is electrically connected to the fourth node N4 and the first electrode of the ninth transistor M9.

For example, the eighth transistor M8 may be turned on under the control of the second voltage signal, receive and transmit the second voltage signal to the fourth node N4, and charge the fourth node N4, so that the voltage of the fourth node N4 is raised.

Illustratively, as shown in fig. 13, a control electrode of the ninth transistor M9 is electrically connected to the first node N1, and a second electrode of the ninth transistor M9 is electrically connected to the first voltage signal terminal VGL 1.

For example, in a case where the voltage of the first node N1 is at a high level, the ninth transistor M9 may be turned on under the control of the first node N1, receive and transmit the first voltage signal to the fourth node N4, and perform a pull-down reset on the fourth node N4.

In some embodiments, as shown in fig. 13, the first reset circuit 14 includes a tenth transistor M10.

Illustratively, as shown in fig. 13, a control electrode of the tenth transistor M10 is electrically connected to the first reset signal terminal STD, a first electrode of the tenth transistor M10 is electrically connected to the first node N1, and a second electrode of the tenth transistor M10 is electrically connected to the first voltage signal terminal VGL 1.

For example, in a case where the level of the first reset signal is a high level, the tenth transistor M10 may be turned on under the control of the first reset signal, receive and transmit the first voltage signal to the first node N1, and perform a pull-down reset on the first node N1.

In some embodiments, as shown in fig. 13, the second reset circuit 15 includes an eleventh transistor M11 and a twelfth transistor M12.

Illustratively, as shown in fig. 13, a control electrode of the eleventh transistor M11 is electrically connected to the first black insertion node M, a first electrode of the eleventh transistor M11 is electrically connected to the first node N1, and a second electrode of the eleventh transistor M11 is electrically connected to the first electrode of the twelfth transistor M12. A control electrode of the twelfth transistor M12 is electrically connected to the second reset signal terminal BTRST, and a second electrode of the twelfth transistor M12 is electrically connected to the first voltage signal terminal VGL 1.

For example, in a case where the voltage of the first black inserted node M is at a high level and the level of the second reset signal is at a high level, the eleventh transistor M11 may be turned on under the control of the voltage of the first black inserted node M, the twelfth transistor M12 may be turned on under the control of the second reset signal, the twelfth transistor M12 may receive and transmit the first voltage signal to the second pole of the eleventh transistor M11, and then the eleventh transistor M11 may transmit the first voltage signal to the first node N1, performing a pull-down reset on the first node N1.

In some embodiments, as shown in fig. 13, the third reset circuit 16 includes a thirteenth transistor M13.

Illustratively, as shown in fig. 13, a control electrode of the thirteenth transistor M13 is electrically connected to the fourth node N4, a first electrode of the thirteenth transistor M13 is electrically connected to the first node N1, and a second electrode of the thirteenth transistor M13 is electrically connected to the first voltage signal terminal VGL 1.

For example, in a case where the voltage of the fourth node N4 is at a high level, the thirteenth transistor M13 may be turned on under the control of the voltage of the fourth node N4, receive and transmit the first voltage signal to the first node N1, and perform a pull-down reset on the first node N1.

In some embodiments, as shown in fig. 13, the fourth reset circuit 17 includes: a fourteenth transistor M14, a fifteenth transistor M15, and a sixteenth transistor M16.

Illustratively, as shown in fig. 13, a control electrode of the fourteenth transistor M14 is electrically connected to the fourth node N4, a first electrode of the fourteenth transistor M14 is electrically connected to the cascade signal terminal CR, and a second electrode of the fourteenth transistor M14 is electrically connected to the first voltage signal terminal VGL 1.

For example, in a case where the voltage of the fourth node N4 is at a high level, the fourteenth transistor M14 may be turned on under the control of the voltage of the fourth node N4, receive and transmit the first voltage signal to the cascade signal terminal CR, and perform a pull-down reset on the cascade signal terminal CR.

Illustratively, as shown in fig. 13, a control electrode of the fifteenth transistor M15 is electrically connected to the fourth node N4, a first electrode of the fifteenth transistor M15 is electrically connected to the first output signal terminal Oput1, and a second electrode of the fifteenth transistor M15 is electrically connected to the third voltage signal terminal VGL 2.

For example, in a case where the voltage of the fourth node N4 is at a high level, the fifteenth transistor M15 may be turned on under the control of the voltage of the fourth node N4, receive and transmit the third voltage signal to the first output signal terminal Oput1, and perform a pull-down reset on the first output signal terminal Oput 1.

Illustratively, as shown in fig. 13, a control electrode of the sixteenth transistor M16 is electrically connected to the fourth node N4, a first electrode of the sixteenth transistor M16 is electrically connected to the second output signal terminal Oput2, and a second electrode of the sixteenth transistor M16 is electrically connected to the third voltage signal terminal VGL 2.

For example, in case that the voltage of the fourth node N4 is at a high level, the sixteenth transistor M16 may be turned on under the control of the voltage of the fourth node N4, receive and transmit the third voltage signal to the second output signal terminal Oput2, and pull-down reset the second output signal terminal Oput 2.

From the foregoing, one frame period may include, for example, a display period, a black insertion period, and a blanking period, which are sequentially performed. Based on this, in some embodiments, as shown in fig. 13, sub-shift register 10 may further include blanking circuit 18.

In some embodiments, as shown in fig. 13, the blanking circuit 18 is electrically connected to the sixth clock signal terminal CLKA, the selection control signal terminal OE, the scan input signal terminal GI, the first node N1 and the first voltage signal terminal VGL 1. Therein, the blanking circuit 18 is configured to transmit the sixth clock signal to the first node N1 under control of the selection control signal at the selection control signal terminal OE, the scan-in signal and the sixth clock signal at the sixth clock signal terminal CLKA.

In some embodiments, one shift register 1 comprises a plurality of sub-shift registers 10, each sub-shift register 10 comprising one blanking circuit 18.

In other embodiments, the sub-shift registers 10 with the same blanking timing in the plurality of sub-shift registers 10 included in one shift register 1 may share one blanking circuit 18. Illustratively, one sub-shift register group 20 includes two sub-shift registers 10, and the two sub-shift registers 10 may share one blanking circuit 18.

Here, by sharing one blanking circuit 18 with the sub shift registers 10 included in the sub shift register group 20, the number of blanking circuits 18 can be reduced, the structure of the shift register 1 can be simplified, and the yield of the shift register 1 can be improved.

Moreover, with the above arrangement, a small number of blanking circuits 18 can be used to control the plurality of sub-shift registers 10 that blank the same timing sequence, which is beneficial to reducing the difficulty of controlling the plurality of sub-shift registers 10 to blank simultaneously.

In some embodiments, as shown in fig. 13, the blanking circuit 18 includes a select control sub-circuit 181, a blank input sub-circuit 182, and a blank transmission sub-circuit 183.

The selection control sub-circuit 181 is electrically connected to the scan input signal terminal GI, the first blanking node H, the selection control signal terminal OE, the scan input signal terminal GI, the first blanking node H, and the first voltage signal terminal VGL 1. Wherein the selection control sub-circuit 181 is configured to transmit the scan input signal to the first blanking node H under the control of the selection control signal.

For example, in a case where the level of the selection control signal is a high level, the selection control sub-circuit 181 may be turned on under the control of the selection control signal and transmit the received scan input signal to the first blanking node H, charging the first blanking node H, so that the voltage of the first blanking node H is raised.

For example, when the sub shift register 10 needs to output the sensing signal, the waveform timing of the selection control signal and the waveform timing of the scan input signal may be made the same, and the selection control sub circuit 181 may be turned on.

In some embodiments, as shown in fig. 13, the blanking input sub-circuit 182 is electrically connected to the first blanking node H, the sixth clock signal terminal CLKA, and the second blanking node Q. Wherein the blanking input sub-circuit 182 is configured to transmit the sixth clock signal to the second blanking node Q under control of the voltage of the first blanking node H.

For example, in case the selection control sub-circuit 181 is turned on such that the voltage of the first blanking node H is raised, the blanking input sub-circuit 182 may be turned on under the control of the voltage of the first blanking node H, receive the sixth clock signal transmitted by the sixth clock signal terminal CLKA, and transmit the sixth clock signal to the second blanking node Q.

In some embodiments, as shown in fig. 13, the blanking transmission sub-circuit 183 is electrically connected to the sixth clock signal terminal CLKA, the second blanking node Q, and the first node N1. Wherein the blanking transmission sub-circuit 183 is configured to transmit the sixth clock signal from the second blanking node Q to the first node N1 under control of the sixth clock signal.

For example, in a case where the level of the sixth clock signal is a high level, the blanking transmission sub-circuit 183 may be turned on under the control of the sixth clock signal, and receive the sixth clock signal from the second blanking node Q, transmit the received sixth clock signal to the first node N1, charge the first node N1, so that the voltage of the first node N1 is raised.

The following description will be made schematically with reference to the drawings, regarding the structure of the selection control sub-circuit 181, the blanking input sub-circuit 182, and the blanking transmission sub-circuit 183 included in the blanking circuit 18.

In some embodiments, as shown in fig. 13, the selection control sub-circuit 181 includes a seventeenth transistor M17 and a fourth capacitor C4.

Illustratively, as shown in fig. 13, a control electrode of the seventeenth transistor M17 is electrically connected to the selection control signal terminal OE, a first electrode of the seventeenth transistor M17 is electrically connected to the scan input signal terminal GI, and a second electrode of the seventeenth transistor M17 is electrically connected to the first blanking node H.

For example, in a case where the level of the selection control signal transmitted by the selection control signal terminal OE is a high level, the seventeenth transistor M17 may be turned on by the selection control signal, receive and transmit the scan input signal to the first blanking node H, and charge the first blanking node H such that the voltage of the first blanking node H is increased.

Illustratively, as shown in fig. 13, a first terminal of the fourth capacitor C4 is electrically connected to the first blanking node H, and a second terminal of the fourth capacitor C4 is electrically connected to the first voltage signal terminal VGL 1.

For example, during the seventeenth transistor M17 is turned on and charges the first blanking node H, the fourth capacitor C4 is also charged. This makes it possible to discharge with the fourth capacitor C4 with the seventeenth transistor M17 turned off, so that the first blanking node H maintains a high level.

In some embodiments, as shown in fig. 13, the blanking input sub-circuit 182 includes an eighteenth transistor M18.

Illustratively, as shown in fig. 13, a control electrode of the eighteenth transistor M18 is electrically connected to the first blanking node H, a first electrode of the eighteenth transistor M18 is electrically connected to the sixth clock signal terminal CLKA, and a second electrode of the eighteenth transistor M18 is electrically connected to the second blanking node Q.

For example, in case that the voltage of the first blanking node H is a high level, the eighteenth transistor M18 may be turned on under the control of the voltage of the first blanking node H, transmitting the sixth clock signal received at the sixth clock signal terminal CLKA to the second blanking node Q.

In some embodiments, as shown in fig. 13, the blanking transmission sub-circuit 183 includes a nineteenth transistor M19.

Illustratively, as shown in fig. 13, a control electrode of the nineteenth transistor M19 is electrically connected to the sixth clock signal terminal CLKA, a first electrode of the nineteenth transistor M19 is electrically connected to the second blanking node Q, and a second electrode of the nineteenth transistor M19 is electrically connected to the first node N1.

For example, in a case where the level of the sixth clock signal transmitted by the sixth clock signal terminal CLKA is at a high level, the nineteenth transistor M19 may be turned on by the sixth clock signal, receive and transmit the sixth clock signal from the second blanking node Q to the first node N1, and charge the first node N1.

As shown in fig. 14 and fig. 15, some embodiments of the present disclosure further provide a scan driving circuit 100, where the scan driving circuit 100 includes a plurality of cascaded shift registers 1 according to any of the above embodiments.

Wherein, each shift register 1 comprises X sub-shift registers 10, X is more than or equal to 2, and X is an integer. The scan driving circuit 100 further includes a plurality of first clock signal line groups 30, each of the first clock signal line groups 30 including at least X-M X (N-1) first clock signal lines 31. The plurality of first clock signal terminals CLKE of each shift register 1 are coupled to the plurality of first clock signal lines 31 of one first clock signal line group 30, respectively.

For example, in the case where the shift register 1 includes eight sub shift registers 10, the eight sub shift registers 10 include one sub shift register group 20, each sub shift register group 20 includes two adjacent sub shift registers 10, and the timings of the eight black insertion signals output by the eight sub shift registers 10 are the same, each first clock signal line group 30 may include 7 first clock signal lines 31(CLK5 to CLK11 or CLK12 to CLK18), and the timing diagrams refer to fig. 19 and 21.

Illustratively, in the case where the shift register 1 includes eight sub shift registers 10, the eight sub shift registers 10 include two sub shift register groups 20, each sub shift register group 20 includes two adjacent sub shift registers 10, and the eight black insertion signals output by the eight sub shift registers 10 include two timings, each first clock signal line group 30 may include 6 first clock signal lines 31(CLK5 to CLK10 or CLK11 to CLK16), and the timing diagram is shown in fig. 23.

For example, in the case where the shift register 1 includes eight sub shift registers 10, the eight sub shift registers 10 include four sub shift register groups 20, and the eight black insertion signals output by the eight sub shift registers 10 include four timings, each first clock signal line group 30 may include 4 first clock signal lines 31(CLK5 to CLK8 or CLK9 to CLK12), and the timing diagram is shown in fig. 25.

Here, in the shift register 1, the first clock signal terminal CLKE of the N sub-shift registers 10 of each sub-shift register group 20 is coupled to the same first clock signal line 31, and different sub-shift register groups 20 are coupled to different first clock signal lines 31. It should be noted that, in the shift register 1, the first clock signal terminal CLKE of each of the other sub-shift registers 10 except the M sub-shift register groups 20 is coupled to a different first clock signal line 31, respectively.

In this case, the sub-shift registers 10 included in each sub-shift register group 20 share one clock signal line, so that the number of clock signal lines can be reduced, the structure of the scan driving circuit 100 can be simplified, and the yield of the scan driving circuit 100 and the display panel 1000 and the display device 2000 applied thereto can be improved.

The scanning drive circuit 100 will be schematically described below by taking the configuration diagrams of the scanning drive circuit 100 shown in fig. 14 and 15 as examples.

Illustratively, A <1-8>, A <9-16>, A <17-24>, A <25-32> … … A < 2145-. A1, a2, A3 … … a15, a16 shown in fig. 15 respectively represent 16 sub shift registers 10 in the first shift register 1 and the second shift register 1.

For example, as shown in fig. 14, each shift register 1 includes one sub shift register group 20, and each sub shift register group 20 includes two sub shift registers 10.

Illustratively, as shown in fig. 15, the scan driving circuit 100 includes a plurality of clock signal lines, which may include a first control clock signal line CLK1, a second control clock signal line CLK2, a third control clock signal line CLK3, and a fourth control clock signal line CLK 4.

For example, in the 2Y-1 th shift register 1, the third clock signal terminal BCK1 of each sub-shift register 10 is electrically connected to the first control clock signal line CLK 1. In the 2M-1 th shift register 1, the fourth clock signal terminal BCK2 of each sub-shift register 10 is electrically connected to the second control clock signal line CLK 2. Wherein Y is a positive integer.

In the 2Y-th shift register 1, the third clock signal terminal BCK1 of each sub-shift register 10 is electrically connected to the third control clock signal line CLK 3. In the 2M-th shift register 1, the fourth clock signal terminal BCK2 of each sub-shift register 1 is electrically connected to the fourth control clock signal line CLK 4.

Illustratively, as shown in fig. 15, the plurality of clock signal lines included in the scan driving circuit 100 further includes two first clock signal line groups 30, and the two first clock signal line groups 30 include a fifth clock signal line CLK5, a sixth clock signal line CLK6, a seventh clock signal line CLK7, an eighth clock signal line CLK8, a ninth clock signal line CLK9, a tenth clock signal line CLK10, an eleventh clock signal line CLK11, a twelfth clock signal line CLK12, a thirteenth clock signal line CLK13, a fourteenth clock signal line CLK14, a fifteenth clock signal line CLK15, a sixteenth clock signal line CLK16, a seventeenth clock signal line CLK17, and an eighteenth clock signal line CLK 18.

For example, in the 2Y-1 th shift register 1, the second clock signal terminal CLKD and the first clock signal terminal CLKE of the first sub-shift register 10 and the second sub-shift register 10 are electrically connected to the fifth clock signal line CLK5, the second clock signal terminal CLKD and the first clock signal terminal CLKE of the third sub-shift register 10 are electrically connected to the sixth clock signal line CLK6, the second clock signal terminal CLKD and the first clock signal terminal CLKE of the fourth sub-shift register 10 are electrically connected to the seventh clock signal line CLK7, the second clock signal terminal CLKD and the first clock signal terminal CLKE of the fifth shift register 10 are electrically connected to the eighth clock signal line CLK8, the second clock signal terminal CLKD and the first clock signal terminal CLKE of the sixth sub-shift register 10 are electrically connected to the ninth clock signal line CLK9, the second clock signal terminal CLKD and the first clock signal terminal CLKE of the seventh sub-shift register 10 are electrically connected to the tenth clock signal line 10, the second clock signal terminal CLKD and the first clock signal terminal CLKE of the eighth sub-shift register 10 are electrically connected to the eleventh clock signal line CLK 11.

In the 2Y shift register 1, the second clock signal terminal CLKD and the first clock signal terminal CLKE of the first sub-shift register 10 and the second sub-shift register 10 are electrically connected to the twelfth clock signal line CLK12, the second clock signal terminal CLKD and the first clock signal terminal CLKE of the third sub-shift register 10 are electrically connected to the thirteenth clock signal line CLK13, the second clock signal terminal CLKD and the first clock signal terminal CLKE of the fourth sub-shift register 10 are electrically connected to the fourteenth clock signal line CLK14, the second clock signal terminal CLKD and the first clock signal terminal CLKE of the fifth shift register 10 are electrically connected to the fifteenth clock signal line CLK15, the second clock signal terminal CLKD and the first clock signal terminal CLKE of the sixth sub-shift register 10 are electrically connected to the sixteenth clock signal line CLK16, the second clock signal terminal CLKD and the first clock signal terminal CLKE of the seventh sub-shift register 10 are electrically connected to the seventeenth clock signal line CLK17, the second clock signal terminal CLKD and the first clock signal terminal CLKE of the eighth sub-shift register 10 are electrically connected to the eighteenth clock signal line CLK 18.

It should be noted that the cascade relationship shown in fig. 15 is only an example, and the present disclosure may also adopt other cascade manners according to practical situations.

In the scan driving circuit 100, in addition to the first L stages of sub-shift registers 10, the scan input signal terminal GI of each sub-shift register 10 may be coupled to the cascade signal terminal CR of the previous sub-shift register 10 to implement cascade display. Wherein L is not less than 1 and is an integer. It should be noted that the scan input signal terminal GI of the first L-stage sub-shift register 10 may be coupled to the scan initialization signal line STV 2.

Illustratively, in the scan driving circuit 100, the scan input signal terminals GI of the first four sub-shift registers 10 are coupled to the scan initialization signal line STV2, and the scan input signal terminals GI of the remaining sub-shift registers 10 are respectively coupled to the cascade signal terminals CR of the fourth sub-shift register 10 to implement cascade display.

In the scan driving circuit 100, in addition to the first S-stage sub shift register 10, the black insertion input signal terminal BI in each sub shift register 10 may be coupled to the first node N1 of the previous sub shift register 10 to implement cascade black insertion. Wherein S is not less than 1 and is an integer. It should be noted that the black insertion input signal terminal BI of the first S-stage sub-shift register 10 may be coupled to the black insertion initialization signal.

Illustratively, in the scan driving circuit 100, the black insertion input signal terminals BI of the first eight sub-shift registers 10 are coupled to the black insertion initialization signal line STV1, and the black insertion input signal terminals BI of the remaining sub-shift registers 10 are respectively coupled to the first node N1 of the first eighth sub-shift register 10, so as to implement the cascade black insertion.

Some embodiments of the present disclosure further provide a driving method of a scan driving circuit, which is applied to the scan driving circuit 100 described in any of the above embodiments.

In the scan drive circuit 100, in conjunction with fig. 18 and 24, each frame period includes a plurality of row scan periods, each including a scan phase P6 and a black insertion phase P7. Each sub shift register 10 of each shift register 1 of the scan drive circuit 100 (see fig. 14) is used to perform one row scan period.

In the scan phase, the sub-shift register 10 receives a scan input signal and a scan clock signal, and outputs a scan signal. At this time, the Data signal terminal Data of the pixel driving circuit in the sub-pixel P electrically connected to the sub-shift register 10 receives a display Data signal, so that the driving transistor T2 is turned on to control the sub-pixel P of one row electrically connected to the sub-shift register 10 to emit light.

The scan clock signal is a first clock signal output from the first clock signal terminal CLKE of the output circuit 12 of the sub-shift register 10 when the input circuit 11 of the sub-shift register 10 receives the scan input signal.

In the black insertion phase P7, the sub shift register 10 receives the black insertion input signal and the black insertion clock signal, and outputs a black insertion signal. At this time, the Data signal terminal Data of the pixel driving circuit in the sub-pixel P electrically connected to the sub-shift register 10 receives the black insertion Data signal, so that the driving transistor T2 is turned off to control the sub-pixels P of one row electrically connected to the sub-shift register 10 to stop emitting light. Wherein the voltage of the black insertion data signal is less than the voltage of the display data signal.

The black insertion clock signal is a first clock signal output from the first clock signal terminal CLKE of the output circuit 12 of the sub-shift register 10 when the input circuit 11 of the sub-shift register 10 receives the black insertion input signal.

In some embodiments, as shown in fig. 22 and 24, the black insertion phase P7 of the row scanning period performed by any one of the sub shift registers 10 follows the scanning phase P6 of the row scanning period performed by the last sub shift register 10 in the cascaded plurality of shift registers 1.

That is, the black insertion signal outputted from any shift register 1 is after the scanning signal is outputted from the last sub-shift register 10 in the cascaded shift registers 1. That is, after all the sub shift registers 10 output the scanning signal to cause the sub pixels electrically connected to the sub shift registers 10 to emit light, black insertion is sequentially performed for all the sub shift registers 10.

In this case, in the input circuit 11 of the sub shift register 10, the scan input signal and the black insertion input signal are transmitted at different times, respectively, and the scan input signal and the black insertion input signal can be multiplexed by one circuit. For example, the scan input signal terminal GI of the scan input circuit 111 mentioned above can also receive a black insertion input signal, so that black insertion can be achieved without providing the black insertion input circuit 112, the structure of the scan driving circuit 100 is simplified, and the yield of the scan driving circuit 100 and the display panel 1000 and the display device 2000 applied thereto is improved.

In other embodiments, as shown in fig. 18 and 20, the black insertion phase P7 of the row scanning period executed by each sub-shift register 10 of the shift register 1 is after the scanning phase P6 of the plurality of row scanning periods executed by the plurality of sub-shift registers 10 of the shift register 1 and before the data signal writing of one row of sub-pixels P corresponding to the row scanning period executed by one sub-shift register 10 of the other shift registers 1, i.e., before the data writing phase P2 in fig. 5.

That is, the sub-shift registers 10 of the shift register 1 include the black insertion input circuit 112, and the black insertion signal outputted by each shift register 1 is after the last sub-shift register 10 in the shift register 1 outputs the scan signal and before the data signal of the sub-pixel P in one row corresponding to one sub-shift register 10 in the other shift register 1 is written, i.e., before the data writing stage P2 in fig. 5.

Illustratively, the black insertion signal outputted by each shift register 1 except the last shift register 1 is after the last sub-shift register 10 in the shift register 1 outputs the scan signal and before the data signal writing of the sub-pixel P in one row corresponding to the first sub-shift register 10 in the next shift register 1.

It should be noted that the black insertion signal output by the last shift register 1 may be after the last sub-shift register 10 in the last shift register 1 outputs the scan signal and before the data signal of the sub-pixel P in one row corresponding to the first sub-shift register 10 in the first shift register 1 is written.

Some embodiments of the present disclosure also provide a driving method of the shift register 1, as shown in fig. 9, 10 and 16, the shift register 1 (see fig. 15) includes a plurality of sub-shift registers 10, each sub-shift register 10 corresponds to one line scanning period in one frame period, and the line scanning period includes a scanning phase P6 and a black insertion phase P7.

The black insertion phase P7 starts at the same time as the data signal writing of the sub-pixels P in one row driven by the set row scanning period starts, and the ratio of the duration of the black insertion phase P7 to the duration of the data signal writing of the sub-pixels P in one row driven by the set row scanning period is less than or equal to 1/2. Setting the line scanning time interval as the line scanning time interval corresponding to one sub-shift register 10 of other shift registers 1; for example, except for the last shift register 1, the line scanning period is set as the next stage line scanning period; the set line scanning period corresponding to the last shift register 1 may be a line scanning period corresponding to the first shift register 1.

That is, each shift register 1 in the scan driving circuit 100 uses one sub-shift register 10 in the other shift register 1, and the first half of the time period for writing the data signal of the connected row of sub-pixels P is black-inserted, i.e. the first half of the data writing phase P2 in fig. 5; that is, in the sub-shift register 10 which is performing the black insertion phase P7 in the row scanning period, the Data signal terminal Data of the pixel driving circuit in the one row of the sub-pixels P to which the electric connection is made is written at most, and in the sub-shift register 10 which is performing the scanning phase P6 in the row scanning period, the first half of the display Data signal received by the Data signal terminal Data of the pixel driving circuit in the one row of the sub-pixels P to which the electric connection is made. The voltage of the display Data signal transmitted by the Data signal terminal Data gradually rises from low to high, and when the voltage of the first node G is the peak voltage corresponding to the first half of the display Data signal, Vgs is still smaller than Vth. In this way, when the sub-shift register 10 in the black insertion phase P7 is being performed, the voltage at the first node G in the pixel driving circuit in the electrically connected sub-pixel P in one row is pulled low, Vgs is smaller than Vth, and the driving transistor T2 is turned off, so that the sub-pixel P stops emitting light and is switched to a black screen.

That is, the driving method of the shift register 1 according to the present disclosure can increase the black insertion data writing Time on the basis of the Time of not compressing the data writing when the refresh frequency is constant, and insert the black Picture in the process of emitting light to perform normal image display of the sub-pixel P, thereby increasing the MPRT (Motion Picture Response Time), improving the phenomenon of Motion Picture smear, and improving the image display effect.

Some embodiments of the present disclosure also provide a shift register 1 for implementing the driving method of the shift register described in the above embodiments. Referring to fig. 7 and 9, the shift register 1 includes a plurality of sub-shift registers 10, and each sub-shift register 10 electrically connects a plurality of pixel driving circuits in one row of sub-pixels P (see fig. 2). The sub shift register 10 includes a scan input circuit 111, a black insertion input circuit 112, and an output circuit 12.

It should be noted that, the scan input circuit 111, the black insertion input circuit 112, and the output circuit 12 may specifically refer to the descriptions in some embodiments, and are not described herein again.

Here, referring to fig. 16, the timing at which the black insertion signal starts to be output is the same as the timing at which the data signal writing starts for the one row of sub-pixels P connected to the setting sub-shift register 10, that is, the timing at which the data writing phase P2 starts in fig. 5. Also, the ratio of the duration of the black insertion signal to the duration of the data signal writing for the sub-pixel P of one row to which the sub-shift register 10 is set is less than or equal to 1/2, i.e., the ratio of the duration of the data writing phase P2 (see fig. 5) for the sub-pixel P of one row to which the sub-shift register 10 is set is less than or equal to 1/2. The sub shift register 10 is set as one sub shift register 10 of the other shift registers 1. For example, except for the last shift register 1, the sub-shift register 10 is set as the first sub-shift register 10 in the next stage of shift register 1; the setting sub-shift register 10 corresponding to the last shift register 1 may be the first sub-shift register 10 in the first shift register 1.

The beneficial effects of the shift register 1 provided in some embodiments of the present disclosure are the same as the beneficial effects of the driving method of the shift register provided in the above technical solution, and are not described herein again.

Some embodiments of the present disclosure also provide a scan driving circuit 100 including a plurality of shift registers 1 as described in the above embodiments in cascade.

In some embodiments, the scan driving circuit 100 includes a plurality of first clock signal line groups 30, each of the first clock signal line groups 30 includes at least a plurality of first clock signal lines 31, and the plurality of first clock signal terminals CLKE of each of the shift registers 1 are coupled to the plurality of first clock signal lines 31 of one of the first clock signal line groups 30 in a one-to-one correspondence.

For example, in the case where the shift register 1 includes eight sub-shift registers 10, each of the first clock signal line groups 30 may include 8 first clock signal lines 31(CLK5 to CLK12 or CLK13 to CLK20), and the timing chart is shown in fig. 17.

The beneficial effects of the scan driving circuit 100 provided in some embodiments of the present disclosure are the same as the beneficial effects of the driving method of the shift register provided in the above technical solution, and are not described herein again.

As shown in fig. 2 and fig. 3, some embodiments of the present disclosure further provide a display panel 1000, including the scan driving circuit 100 of any of the above embodiments and a plurality of sub-pixels P arranged in an array, the scan driving circuit 100 being electrically connected to the plurality of sub-pixels P.

As shown in fig. 1, some embodiments of the present disclosure also provide a display device 2000 including the display panel 1000 and the timing controller of any of the above embodiments.

Wherein, the timing controller is electrically connected with the display panel 1000. The timing controller is configured to transmit a scan clock signal and a black insertion clock signal to the display panel 1000. The scan clock signal received at the first clock signal terminal CLKE of each sub shift register 10 is the same as the scan signal output at the first output signal terminal Oput1 of the sub shift register 10, and the black inserted clock signal received at the first clock signal terminal CLKE of each sub shift register 10 is the same as the black inserted signal output at the first output signal terminal Oput1 of the sub shift register 10. It should be noted that the timing controller is further configured to transmit a scan initialization signal and a black insertion initialization signal to the scan driving circuit 100 of the display panel 1000.

The beneficial effects of the display panel 1000 and the display device 2000 provided by some embodiments of the present disclosure are the same as the beneficial effects of the driving method of the shift register provided by the above technical solution, and are not described herein again.

The above description is only for the specific embodiments of the present disclosure, but the scope of the present disclosure is not limited thereto, and any person skilled in the art will appreciate that changes or substitutions within the technical scope of the present disclosure are included in the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. The driving method of the shift register is characterized in that the shift register comprises a plurality of sub shift registers, each sub shift register corresponds to a line scanning period in one frame period, and the line scanning period comprises a scanning stage and a black insertion stage;

the plurality of line scanning periods corresponding to the plurality of sub-shift registers comprise at least M line scanning period groups, each line scanning period group comprises N line scanning periods, and the time sequences of the scanning stages of the N line scanning periods are the same; m is more than or equal to 1, N is more than or equal to 2, and M and N are integers;

a time at which a black insertion phase of the line scanning period starts is after a scanning phase of a last line scanning period of the plurality of line scanning periods; the duration of the black insertion phase is less than or equal to the reference time difference of the starting times of two scanning phases in the condition that scanning signals are output row by row in two adjacent row scanning periods, and the black insertion phase of the plurality of row scanning periods comprises M (N-1) time sequences at most.

2. The driving method according to claim 1, wherein timings of black insertion phases of the plurality of row scanning periods are the same; alternatively, the first and second electrodes may be,

the black insertion stages of the plurality of line scanning time periods comprise at least two time sequences, and the time sequences of the black insertion stages of at least two line scanning time periods are the same; alternatively, the first and second electrodes may be,

the black insertion phases of the plurality of line scanning periods include at least two timings, and the black insertion phase of a relatively earlier line scanning period is earlier than the black insertion phase of a relatively later line scanning period.

3. The driving method according to claim 1 or 2, wherein the shift register includes eight sub-shift registers corresponding to eight line scanning periods, respectively, in one frame period;

the eight line scanning periods comprise a line scanning period group, each line scanning period group comprises two line scanning periods, and the time sequences of eight black insertion phases of the eight line scanning periods are the same;

or, the eight line scanning periods comprise two line scanning period groups, each line scanning period group comprising two line scanning periods; the eight black insertion stages of the eight line scanning periods comprise two time sequences, the time sequences of the black insertion stages of the first four line scanning periods are the same, and the time sequences of the black insertion stages of the last four line scanning periods are the same;

or, the eight line scanning periods comprise four line scanning period groups, each line scanning period group comprising two line scanning periods; the eight black insertion phases of the eight row scanning periods comprise four time sequences, and the time sequences of the black insertion phases of each row scanning period group are the same.

4. A shift register for performing the method of driving a shift register according to any one of claims 1 to 3; the shift register comprises a plurality of sub shift registers, and each sub shift register is electrically connected with a row of sub pixels; the sub shift register includes:

an input circuit coupled to the input signal terminal and the first node; the input circuit is configured to transmit a scan input signal to the first node in response to the scan input signal being received at the input signal terminal; and, in response to a black inserted input signal received at said input signal terminal, transmitting said black inserted input signal to said first node;

an output circuit coupled to the first node, a first clock signal terminal CLKE and a first output signal terminal; the output circuit is configured to transmit a scan clock signal received at the first clock signal terminal to the first output signal terminal to cause the first output signal terminal to output a scan signal in a case where the scan input signal is transmitted to the first node; and transmitting a black insertion clock signal received at the first clock signal terminal to the first output signal terminal so that the first output signal terminal outputs a black insertion signal, in a case where the black insertion input signal is transmitted to the first node;

the shift register comprises M sub-shift register groups, each sub-shift register group comprises N adjacent sub-shift registers, M is not less than 1, N is not less than 2, and M and N are integers; the N sub shift registers are configured to receive scanning clock signals with the same time sequence so as to output scanning signals with the same time sequence;

the black insertion signal starts to be output after the data signal writing of a row of sub-pixels connected with the last sub-shift register in the plurality of sub-shift registers is finished; the duration of the black insertion signal is less than or equal to the reference time difference of the start time of two scanning signals under the condition that the scanning signals are output by two adjacent sub-shift registers line by line; the black insertion signals output by the plurality of sub shift registers include M (N-1) kinds of time sequences at most.

5. A scan driver circuit comprising a plurality of shift registers according to claim 4 in cascade.

6. The scan driving circuit according to claim 5, wherein each of the shift registers includes X sub-shift registers, X ≧ 2, and X is an integer; the scanning driving circuit also comprises a plurality of first clock signal line groups, wherein each first clock signal line group at least comprises X-M X (N-1) first clock signal lines;

the plurality of first clock signal terminals of each shift register are coupled to the plurality of first clock signal lines of one first clock signal line group.

7. The scan driving circuit of claim 6, wherein the shift register has the first clock signal terminal of the N sub-shift registers of each sub-shift register group coupled to a same first clock signal line, and different sub-shift register groups coupled to different first clock signal lines;

in the shift register, the first clock signal ends of all the other sub-shift registers except the M sub-shift register groups are respectively coupled with different first clock signal lines.

8. A driving method of a scan driving circuit, applied to the scan driving circuit according to any one of claims 5 to 7, wherein each frame period includes a plurality of line scanning periods, each line scanning period including a scanning phase and a black insertion phase; each sub-shift register of each shift register of the scan driving circuit is configured to perform one row scan period;

in the scanning stage, the sub-shift register receives a scanning input signal and a scanning clock signal and outputs a scanning signal to control a row of sub-pixels electrically connected with the sub-shift register to emit light;

and in the black insertion stage, the input circuit receives a black insertion input signal and a black insertion clock signal and outputs a black insertion signal so as to control a row of sub-pixels electrically connected with the sub-shift register to stop emitting light.

9. The driving method according to claim 8, wherein the black insertion phase of the row scanning period performed by each sub-shift register of the shift register is after the scanning phase of the plurality of row scanning periods performed by the plurality of sub-shift registers of the shift register and before writing of the one row of sub-pixel data signals corresponding to the row scanning period performed by one sub-shift register of the other shift registers.

10. The driving method according to claim 8, wherein the black insertion phase of the row scanning period performed by any of the sub shift registers follows the scanning phase of the row scanning period performed by the last sub shift register in the plurality of shift registers in cascade.

11. The driving method of the shift register is characterized in that the shift register comprises a plurality of sub shift registers, each sub shift register corresponds to a line scanning period in one frame period, and the line scanning period comprises a scanning stage and a black insertion stage;

the starting time of the black insertion phase is the same as the starting time of writing data signals of a row of sub-pixels driven by a set row scanning period, and the ratio of the duration of the black insertion phase to the duration of writing data signals of a row of sub-pixels driven by the set row scanning period is less than or equal to 1/2; the set line scanning time interval is a line scanning time interval corresponding to one sub-shift register of other shift registers.

12. A shift register for executing the shift register driving method according to claim 11; the shift register comprises a plurality of sub shift registers, and each sub shift register is electrically connected with a row of sub pixels; the sub shift register includes:

a scan input circuit coupled to the scan input signal terminal and the first node; the scan-in circuit is configured to transmit a scan-in signal to the first node in response to a scan-in signal received at the scan-in signal terminal;

the black insertion input circuit is coupled with the black insertion signal end and the first node; the black insertion input circuit is configured to transmit the black insertion input signal to the first node in response to a black insertion input signal received at the black insertion input signal terminal;

13. A scan driver circuit comprising a plurality of shift registers as claimed in claim 12 in cascade.

14. A display panel, comprising:

a plurality of sub-pixels arranged in an array;

the scan driving circuit according to any one of claims 6 to 8 and 13, electrically connected to the plurality of sub-pixels.

15. A display device, comprising:

the display panel of claim 14;

the time schedule controller is electrically connected with the display panel; the timing controller is configured to transmit a scan clock signal and a black insertion clock signal to the display panel; the scanning clock signal received by the first clock signal end of each sub-shift register is the same as the scanning signal output by the first output signal end of the sub-shift register, and the black insertion clock signal received by the first clock signal end of each sub-shift register is the same as the black insertion signal output by the first output signal end of the sub-shift register.