CN117908799A - Data writing method and device, electronic equipment and storage medium - Google Patents
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Abstract
The present invention relates to the field of computer technologies, and in particular, to a data writing method, a data writing device, an electronic device, and a storage medium. Acquiring current data to be written, and determining a current target memory for writing the current data to be written; transmitting the current data to be written into a writing-in and writing-out space of the current target memory by utilizing a hardware data transmission channel; sending an operation instruction to a current target memory so that the current target memory writes the current data to be written into the internal storage space corresponding to the current target memory from the writing-out space; after an operation instruction is sent to a current target memory, acquiring the next data to be written after the current data to be written; and cycling the steps until the data to be written is completely written. The method has the advantages that the current target memory does not need to wait for writing the current data to be written into the internal storage space, the data writing speed is improved, the time is saved, the data writing efficiency is improved, the utilization rate of the CPU is greatly optimized, and the cost is lower.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a data writing method, a data writing device, an electronic device, and a storage medium.
Background
With the higher and higher integration level of chips, current mobile phones, tablet computers and the like integrate common digital functions such as internet surfing, games, music playing, video playing, photographing and the like, and more functions naturally also have higher requirements on storage. Flash is the most commonly used non-volatile memory at present, and NAND FLASH has the advantages of higher storage density, higher writing and erasing speeds, more erasable times and the like in terms of Flash use due to lower unit bit cost compared with NOR Flash.
NAND FLASH, because of the complex interface timing, needs to be equipped with a specific controller when in use, and can only operate in units of pages when data is read and written.
Therefore, NAND FLASH is slow in writing speed and low in CPU utilization.
Disclosure of Invention
In view of the above, the present invention provides a data writing method, apparatus, electronic device and storage medium, so as to solve the problems of slower NAND FLASH writing speed and lower CPU utilization in the prior art.
In a first aspect, the present invention provides a data writing method, including:
acquiring current data to be written, and determining a current target memory for writing the current data to be written;
Transmitting the current data to be written into a writing-in and writing-out space of the current target memory by utilizing a hardware data transmission channel;
sending an operation instruction to a current target memory so that the current target memory writes the current data to be written into the internal storage space corresponding to the current target memory from the writing-out space;
After an operation instruction is sent to a current target memory, acquiring the next data to be written after the current data to be written; and cycling the steps until the data to be written is completely written.
According to the data writing method provided by the embodiment of the application, the current data to be written is obtained, the current target memory for writing the current data to be written is determined, and the accuracy of the determined current target memory for writing the current data to be written is ensured. And the hardware data transmission channel is utilized to transmit the current data to be written into the writing-out space of the current target memory, so that the data transmission speed of transmitting the current data to be written into the writing-out space of the current target memory is accelerated, and the event of data transmission is saved. Sending an operation instruction to a current target memory so that the current target memory writes the current data to be written into the internal storage space corresponding to the current target memory from the writing-out space; after an operation instruction is sent to a current target memory, acquiring the next data to be written after the current data to be written; and cycling the steps until the data to be written is completely written. Therefore, the current data to be written is not required to be written into the internal storage space corresponding to the current target memory from the writing-out and writing-in space by waiting for the current target memory, the data writing speed is improved, the time is saved, the data writing efficiency is improved, the utilization rate of the CPU is greatly optimized, and the cost is lower.
In an alternative embodiment, determining the current target memory to which the current data to be written is written includes:
Acquiring the current state corresponding to each memory;
And determining the memory in the idle state as the current target memory for writing the current data to be written according to the current state of each memory.
The data writing method provided by the embodiment of the application obtains the current state corresponding to each memory; according to the current state of each memory, the memory in the idle state is determined to be the current target memory for writing the current data to be written, so that the accuracy of the determined current target memory is ensured, a plurality of memories can be used for writing the data simultaneously, the data writing speed is improved, the time is saved, the data writing efficiency is improved, and the utilization rate of a CPU is greatly optimized.
In an alternative embodiment, using a hardware data transmission channel, transmitting the current data to be written to the writing-out space of the current target memory includes:
Acquiring a source address and a destination address corresponding to current data to be written; the source address is the address of the current storage device corresponding to the current data to be written; the destination address is the address of the current target memory;
acquiring the data length corresponding to the current data to be written;
configuring a hardware data transmission channel according to the source address, the destination address and the data length;
And transmitting the current data to be written into the writing-in and writing-out space of the current target memory by using the configured hardware data transmission channel.
According to the data writing method provided by the embodiment of the application, the source address and the destination address corresponding to the current data to be written are obtained, and the data length corresponding to the current data to be written is obtained; according to the source address, the destination address and the data length, the hardware data transmission channel is configured, and the accuracy of configuring the hardware data transmission channel is ensured. And the configured hardware data transmission channel is utilized to transmit the data to be written currently to the writing-in and writing-out space of the current target memory, so that the data writing speed is improved, and the data writing efficiency is improved.
In an alternative embodiment, using the configured hardware data transmission channel, the writing/writing space for transmitting the data to be written to the current target memory includes:
calculating first check data corresponding to the current data to be written by using a preset data check method;
And transmitting the current data to be written and the first check data to a writing-out space of the current target memory by using the configured hardware data transmission channel.
According to the data writing method provided by the embodiment of the application, the first check data corresponding to the current data to be written is calculated by using a preset data check method; the accuracy of the first check data corresponding to the current data to be written is ensured. And transmitting the current data to be written and the first check data to a writing-in and writing-out space of the current target memory by using the configured hardware data transmission channel, so that the current data to be written can be checked according to the first check data.
In an alternative embodiment, the method further comprises:
acquiring current data to be written in a writing-out space;
calculating second check data corresponding to the current data to be written by using a preset data check method again;
Comparing the first check data with the second check data;
When the first check data and the second check data are the same, determining that the current data to be written in the writing-out space is accurate;
When the first check data and the second check data are different, the fact that the current data to be written in the writing-out space are inaccurate is determined, an abnormal interrupt signal is generated, and the abnormal interrupt signal is output to a user.
According to the data writing method provided by the embodiment of the application, the current data to be written is obtained in the writing-out space; and calculating second check data corresponding to the current data to be written by using a preset data check method, so that the accuracy of the calculated second check data is ensured. Comparing the first check data with the second check data; when the first check data and the second check data are the same, determining that the current data to be written in the writing-out space is accurate; when the first check data and the second check data are different, the fact that the current data to be written in the writing-out space are inaccurate is determined, an abnormal interrupt signal is generated, and the abnormal interrupt signal is output to a user. Thereby ensuring the accuracy of data transmission by using the hardware data transmission channel.
In an alternative embodiment, sending the operation instruction to the current target memory includes:
after the hardware data transmission channel transmits the current data to be written to the writing-out space, receiving a transportation completion instruction transmitted by the hardware data transmission channel;
after receiving the transport completion instruction, acquiring configuration information corresponding to a target bus protocol;
configuring a target bus protocol according to the configuration information;
Based on a target bus protocol, sending an operation instruction to a current target memory; the operation instruction comprises current data to be written in and a writing address for writing the current data to be written in the current target memory; the write address is used to characterize the row address and column address of the current data to be written in the current target memory.
According to the data writing method provided by the embodiment of the application, after the hardware data transmission channel transmits the current data to be written to the writing-out space, a transportation completion instruction transmitted by the hardware data transmission channel is received; therefore, the condition that the current data to be written is transmitted to the writing-out space can be timely obtained. After receiving the transport completion instruction, acquiring configuration information corresponding to a target bus protocol; and the target bus protocol is configured according to the configuration information, so that the accuracy of configuring the target bus protocol is ensured. Based on the target bus protocol, an operation instruction is sent to the current target memory, so that the accuracy of sending the operation instruction to the current target memory is ensured.
In an alternative embodiment, after sending the operation instruction to the current target memory based on the target bus protocol, the method further includes:
inquiring a state machine corresponding to the current target memory;
If the state machine represents that the current target memory is in a working state, determining that the operation instruction is successfully sent;
If the state machine represents that the current target memory is in an idle state, determining that the operation instruction is not sent successfully;
If the operation instruction is not successfully sent, sending the operation instruction to the current target memory again;
Until the operation instruction is successfully sent;
correspondingly, after sending an operation instruction to the current target memory, acquiring the next data to be written after the current data to be written, including:
After the operation instruction is successfully sent, the next data to be written after the current data to be written is obtained.
According to the data writing method provided by the embodiment of the application, a state machine corresponding to the current target memory is inquired, and if the state machine represents that the current target memory is in a working state, the successful sending of the operation instruction is determined; if the state machine indicates that the current target memory is in an idle state, the fact that the operation instruction is not sent successfully is determined, so that whether the operation instruction is sent successfully or not can be timely obtained. If the operation instruction is not successfully sent, sending the operation instruction to the current target memory again; until the operation instruction is successfully sent; therefore, the success of the transmission of the operation instruction is ensured, and the failure of data writing caused by the success of the transmission of the operation instruction is avoided. Correspondingly, after sending an operation instruction to the current target memory, acquiring the next data to be written after the current data to be written, including: after the operation instruction is successfully sent, the next data to be written after the current data to be written is obtained. Therefore, the current data to be written is not required to be written into the internal storage space corresponding to the current target memory from the writing-out and writing-in space by waiting for the current target memory, the data writing speed is improved, the time is saved, the data writing efficiency is improved, the utilization rate of a CPU is greatly optimized, and the data writing accuracy is ensured.
In a second aspect, the present invention provides a data writing apparatus, the apparatus comprising:
The first acquisition module is used for acquiring the current data to be written and determining a current target memory for writing the current data to be written;
the transmission module is used for transmitting the current data to be written into the writing-in and writing-out space of the current target memory by utilizing the hardware data transmission channel;
The sending module is used for sending an operation instruction to the current target memory so that the current target memory writes the current data to be written into the internal memory space corresponding to the current target memory from the writing-out space;
the second acquisition module is used for acquiring the next data to be written after the current data to be written after sending the operation instruction to the current target memory; and cycling the steps until the data to be written is completely written.
The data writing device provided by the embodiment of the application acquires the current data to be written, determines the current target memory for writing the current data to be written, and ensures the accuracy of the determined current target memory for writing the current data to be written. And the hardware data transmission channel is utilized to transmit the current data to be written into the writing-out space of the current target memory, so that the data transmission speed of transmitting the current data to be written into the writing-out space of the current target memory is accelerated, and the event of data transmission is saved. Sending an operation instruction to a current target memory so that the current target memory writes the current data to be written into the internal storage space corresponding to the current target memory from the writing-out space; after an operation instruction is sent to a current target memory, acquiring the next data to be written after the current data to be written; and cycling the steps until the data to be written is completely written. Therefore, the current data to be written is not required to be written into the internal storage space corresponding to the current target memory from the writing-out and writing-in space by waiting for the current target memory, the data writing speed is improved, the time is saved, the data writing-in efficiency is improved, and the utilization rate of the CPU is greatly optimized.
In a third aspect, the present invention provides an electronic device, comprising: the memory and the processor are in communication connection with each other, the memory stores computer instructions, and the processor executes the computer instructions, thereby executing the data writing method according to the first aspect or any implementation manner corresponding to the first aspect.
In a fourth aspect, the present invention provides a computer-readable storage medium having stored thereon computer instructions for causing a computer to perform the data writing method of the first aspect or any of its corresponding embodiments.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a data writing method according to an embodiment of the invention;
FIG. 2 is a flow chart of another data writing method according to an embodiment of the invention;
FIG. 3 is a flow chart of yet another data writing method according to an embodiment of the present invention;
FIG. 4 is a flow chart of yet another data writing method according to an embodiment of the present invention;
FIG. 5 is a flow chart of a further data writing method according to an embodiment of the invention;
FIG. 6 is a flow chart of yet another data writing method according to an embodiment of the present invention;
FIG. 7 is a flow chart of yet another data writing method according to an embodiment of the present invention;
FIG. 8 is a flow chart of yet another data writing method according to an embodiment of the present invention;
Fig. 9 is a block diagram of a data writing apparatus according to an embodiment of the present invention;
fig. 10 is a schematic diagram of a hardware structure of an electronic device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
With the higher and higher integration level of chips, current mobile phones, tablet computers and the like integrate common digital functions such as internet surfing, games, music playing, video playing, photographing and the like, and more functions naturally also have higher requirements on storage. Flash is the most commonly used non-volatile memory at present, and NAND FLASH has the advantages of higher storage density, higher writing and erasing speeds, more erasable times and the like in terms of Flash use due to lower unit bit cost compared with NOR Flash.
NAND FLASH, because of the complex interface timing, needs to be equipped with a specific controller when in use, and can only operate in units of pages when data is read and written.
Therefore, NAND FLASH is slow in writing speed and low in CPU utilization.
At present, a common method for improving the writing speed of NAND FLASH controllers is to set a buffer memory in the controller, and improve the random writing speed by setting a large amount of buffer memories, but such a way brings about a problem: the cost is greatly increased while the speed is increased. This increase in cost is largely due to the waste of internal cache resources.
Therefore, a new design approach is needed to address this problem, i.e., to increase speed while at the same time compromising cost.
Based on the above, the embodiment of the application provides a data writing method, after transmitting the current data to be written to the writing-out space of the current target memory, an operation instruction is sent to the current target memory, and then the next data to be written after the current data to be written is acquired. Therefore, the current data to be written is not required to be written into the internal storage space corresponding to the current target memory from the writing-out and writing-in space by waiting for the current target memory, the data writing speed is improved, the time is saved, the data writing efficiency is improved, the utilization rate of the CPU is greatly optimized, and the cost is lower.
According to an embodiment of the present invention, there is provided a data writing method embodiment, it being noted that the steps shown in the flowcharts of the drawings may be performed in a computer system such as a set of computer executable instructions, and that although a logical order is shown in the flowcharts, in some cases the steps shown or described may be performed in an order different from that herein.
It should be noted that, the execution body of the method for writing data provided in the embodiment of the present application may be a device for writing data, where the device for writing data may be implemented as part or all of an electronic device by software, hardware, or a combination of software and hardware, where the electronic device may be a server or a terminal, where the server in the embodiment of the present application may be a server or a server cluster formed by multiple servers, and the terminal in the embodiment of the present application may be a smart phone, a personal computer, a tablet computer, a wearable device, and other intelligent hardware devices such as an intelligent robot. In the following method embodiments, the execution subject is an electronic device.
In this embodiment, a data writing method is provided, which may be used in the above electronic device, such as a mobile phone, a tablet computer, etc., fig. 1 is a flowchart of the data writing method according to an embodiment of the present invention, and as shown in fig. 1, the flowchart includes the following steps:
step S101, obtaining the current data to be written, and determining the current target memory for writing the current data to be written.
Specifically, the electronic device may receive data to be written input by a user, and then determine current data to be written according to an order in which the data to be written is written; the electronic equipment can also receive a user command, search data to be written from the storage space, and then determine the current data to be written according to the sequence of writing the data to be written; the electronic device may also receive data to be written sent by other devices, and determine current data to be written according to the sequence of writing the data to be written.
The mode of the electronic device for acquiring the current data to be written is not particularly limited.
Optionally, after obtaining the current data to be written, the electronic device may determine, according to the state of each memory, a current target memory to which the current data to be written is written.
Optionally, after obtaining the current data to be written, the electronic device may further search, according to a user instruction, a current target memory in which the current data to be written is written.
The current target memory may be NAND FLASH registers or other registers. NAND FLASH is a non-volatile memory based on NAND technology. Compared with the traditional Flash memory, NAND FLASH has higher storage density, lower power consumption and longer service life. NAND FLASH is very simple in structure and mainly comprises elements such as a NAND chip, a capacitor, a resistor and the like; NAND FLASH has the advantages of larger memory capacity, high rewriting speed and the like, so that the memory is widely applied to the market.
This step will be described in detail below.
Step S102, transmitting the current data to be written into the writing-out space of the current target memory by utilizing a hardware data transmission channel.
Specifically, the electronic device may configure a hardware data transmission channel, and then transmit the data to be written currently to the write-out space of the current target memory using the hardware data transmission channel.
Wherein the hardware data transfer channel may be a DMA (Direct Memory Access ). Wherein a DMA transfer copies data from one address space to another address space, providing high speed data transfer between a peripheral and a memory or between a memory and a memory. When the CPU initiates this transfer action, the transfer action itself is implemented and completed by the DMA controller. The DMA transmission mode does not need direct control transmission of a CPU, and does not have the processes of reserving the site and recovering the site like an interrupt processing mode, and a channel for directly transmitting data is opened up for the RAM and the IO equipment through hardware, so that the efficiency of the CPU is greatly improved.
Step S103, an operation instruction is sent to the current target memory, so that the current target memory writes the current data to be written into the internal memory space corresponding to the current target memory from the writing-out space.
Specifically, after transmitting the current data to be written to the write-out space of the current target memory using the hardware data transmission channel, the electronic device may send an operation instruction to the current target memory.
The operation instruction is used for indicating the current target memory to write the current data to be written into the internal storage space corresponding to the current target memory from the write-out space.
It should be noted that, the process of writing the current data to be written into the internal storage space corresponding to the current target memory from the write-out space by the current target memory may be divided into two steps, where the first step is to write the current data to be written into the cache register of the current target memory, and the second step is to write the data in the cache register into the internal storage space of Flash. Therefore, the current target memory takes a long time when writing the current data to be written from the write-out space to the internal memory space corresponding to the current target memory.
Step S104, after an operation instruction is sent to a current target memory, acquiring the next data to be written after the current data to be written; and cycling the steps until the data to be written is completely written.
Specifically, after an operation instruction is sent to the current target memory, the current target memory may not wait for the current target memory to complete the task of writing the current data to be written into the internal memory space corresponding to the current target memory from the writing-out space, but the electronic device obtains the next data to be written after the current data to be written, and then determines the next target memory to which the next previous data to be written is written; transmitting the next data to be written into a writing-in and writing-out space of the next target memory by utilizing a hardware data transmission channel; and sending the operation instruction to the next target memory again. And cycling the steps until the data to be written is completely written.
According to the data writing method provided by the embodiment of the application, the current data to be written is obtained, the current target memory for writing the current data to be written is determined, and the accuracy of the determined current target memory for writing the current data to be written is ensured. And the hardware data transmission channel is utilized to transmit the current data to be written into the writing-out space of the current target memory, so that the data transmission speed of transmitting the current data to be written into the writing-out space of the current target memory is accelerated, and the event of data transmission is saved. Sending an operation instruction to a current target memory so that the current target memory writes the current data to be written into the internal storage space corresponding to the current target memory from the writing-out space; after an operation instruction is sent to a current target memory, acquiring the next data to be written after the current data to be written; and cycling the steps until the data to be written is completely written. Therefore, the current data to be written is not required to be written into the internal storage space corresponding to the current target memory from the writing-out and writing-in space by waiting for the current target memory, the data writing speed is improved, the time is saved, the data writing efficiency is improved, the utilization rate of the CPU is greatly optimized, and the cost is lower.
In this embodiment, a data writing method is provided, which may be used in the above mobile terminal, such as a mobile phone, a tablet computer, etc., fig. 2 is a flowchart of the data writing method according to an embodiment of the present invention, and as shown in fig. 2, the flowchart includes the following steps:
Step S201, obtaining the current data to be written, and determining the current target memory for writing the current data to be written.
In an alternative embodiment of the present application, the determining the current target memory to which the data to be written is written in step S201 includes:
s2011, obtaining the current state corresponding to each memory.
Specifically, the electronic device may read the state machine corresponding to each memory, and determine the current state corresponding to each memory according to the state machine corresponding to each memory.
Specifically, when the state machine identifier corresponding to the memory is 1, determining that the current state corresponding to the memory is an operating state; when the state machine identifier corresponding to the memory is 0, determining that the current state corresponding to the memory is an idle state.
S2012, according to the current state of each memory, determining the memory in the idle state as the current target memory to which the current data to be written is written.
Specifically, after acquiring the current state of each memory, the electronic device may determine that the memory in the idle state is a candidate memory.
Alternatively, the electronic device may randomly select one candidate memory from the candidate memories as the current target memory.
Optionally, the electronic device may obtain the remaining memory capacity corresponding to each candidate memory, and compare the remaining memory capacity of each candidate memory with the data amount of the current data to be written. And selecting a candidate memory with the residual content capacity larger than the data amount of the current data to be written from the candidate memories as a target memory, wherein the difference between the residual content capacity and the data amount of the current data to be written is the smallest, so that memory fragmentation can be reduced.
Step S202, using the hardware data transmission channel to transmit the current data to be written into the writing-out space of the current target memory.
Specifically, after determining the current target memory corresponding to the current data to be written, the electronic device may configure a hardware data transmission channel according to the address corresponding to the current target memory, and then transmit the current data to be written to the writing-out space of the current target memory by using the hardware data transmission channel.
In an alternative embodiment of the present application, the step S202 may include:
In step S2021, the source address and the destination address corresponding to the current data to be written are obtained.
The source address is the address of the current storage device corresponding to the current data to be written; the destination address is the address of the current target memory.
Specifically, the electronic device reads the storage device corresponding to the current data to be written, and obtains the address of the storage device corresponding to the current data to be written, so as to determine the source address corresponding to the current data to be written. And then, the electronic equipment reads the address corresponding to the current target memory to acquire the destination address corresponding to the current data to be written.
In step S2022, the data length corresponding to the current data to be written is obtained.
Specifically, the electronic device may read the current data to be written, and determine a data length corresponding to the current data to be written.
In step S2023, the hardware data transmission channel is configured according to the source address, the destination address and the data length.
Specifically, the electronic device may configure the hardware data transmission channel according to the source address, the destination address, and the data length.
In step S2024, the configured hardware data transmission channel is used to transmit the data to be written to the writing-out space of the current target memory.
Optionally, the step S2024 may include:
Step a1, calculating first check data corresponding to the current data to be written by using a preset data check method.
Specifically, the electronic device may calculate, by using a preset data verification method, first verification data corresponding to the data to be written currently.
The preset data checking method may be any one of a parity checking method, a longitudinal redundancy check (Longitudinal Redundancy Check, LRC) method, a cyclic redundancy check (Cyclic Redundancy Codes, CRC) method, and the like, and the preset checking method is not specifically limited in the embodiment of the present application.
And a2, transmitting the current data to be written and the first check data to a writing-out space of the current target memory by using the configured hardware data transmission channel.
Specifically, the electronic device may use the configured hardware data transmission channel to input the current data to be written and the first check data together into the writing-out space of the current target memory.
And a step a3, obtaining the current data to be written in the writing-out space.
Specifically, after the electronic device inputs the current data to be written and the first check data to the writing-out space of the current target memory together, the electronic device may acquire the current data to be written in the writing-out space.
And a4, calculating second check data corresponding to the current data to be written by using a preset data check method again.
Specifically, the electronic device calculates second check data corresponding to the data to be written currently by using the preset data check method again.
And a step a5, comparing the first check data with the second check data.
Specifically, the electronic device compares the calculated second check data with the transmitted first check data. And determining whether an abnormality occurs in the current data transmission process to be written according to the comparison result.
And a step a6, when the first check data and the second check data are the same, determining that the current data to be written in the write-out space is accurate.
Specifically, when the first check data and the second check data are the same, the electronic device determines that the current data to be written in the writing-out space is accurate, and no abnormality occurs in the transmission process of the current data to be written.
And a step a7 of determining that the current data to be written in the writing-out space is inaccurate when the first check data and the second check data are different, generating an abnormal interrupt signal and outputting the abnormal interrupt signal to a user.
Specifically, when the first check data and the second check data are different, the electronic device determines that the current data to be written in the writing-out space is inaccurate, and an abnormality occurs in the transmission process of the current data to be written, so that the electronic device generates an abnormal interrupt signal and outputs the abnormal interrupt signal to a user, so that the user knows that the abnormality occurs in the transmission process of the current data to be written.
Step S203, an operation instruction is sent to the current target memory, so that the current target memory writes the current data to be written into the internal memory space corresponding to the current target memory from the write-out space.
For this step, please refer to fig. 1 for description of step S103, and detailed description thereof is omitted herein.
Step S204, after sending an operation instruction to a current target memory, acquiring the next data to be written after the current data to be written; and cycling the steps until the data to be written is completely written.
For this step, please refer to fig. 1 for description of step S104, and detailed description thereof is omitted herein.
The data writing method provided by the embodiment of the application obtains the current state corresponding to each memory; according to the current state of each memory, the memory in the idle state is determined to be the current target memory for writing the current data to be written, so that the accuracy of the determined current target memory is ensured, a plurality of memories can be used for writing the data simultaneously, the data writing speed is improved, the time is saved, the data writing efficiency is improved, and the utilization rate of a CPU is greatly optimized.
Then, acquiring a source address and a destination address corresponding to the current data to be written, and acquiring a data length corresponding to the current data to be written; according to the source address, the destination address and the data length, the hardware data transmission channel is configured, and the accuracy of configuring the hardware data transmission channel is ensured. Calculating first check data corresponding to the current data to be written by using a preset data check method; the accuracy of the first check data corresponding to the current data to be written is ensured. And transmitting the current data to be written and the first check data to a writing-in and writing-out space of the current target memory by using the configured hardware data transmission channel, so that the current data to be written can be checked according to the first check data. Acquiring current data to be written in a writing-out space; and calculating second check data corresponding to the current data to be written by using a preset data check method, so that the accuracy of the calculated second check data is ensured. Comparing the first check data with the second check data; when the first check data and the second check data are the same, determining that the current data to be written in the writing-out space is accurate; when the first check data and the second check data are different, the fact that the current data to be written in the writing-out space are inaccurate is determined, an abnormal interrupt signal is generated, and the abnormal interrupt signal is output to a user. Thereby ensuring the accuracy of data transmission by using the hardware data transmission channel.
In this embodiment, a data writing method is provided, which may be used in the above electronic device, such as a mobile phone, a tablet computer, etc., and fig. 3 is a flowchart of the data writing method according to an embodiment of the present invention, as shown in fig. 3, where the flowchart includes the following steps:
Step S301, the current data to be written is obtained, and the current target memory in which the current data to be written is determined.
For this step, please refer to the description of S201 in fig. 2, and a detailed description is omitted here.
In step S302, the data to be written is transferred to the write-write space of the current target memory by using the hardware data transfer channel.
For this step, please refer to the description of S202 in fig. 2, and a detailed description is omitted here.
Step S303, an operation instruction is sent to the current target memory, so that the current target memory writes the current data to be written into the internal memory space corresponding to the current target memory from the write-out space.
In an alternative embodiment of the present application, the step S303 may include the following steps:
In step S3031, after the hardware data transmission channel transmits the current data to be written to the writing-out space, a transport completion instruction transmitted by the hardware data transmission channel is received.
Specifically, after the hardware data transmission channel transmits the current data to be written to the writing-out space, the hardware data transmission channel sends a transportation completion instruction to the electronic device, so that the electronic device can receive the transportation completion instruction transmitted by the hardware data transmission channel.
Step S3032, after receiving the transport completion instruction, configuration information corresponding to the target bus protocol is obtained.
Specifically, after receiving the transport completion instruction, the electronic device may generate configuration information according to the configuration information corresponding to the target bus protocol input by the user, or may receive configuration information sent by other devices according to the current target memory.
The target bus protocol may be a QSPI protocol, among others. QSPI is Queued SPI short, is an SPI interface extension introduced by Motorola, and is more widely applied than SPI. On the basis of SPI protocol, motorola company can make its function be enhanced, and can add queue transmission mechanism and can exit from queue serial peripheral interface protocol (i.e. QSPI protocol). The QSPI is a special communication interface and is connected with a single, double or four (data line) SPI Flash storage medium.
The configuration information may include, but is not limited to, frequency division information, current target memory granule memory size, SCK mode, operation mode, T FIFO enable, DATA size, DATA mode, address size, address mode, instruction size, instruction mode, etc.
Step S3033, the target bus protocol is configured according to the configuration information.
Specifically, the electronic device may configure the target bus protocol according to the configuration information.
In step S3034, an operation instruction is sent to the current target memory based on the target bus protocol.
The operation instruction comprises current data to be written and a writing address for writing the current data to be written into the current target memory. The write address is used for representing a row address and a column address of the current data to be written in the current target memory.
Specifically, after the target bus protocol is configured, the electronic device may send an operation instruction to the current target memory according to the target bus protocol.
In an alternative embodiment of the present application, the step S3034 may further include the following steps:
and b1, inquiring a state machine corresponding to the current target memory.
Specifically, the electronic device may query the state machine corresponding to the current target memory.
And b2, if the state machine represents that the current target memory is in a working state, determining that the operation instruction is successfully sent.
Specifically, if the state machine corresponding to the current target memory is 1, the current target memory is characterized as being in a working state, and the electronic device determines that the operation instruction is successfully sent.
And b3, if the state machine represents that the current target memory is in an idle state, determining that the operation instruction is not sent successfully.
Specifically, if the state machine corresponding to the current target memory is 0, the current target memory is represented as an idle state, and it is determined that the operation instruction is not sent successfully.
And b4, if the operation instruction is not successfully sent, sending the operation instruction to the current target memory again.
And b5, until the operation instruction is successfully sent.
Specifically, if the operation instruction is not successfully sent, the operation instruction is sent to the current target memory again. Until the operation instruction is successfully sent.
In another optional embodiment of the present application, if the operation instruction is not sent successfully, the operation instruction is sent to the current target memory again, until the current target memory fails after the preset times, and the electronic device outputs an operation instruction sending failure message to the user.
Step S304, after an operation instruction is sent to a current target memory, acquiring the next data to be written after the current data to be written; and cycling the steps until the data to be written is completely written.
In step S3041, after the operation instruction is sent successfully, the next data to be written after the current data to be written is obtained.
Specifically, after the operation instruction is successfully sent, the electronic device continues to acquire the next data to be written after the current data to be written.
According to the data writing method provided by the embodiment of the application, after the hardware data transmission channel transmits the current data to be written to the writing-out space, a transportation completion instruction transmitted by the hardware data transmission channel is received; therefore, the condition that the current data to be written is transmitted to the writing-out space can be timely obtained. After receiving the transport completion instruction, acquiring configuration information corresponding to a target bus protocol; and the target bus protocol is configured according to the configuration information, so that the accuracy of configuring the target bus protocol is ensured. Based on the target bus protocol, an operation instruction is sent to the current target memory, so that the accuracy of sending the operation instruction to the current target memory is ensured.
Then, inquiring a state machine corresponding to the current target memory, and if the state machine represents that the current target memory is in a working state, determining that the operation instruction is successfully sent; if the state machine indicates that the current target memory is in an idle state, the fact that the operation instruction is not sent successfully is determined, so that whether the operation instruction is sent successfully or not can be timely obtained. If the operation instruction is not successfully sent, sending the operation instruction to the current target memory again; until the operation instruction is successfully sent; therefore, the success of the transmission of the operation instruction is ensured, and the failure of data writing caused by the success of the transmission of the operation instruction is avoided. Correspondingly, after sending an operation instruction to the current target memory, acquiring the next data to be written after the current data to be written, including: after the operation instruction is successfully sent, the next data to be written after the current data to be written is obtained. Thus, the Flash will be regarded as the current target memory without waiting
In order to better describe the flow chart of the data writing method provided by the embodiment of the application, as shown in fig. 4,
First, the CPU determines the specific Flash granule of the register and configures FLASH CHANNEL SELECT registers.
Secondly, the CPU configures the DMA, and specifically needs to configure information such as a start address (address in RAM), a destination address (address of QSPI FIFO), and a transfer data length of the DMA.
Thirdly, after configuration is effective, a first crc check value is calculated according to the original data, and the first crc check value is combined with the original data and carried to the FIFO space of the Flash.
And fourthly, in the FIFO space of the Flash, the original data is read, the second crc check value is recalculated, and the second crc check value and the first crc check value are compared to judge the consistency of the original data. If the second crc check value is inconsistent with the first crc check value, the CPU generates an abnormal interrupt signal, and the reliability of data transmission of qspi buses is improved by using the crc check. If the handling is successful, an interrupt signal for generating DMA done is given to the CPU. And carrying the data in the RAM to the FIFO space of the Flash.
Fifthly, configuring configuration information such as QSPI frequency division information, flash particle memory size, SCK mode, working mode, T FIFO enabling, DATA size, DATA mode, address size, address mode, instruction size, instruction mode and the like for a QSPI bus; the CPU starts the Program operation issued to the Flash through the QSPI bus.
And sixthly, starting to send a Program operation command, an address and corresponding original data to Flash based on configuration information of a QSPI bus.
And seventhly, the CPU queries whether the Program command is sent completely or not based on the QSPI bus until the command is sent completely.
And step eight, the CPU queries the state of Flash based on the QSPI bus until FlashProgram is completed.
Because the characteristic of Flash divides the process from the data Program to the Flash grain into two processes, the first step is to write the data into the cache register of Flash, and the second step is to write the data in the cache register into the grain of Flash.
Therefore, after the seventh step is completed, the first step is performed to select the second Flash granule for writing in the period of FlashProgram, after the second Flash granule is switched, the first step is performed again to switch to the next Flash granule after the seventh step is completed, and the flow after the seventh step is performed. And after all the processes are finished, if the data is needed to be written, continuing to execute the process from the first step, after the seventh step is finished, executing the first step to switch back to the second Flash particle, executing the process after the seventh step, and after all the processes are finished, if the data is needed to be written, continuing to execute the process from the first step, and the subsequent writing processes are similar. The writing speed of the plurality NAND FLASH of writing can be improved to the greatest extent according to the flow. For a better understanding of the ping-pong write process described above for multiple Flash, reference may be made to the software flow diagram of fig. 5.
As shown in fig. 6, two time lines for NAND FLASH writing different data can be clearly represented, the CPU configures the chip select register to switch to Flash1, after the QSPI is configured, the data a is written to Flash1, when the program flow of Flash1 starts, the chip select register is configured to switch to Flash2, after the QSPI is configured, the data B is written to Flash2, when the program flow of Flash2 starts, the chip select register is configured to switch to Flash1, and the writing state of the data a is checked. The CPU configures the chip select register to switch to Flash2 to check the writing state of the data B.
The system scheme of fig. 7 includes 2 DMA modules, 2 QSPI Ctrl modules, and 6 Flash particles. As shown in FIG. 7, the multiple time lines for writing data NAND FLASH are shown in FIG. 7, the CPU transfers the data A in the RAM to the fifo of QSPI Ctrl0 after configuring the DMA0 related register, the configuration FLASH CHANNEL SELECT register is switched to Flash0, the CPU transfers the data B in the RAM to the fifo of QSPI Ctrl0 after configuring the DMA0 related register again, the configuration FLASH CHANNEL SELECT register is switched to Flash1, the CPU transfers the data C in the RAM to the fifo of QSPI Ctrl0 after configuring the DMA0 related register again, the configuration FLASH CHANNEL SELECT register is switched to Flash2, and the CPU configures the register of QSPI Ctrl 0.
In fig. 7, after the CPU finishes configuring the DMA0 related register for the first time, as shown in fig. 8, the CPU starts configuring the DMA1 related register, then transfers the data D in the RAM to the fifo of the QSPI Ctrl1, the configuration FLASH CHANNEL SELECT register is switched to Flash3, after the CPU configures the register of the QSPI Ctrl1, the CPU again configures the DMA1 related register, then transfers the data E in the RAM to the fifo of the QSPI Ctrl1, the configuration FLASH CHANNEL SELECT register is switched to Flash4, after the CPU configures the register of the QSPI Ctrl1, the CPU again configures the DMA1 related register, then transfers the data F in the RAM to the fifo of the QSPI Ctrl1, the configuration FLASH CHANNEL SELECT register is switched to Flash5, and the CPU configures the register of the QSPI Ctrl 1.
As described above, wherein DMA0, QSPI Ctrl0 is responsible for handling data in RAM to Flash0, flash1, flash2; DMA1, QSPI Ctrl1 is responsible for handling data in RAM to Flash3, flash4, flash5. The ping-pong writing mode through the QSPI interface reduces the time consumed by the CPU for waiting for a plurality of Flash in the program stage (320 us/2 kB), thereby improving the writing speed of a plurality of NAND FLASH.
The embodiment also provides a data writing device, which is used for implementing the above embodiment and the preferred implementation, and is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.
The present embodiment provides a data writing apparatus, as shown in fig. 9, including:
A first obtaining module 401, configured to obtain current data to be written, and determine a current target memory in which the current data to be written is written;
A transmission module 402, configured to transmit, using a hardware data transmission channel, data to be written currently to a write-write space of a current target memory;
a sending module 403, configured to send an operation instruction to a current target memory, so that the current target memory writes the current data to be written into an internal storage space corresponding to the current target memory from a write-out space;
a second obtaining module 404, configured to obtain, after sending an operation instruction to the current target memory, next data to be written after the current data to be written; and cycling the steps until the data to be written is completely written.
In some optional embodiments, the first obtaining module 401 is specifically configured to obtain a current state corresponding to each memory; and determining the memory in the idle state as the current target memory for writing the current data to be written according to the current state of each memory.
In some optional embodiments, the transmission module 402 is specifically configured to obtain a source address and a destination address corresponding to the data to be written currently; the source address is the address of the current storage device corresponding to the current data to be written; the destination address is the address of the current target memory; acquiring the data length corresponding to the current data to be written; configuring a hardware data transmission channel according to the source address, the destination address and the data length; and transmitting the current data to be written into the writing-in and writing-out space of the current target memory by using the configured hardware data transmission channel.
In some optional embodiments, the transmission module 402 is specifically configured to calculate, using a preset data verification method, first verification data corresponding to data to be written currently; and transmitting the current data to be written and the first check data to a writing-out space of the current target memory by using the configured hardware data transmission channel.
In some optional embodiments, the transmission module 402 is specifically configured to obtain, in the write-write space, data to be written currently; calculating second check data corresponding to the current data to be written by using a preset data check method again; comparing the first check data with the second check data; when the first check data and the second check data are the same, determining that the current data to be written in the writing-out space is accurate; when the first check data and the second check data are different, the fact that the current data to be written in the writing-out space are inaccurate is determined, an abnormal interrupt signal is generated, and the abnormal interrupt signal is output to a user.
In some optional embodiments, the sending module 403 is specifically configured to receive a transport completion instruction transmitted by the hardware data transmission channel after the hardware data transmission channel transmits the data to be written currently to the write-out space; after receiving the transport completion instruction, acquiring configuration information corresponding to a target bus protocol; configuring a target bus protocol according to the configuration information; based on a target bus protocol, sending an operation instruction to a current target memory; the operation instruction comprises current data to be written in and a writing address for writing the current data to be written in the current target memory; the write address is used to characterize the row address and column address of the current data to be written in the current target memory.
In some optional embodiments, the sending module 403 is specifically configured to query a state machine corresponding to the current target memory; if the state machine represents that the current target memory is in a working state, determining that the operation instruction is successfully sent; if the state machine represents that the current target memory is in an idle state, determining that the operation instruction is not sent successfully; if the operation instruction is not successfully sent, sending the operation instruction to the current target memory again; until the operation instruction is successfully sent; correspondingly, the second obtaining module 404 is specifically configured to obtain, after the operation instruction is sent successfully, the next data to be written after the current data to be written.
The data writing means in this embodiment are presented in the form of functional units, here referred to as ASIC circuits, processors and memories executing one or more software or firmware programs, and/or other devices that can provide the above described functionality.
Further functional descriptions of the above respective modules and units are the same as those of the above corresponding embodiments, and are not repeated here.
The embodiment of the invention also provides electronic equipment, which is provided with the data writing device shown in the figure 9.
Referring to fig. 10, fig. 10 is a schematic structural diagram of an electronic device according to an alternative embodiment of the present invention, as shown in fig. 10, the electronic device includes: one or more processors 10, memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the electronic device, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display device coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple electronic devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 10 is illustrated in fig. 10.
The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.
Wherein the memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform a method for implementing the embodiments described above.
The memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created from the use of the electronic device of the presentation of one applet landing page, and the like. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 20 may optionally include memory located remotely from processor 10, which may be connected to the electronic device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.
Memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; the memory 20 may also comprise a combination of the above types of memories.
The electronic device further comprises input means 30 and output means 40. The processor 10, memory 20, input device 30, and output device 40 may be connected by a bus or other means, for example in fig. 10.
The input device 30 may receive input numeric or character information and generate key signal inputs related to user settings and function control of the electronic device, such as a touch screen, keypad, mouse, trackpad, touchpad, pointer stick, one or more mouse buttons, trackball, joystick, and the like. The output means 40 may include a display device, auxiliary lighting means (e.g., LEDs), tactile feedback means (e.g., vibration motors), and the like. Such display devices include, but are not limited to, liquid crystal displays, light emitting diodes, displays and plasma displays. In some alternative implementations, the display device may be a touch screen.
The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.
Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.
Claims (10)
1. A method of writing data, the method comprising:
acquiring current data to be written, and determining a current target memory for writing the current data to be written;
transmitting the current data to be written to a writing-in and writing-out space of the current target memory by utilizing a hardware data transmission channel;
Sending an operation instruction to the current target memory so that the current target memory writes the current data to be written into the internal storage space corresponding to the current target memory from the writing-out space;
After an operation instruction is sent to the current target memory, acquiring the next data to be written after the current data to be written; and cycling the steps until the data to be written is completely written.
2. The method of claim 1, wherein the determining the current target memory to which the current data to be written is written comprises:
Acquiring the current state corresponding to each memory;
and determining the memory in an idle state as the current target memory to which the current data to be written is written according to the current state of each memory.
3. The method of claim 1, wherein transferring the current data to be written to the write-write space of the current target memory using a hardware data transfer channel comprises:
Acquiring a source address and a destination address corresponding to the current data to be written; the source address is the address of the current storage device corresponding to the current data to be written; the destination address is the address of the current target memory;
acquiring the data length corresponding to the current data to be written;
Configuring the hardware data transmission channel according to the source address, the destination address and the data length;
And transmitting the current data to be written to the writing-out space of the current target memory by using the configured hardware data transmission channel.
4. The method according to claim 3, wherein the transferring the current data to be written to the write-write space of the current target memory using the configured hardware data transfer channel includes:
calculating first check data corresponding to the current data to be written by using a preset data check method;
And transmitting the current data to be written and the first check data to the writing-out space of the current target memory by using the configured hardware data transmission channel.
5. The method according to claim 4, wherein the method further comprises:
acquiring the current data to be written in the writing-out space;
calculating second check data corresponding to the current data to be written by using the preset data check method again;
comparing the first check data with the second check data;
When the first check data and the second check data are the same, determining that the current data to be written in the writing-out space is accurate;
When the first check data and the second check data are different, determining that the current data to be written in the writing-out space is inaccurate, generating an abnormal interrupt signal, and outputting the abnormal interrupt signal to a user.
6. The method of claim 1, wherein the sending an operation instruction to the current target memory comprises:
After the hardware data transmission channel transmits the current data to be written to the writing-out space, receiving a transportation completion instruction transmitted by the hardware data transmission channel;
After receiving the transport completion instruction, acquiring configuration information corresponding to a target bus protocol;
configuring the target bus protocol according to the configuration information;
Transmitting an operation instruction to the current target memory based on the target bus protocol; the operation instruction comprises the current data to be written and a writing address for writing the current data to be written into the current target memory; the write address is used to characterize a row address and a column address of the current data to be written in the current target memory.
7. The method of claim 6, wherein after the sending an operation instruction to the current target memory based on the target bus protocol, the method further comprises:
inquiring a state machine corresponding to the current target memory;
if the state machine characterizes the current target memory as being in a working state, determining that the operation instruction is successfully sent;
if the state machine characterizes the current target memory to be in an idle state, determining that the operation instruction is not successfully sent;
if the operation instruction is not successfully sent, sending the operation instruction to the current target memory again;
Until the operation instruction is successfully sent;
Correspondingly, after the operation instruction is sent to the current target memory, acquiring the next data to be written after the current data to be written includes:
And after the operation instruction is successfully sent, acquiring the next data to be written after the current data to be written.
8. A data writing apparatus, the apparatus comprising:
The first acquisition module is used for acquiring current data to be written in and determining a current target memory for writing the current data to be written in;
the transmission module is used for transmitting the current data to be written to a writing-out space of the current target memory by utilizing a hardware data transmission channel;
the sending module is used for sending an operation instruction to the current target memory so that the current target memory writes the current data to be written into the internal storage space corresponding to the current target memory from the writing-out and writing-out space;
the second acquisition module is used for acquiring the next data to be written after the current data to be written after sending an operation instruction to the current target memory; and cycling the steps until the data to be written is completely written.
9. An electronic device, comprising:
a memory and a processor, the memory and the processor being communicatively connected to each other, the memory having stored therein computer instructions, the processor executing the computer instructions to perform the data writing method of any of claims 1 to 7.
10. A computer-readable storage medium having stored thereon computer instructions for causing a computer to perform the data writing method of any of claims 1 to 7.
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