CN110888588B - Flash memory controller and related access method and electronic device - Google Patents
Flash memory controller and related access method and electronic device Download PDFInfo
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- CN110888588B CN110888588B CN201811043980.8A CN201811043980A CN110888588B CN 110888588 B CN110888588 B CN 110888588B CN 201811043980 A CN201811043980 A CN 201811043980A CN 110888588 B CN110888588 B CN 110888588B
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- mapping table
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
Abstract
The present invention discloses a flash memory controller, which comprises an artificial intelligence module and a microprocessor. In the operation of the flash memory controller, the artificial intelligence module is used for receiving a read command from a main device and generating an auxiliary command according to the read command; and the microprocessor is used for referencing a first logic address to physical address mapping table according to a logic address contained in the read command so as to read data from a flash memory module; and the microprocessor reads a second logic address to physical address mapping table from the flash memory module according to the auxiliary command, wherein the second logic address to physical address mapping table does not contain the logic address contained in the read command.
Description
Technical Field
The invention relates to a flash memory controller.
Background
In the current flash memory controller, when a read command from a host device is received, a logic address to physical address mapping table (hereinafter referred to as L2P mapping table) is required to convert a logic address in the read command into a physical address, so that the required data can be read from a flash memory module according to the physical address and returned to the host device. However, as the capacity of the flash memory module increases, a plurality of L2P mapping tables are required for implementation, and as the capacity of the buffer memory in the flash memory controller may not be enough to temporarily store all L2P mapping tables, the L2P mapping tables that are temporarily not needed are stored in the flash memory module to avoid occupying the space of the buffer memory.
However, since most of the L2P mapping table is stored in the flash memory module and is read from the flash memory module and temporarily stored in the buffer memory of the flash memory controller when the flash memory module is needed, the process of reading the required L2P mapping table from the flash memory module can slow down the reading speed, thereby affecting the performance of the whole system.
Disclosure of Invention
One of the objectives of the present invention is to provide a flash memory controller, which predicts which L2P mapping table will be used next according to the current read command, and reads the L2P mapping table from the flash memory module in advance and stores it in the buffer memory in the flash memory controller, so as to process it quickly when the related read command is received subsequently, thereby improving the overall system performance.
In one embodiment of the present invention, a flash memory controller is disclosed, which includes an artificial intelligence module and a microprocessor. In the operation of the flash memory controller, the artificial intelligence module is used for receiving a read command from a main device and generating an auxiliary command according to the read command; and the microprocessor is used for referencing a first logic address to physical address mapping table according to a logic address contained in the read command so as to read data from a flash memory module; and the microprocessor reads a second logic address to physical address mapping table from the flash memory module according to the auxiliary command, wherein the second logic address to physical address mapping table does not contain the logic address contained in the read command.
In another embodiment of the present invention, a method for accessing a flash memory module is disclosed, comprising the steps of: receiving a read command from a host device; generating an auxiliary command according to the read command; reading a data from a flash memory module according to a logical address contained in the read command and referring to a first logical address-to-physical address mapping table; and reading a second logical address to physical address mapping table from the flash memory module according to the auxiliary command, wherein the second logical address to physical address mapping table does not contain the logical address contained in the read command.
In another embodiment of the present invention, an electronic device is disclosed, which comprises a flash memory module and a flash memory controller, wherein the flash memory controller comprises an artificial intelligence module and a microprocessor. In the operation of the flash memory controller, the artificial intelligence module is used for receiving a read command from a main device and generating an auxiliary command according to the read command; and the microprocessor is used for referencing a first logic address to physical address mapping table according to a logic address contained in the read command so as to read data from a flash memory module; and the microprocessor reads a second logic address to physical address mapping table from the flash memory module according to the auxiliary command, wherein the second logic address to physical address mapping table does not contain the logic address contained in the read command.
Drawings
Fig. 1 is a schematic diagram of an electronic device according to an embodiment of the invention.
FIG. 2 is a diagram illustrating a plurality of L2P mapping tables stored in a flash memory module according to an embodiment of the invention.
FIG. 3 is a diagram illustrating a read sequence of a plurality of read commands and an L2P mapping table.
FIG. 4 is a flow chart of a method for accessing a flash memory module according to an embodiment of the invention.
Symbol description:
100. electronic device
110. Main device
120. Flash memory controller
121. Interface circuit
122. Artificial intelligence module
124. Microprocessor
126. Buffer memory
128. Read only memory
129. Control logic
130. Flash memory module
210_1 to 210_3 logical address to physical address mapping tables
Steps 400 to 408
LBA_0 to LBA_3071 logical addresses
Detailed Description
Fig. 1 is a schematic diagram of an electronic device 100 according to an embodiment of the invention. As shown in FIG. 1, the electronic device 100 comprises a host device 110, a flash memory controller 120 and a flash memory module 130, wherein the flash memory controller 120 comprises an interface circuit 121, an artificial intelligence module 122, a microprocessor 124, a buffer memory 126, a read only memory 128 and a control logic 129. The ROM 213 is used to store a plurality of codes, and the microprocessor 122 is used to execute the codes to control the access to the flash memory module 130, and the devices in the flash memory controller 120 can transfer data through the bus of the figure. In this embodiment, the flash memory controller 120 and the flash memory module 130 can be regarded as a Solid-state drive (SSD), the electronic device 100 can be any computer or server with a Solid-state drive, and the host device 110 can be a processor for accessing the flash memory module 130 through the flash memory controller 120.
The flash memory module 130 includes at least one flash memory chip, each of which includes a plurality of blocks (blocks) and each of which includes a plurality of pages (pages). In the related design of flash memory, each block is a minimum erase unit, i.e., all data in the block is erased together and cannot be erased only in a portion, and each page is a minimum write unit.
A portion of the flash memory module 130 may be used to store a plurality of logical-to-physical address mapping tables (L2P mapping tables), wherein each L2P mapping table includes a plurality of consecutive logical addresses and/or corresponding physical addresses, and each physical address may be a block number in the flash memory module 130 and a page number in the block. FIG. 2 is a schematic diagram of a plurality of L2P mapping tables 210_1 to 210_3 stored in the flash memory module 130 according to an embodiment of the invention, wherein the L2P mapping table 210_1 comprises logical addresses LBA_0 to LBA_1023 and corresponding physical addresses, the L2P mapping table 210_2 comprises logical addresses LBA_1024 to LBA_2047 and corresponding physical addresses, and the L2P mapping table 210_3 comprises logical addresses LBA_2048 to LBA_3071 and corresponding physical addresses. It should be noted that the L2P mapping tables 210_1 to 210_3 shown in fig. 2 are only exemplary, and are not limiting, for example, the number of consecutive logical addresses included in each L2P mapping table may be different, and not every logical address has a physical address (i.e., some logical addresses do not have a corresponding physical address or their corresponding physical addresses are invalid).
The artificial intelligence module 122 has a separate circuit architecture that can continuously receive and analyze successive read commands to create/update a plurality of decision logic for subsequent use. In this embodiment, the plurality of judging logic in the artificial intelligence module 122 is used to judge or predict the sequence relationship between the read commands from the host device 110, especially the sequence relationship of the logic addresses contained in the plurality of read commands, and the sequence relationship of the L2P mapping table corresponding to the logic addresses contained in the plurality of read commands, so as to judge/predict which read command will be issued by the host device 110 after receiving one read command from the host device 110, so as to perform the priority processing in the flash memory controller 120 in advance to read the required L2P mapping table from the flash memory module 130 in advance. Specifically, the artificial intelligence module 122 continuously receives the read command from the host device 110 while the electronic device 100 is operating, and generates a plurality of judging logics for judging the sequence relationship of the read command by recording and learning training, for example, if the artificial intelligence module 122 receives the read command for reading the data with the logical address LBA_123 from the host device 110 and then receives the read command for reading the data with the logical address LBA_2500 after receiving the read command for reading the data with the logical address LBA_123 from the host device 110, the artificial intelligence module 122 can judge that the data with the logical addresses LBA_123 and LBA_2500 are continuously requested to be read by the host device 110, so that the artificial intelligence module 122 can establish the judging logics that the logical address LBA_2500 is the immediately following the logical address LBA_123. In the present embodiment, since the logical address LBA_123 is included in the L2P mapping table 210_1 and the logical address LBA_2500 is included in the L2P mapping table 210_3, the artificial intelligence module 122 can establish that the L2P mapping table 210_3 needs to be the judgment logic immediately following the L2P mapping table 210_1. Therefore, after the artificial intelligence module 122 receives the read command from the host device 110 requesting to read the logical address LBA_123, the artificial intelligence module 122 can determine that the host device 110 is likely to issue the read command with the logical address LBA_2500 immediately after that, and the read command needs to be used in the L2P mapping table 210_3, so that the microprocessor 124 can be notified to perform some preprocessing.
In one embodiment, the decision logic trained by the artificial intelligence module 122 is used to describe the L2P mapping table sequence that the flash memory controller 120 needs to read from the flash memory module 130. For example, referring to fig. 3, assuming that the artificial intelligence module 122 sequentially receives a plurality of read commands with logical addresses lba_123, lba_2500, lba_300, lba_301, lba_130, lba_302, and since the L2P mapping tables corresponding to the logical addresses are 210_1, 210_3, 210_1, 210_2, 210_1, respectively, the artificial intelligence module 122 can determine that the order of the L2P mapping tables that the flash memory controller 120 needs to read from the flash memory module 130 is 210_1, 210_3, 210_2, the order of the L2P mapping tables can be used to build/update the internal determination logic.
In one embodiment of the present invention, considering the capability and efficiency of the artificial intelligence module 122, the artificial intelligence module 122 may be configured to generate/update the plurality of decision logics by receiving a plurality of specific read commands from the host device only during at least one specific period of time when the electronic device 100 performs at least one specific operation. For example, since the user is most careful about the power-on time of the electronic device 100 and the power-on time of opening certain specific software/applications, the user can set the artificial intelligence module 122 through the user interface of the electronic device 100 to train only when the electronic device 100 is powered on or when certain specific software/applications are executed to generate/update the plurality of judgment logics, while other time artificial intelligence modules 122 do not train to generate/update the plurality of judgment logics. Specifically, by user setting, the artificial intelligence module 122 can train within 7 seconds after each power-on of the electronic device 100 to generate/update the plurality of judgment logics, and since the files to be read by each power-on of the electronic device 100 have great similarity, the artificial intelligence module 122 can accurately and effectively train the plurality of judgment logics by training the electronic device 100 for a plurality of times; in addition, since the plurality of judgment logics in the artificial intelligence module 122 are not updated after 7 seconds of the power-on of the electronic device 100, the influence of the disordered read command on the plurality of judgment logics during the subsequent operation of the electronic device 100 on the correctness thereof can be avoided. In another example, by user setting, the artificial intelligence module 122 can train within 4 seconds of each start of executing a specific application program in the electronic device 100 to generate/update the plurality of judgment logics, so that the artificial intelligence module 122 can accurately and efficiently train the plurality of judgment logics; in addition, since the plurality of judgment logics in the artificial intelligence module 122 are not updated after 4 seconds from the start of executing the specific application program, the influence of the disordered read command on the plurality of judgment logics during the operation of the subsequent electronic device 100 on the correctness thereof can be avoided.
In this embodiment, the user can stop training of the artificial intelligence module 122, i.e. stop updating the plurality of judgment logics, at any time through the user interface of the electronic device 100. For example, assuming that the artificial intelligence module 122 has undergone ten power-up processes of the electronic device 100 to update the plurality of judgment logics, the artificial intelligence module 122 can stop training to reduce the system load, since the plurality of judgment logics should be enough to reflect the order of the read commands of the host device 110 or the order of the requirements of the L2P mapping table when the electronic device 100 is powered up.
In the overall operation of the electronic device 100, when the flash memory controller 120 receives a read command from the host 110, the artificial intelligence module 122 analyzes the logical address (i.e., the logical address corresponding to the data requested to be read by the read command) and/or a corresponding L2P mapping table included in the read command, and determines an auxiliary command through the plurality of determination logic therein, wherein the auxiliary command includes another L2P mapping table associated with the L2P mapping table required by the artificial intelligence module 122 to succeed the L2P mapping table during the previous training. For example, if the previous artificial intelligence module 122 establishes that the logical address LBA_2500 is the judgment logic immediately following the logical address LBA_123 or that the L2P mapping table 210_3 is the judgment logic immediately following the L2P mapping table 210_1, the auxiliary command includes the L2P mapping table 210_3 when the read command received by the flash memory controller 120 includes the logical address LBA_123.
Next, the microprocessor 124 determines the corresponding L2P mapping table according to the logical address included in the read command. If the corresponding L2P mapping table already exists in the buffer memory 126, the microprocessor 124 can directly refer to the L2P mapping table to determine a physical address of the flash memory module 130; if the corresponding L2P mapping table does not exist in the buffer memory 126, the microprocessor 124 reads the corresponding L2P mapping table from the flash memory module 130, and the microprocessor 124 refers to the read L2P mapping table to determine a physical address of the flash memory module 130. Then, the flash memory controller 120 reads a data from the physical address and immediately returns the data to the host device. Additionally, if the flash memory controller 120 and the flash memory module have free time, the microprocessor 124 reads the L2P mapping table included in the auxiliary command from the flash memory module 130 according to the L2P mapping table included in the auxiliary command (if the L2P mapping table already exists in the buffer memory 126, it is not necessary to read the L2P mapping table). It should be noted that, at this time, the flash memory controller 120 has not yet received the next command of the read command, and the flash memory controller 120 does not need to use the L2P mapping table contained in the auxiliary command at present, and the L2P mapping table contained in the auxiliary command does not contain the logical address contained in the read command received at present. In other words, the microprocessor 124 does not receive any read command that needs to use the L2P mapping table included in the auxiliary command within the time frame that the microprocessor 124 receives the read command and the microprocessor 124 reads the L2P mapping table included in the auxiliary command from the flash memory module 130.
For example, assuming that the read command includes the logical address LBA_123 and the auxiliary command includes the L2P mapping table 210_3, the flash memory controller 120 immediately reads the L2P mapping table 210_1 corresponding to the logical address LBA_123 from the flash memory module 130 (in the case that the buffer memory 126 does not include the L2P mapping table 210_1), and refers to the L2P mapping table 210_1 to determine a physical address corresponding to the logical address LBA_123, and reads data from the flash memory module 130 according to the physical address and returns the data to the host device. Then, the flash memory controller 120 reads the L2P mapping table 210_3 from the flash memory module 130 in advance and stores it in the buffer memory 126.
Then, if the flash memory controller 120 subsequently receives another read command including the logical address LBA_2500, since the required L2P mapping table 210_3 is already stored in the buffer memory 126, the flash memory controller 120 does not need to read the L2P mapping table 210_3 from the flash memory module 130, but can directly refer to the L2P mapping table 210_3 stored in the buffer memory module 126 to determine a physical address corresponding to the logical address LBA_2500, and then read data from the flash memory module 130 according to the physical address and transmit the data back to the host device. As described above, since the time for reading the L2P mapping table 210_3 is omitted, the speed of processing the other read command can be increased, and the performance of the electronic device 100 can be improved.
On the other hand, if the flash memory controller 120 does not receive the read command to use the L2P mapping table 210_3 within a period of time, the flash memory controller 120 may restore the L2P mapping table 210_3 from the buffer memory 126 to the flash memory module 130 at an appropriate timing point to release the memory space.
FIG. 4 is a flowchart of a method for accessing the flash memory module 130 according to an embodiment of the invention. Referring to fig. 1-3 and the disclosure thereof, the flow is as follows.
Step 400: the flow starts.
Step 402: a read command is received from a host device.
Step 404: generating an auxiliary command according to the read command.
Step 406: according to a logic address included in the read command and referring to a first logic address to physical address mapping table, a data is read from a flash memory module.
Step 408: reading a second logical address to physical address mapping table from the flash memory module according to the auxiliary command, wherein the second logical address to physical address mapping table does not contain the logical address contained in the read command.
Briefly summarized, the flash memory controller of the present invention includes an artificial intelligence module for predicting the L2P mapping table to be used later, and reads the predicted L2P mapping table from the flash memory module in advance and stores it in a buffer memory with a faster access speed, so as to quickly transmit back to the host device when receiving the related read command later. By the invention, the data reading speed can be accelerated and the system efficiency can be improved.
The foregoing description is only of the preferred embodiments of the invention, and all changes and modifications that come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein.
Claims (9)
1. A flash memory controller includes:
an artificial intelligent module for receiving a read command from a main device of an electronic device and generating an auxiliary command according to the read command; and
a microprocessor coupled to the artificial intelligence module for reading a data from a flash memory module according to a logical address included in the read command and referring to a first logical address-to-physical address mapping table (logical address to physical address mapping table); and the microprocessor reads a second logical address to physical address mapping table from the flash memory module according to the auxiliary command, wherein the second logical address to physical address mapping table does not contain the logical address contained in the read command,
wherein, before receiving the read command from the host device, the artificial intelligent module is configured to receive a plurality of specific read commands related to the read command from the host device only at least one specific time period when the electronic device performs at least one specific operation, so as to generate/update a judgment logic, and the artificial intelligent module generates the auxiliary command according to the judgment logic and the read command.
2. The flash memory controller of claim 1, wherein at the point in time when the microprocessor reads the second logical address to physical address mapping table from the flash memory module, the microprocessor does not receive any read command that requires use of the second logical address to physical address mapping table.
3. The flash memory controller of claim 1, wherein the microprocessor does not receive any read command that requires use of the second logical address to physical address mapping table within a time frame that the microprocessor receives the read command and the microprocessor reads the second logical address to physical address mapping table from the flash memory module.
4. The flash memory controller of claim 1, wherein the microprocessor reads the first logical address to physical address mapping table from the flash memory module according to the logical address included in the read command and references the first logical address to physical address mapping table to read the data from the flash memory module.
5. The flash memory controller of claim 1, wherein the plurality of specific read commands comprises at least one first read command and at least one second read command, the at least one first read command and the read command comprising the same logical address, and the at least one second read command is subsequent to the at least one first read command at a point in time of receipt.
6. The flash memory controller of claim 1, wherein the artificial intelligence module is configured to receive a plurality of specific read commands associated with the read command from the host device a plurality of times according to a user setting to generate/update the determination logic.
7. The flash memory controller of claim 6, wherein the flash memory controller is used in an electronic device, the user setting is at least one specific time period when at least one specific operation is performed for the electronic device, and the artificial intelligence module receives a plurality of specific read commands related to the read commands from the host device only during the at least one specific time period to generate/update the determination logic.
8. A method for accessing a flash memory module includes:
receiving a read command from a host device of an electronic device;
the artificial intelligent module generates an auxiliary command according to the read command;
reading a data from a flash memory module according to a logical address contained in the read command and referring to a first logical address-to-physical address mapping table (logical address to physical address mapping table); and
reading a second logical address to physical address mapping table from the flash memory module according to the auxiliary command, wherein the second logical address to physical address mapping table does not contain the logical address contained in the read command,
wherein, before receiving the read command from the host device, the artificial intelligent module is configured to receive a plurality of specific read commands related to the read command from the host device only at least one specific time period when the electronic device performs at least one specific operation, so as to generate/update a judgment logic, and the artificial intelligent module generates the auxiliary command according to the judgment logic and the read command.
9. An electronic device, comprising:
a flash memory module; and
a flash memory controller for accessing the flash memory module, comprising:
an artificial intelligent module for receiving a read command from a main device of an electronic device and generating an auxiliary command according to the read command; and
a microprocessor coupled to the artificial intelligence module for reading a data from a flash memory module according to a logical address included in the read command and referring to a first logical address-to-physical address mapping table (logical address to physical address mapping table); and the microprocessor reads a second logical address to physical address mapping table from the flash memory module according to the auxiliary command, wherein the second logical address to physical address mapping table does not contain the logical address contained in the read command,
wherein, before receiving the read command from the host device, the artificial intelligent module is configured to receive a plurality of specific read commands related to the read command from the host device only at least one specific time period when the electronic device performs at least one specific operation, so as to generate/update a judgment logic, and the artificial intelligent module generates the auxiliary command according to the judgment logic and the read command.
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| TWI629591B (en) * | 2017-08-30 | 2018-07-11 | 慧榮科技股份有限公司 | Method for accessing flash memory module and associated flash memory controller and electronic device |
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| TWI444825B (en) * | 2011-03-29 | 2014-07-11 | Phison Electronics Corp | Memory storage device, memory controller thereof, and method for programming data thereof |
| US10146448B2 (en) * | 2014-05-30 | 2018-12-04 | Sandisk Technologies Llc | Using history of I/O sequences to trigger cached read ahead in a non-volatile storage device |
| CN106547480B (en) * | 2015-09-17 | 2019-04-12 | 慧荣科技股份有限公司 | Data storage device and data reading method thereof |
| US10866897B2 (en) * | 2016-09-26 | 2020-12-15 | Samsung Electronics Co., Ltd. | Byte-addressable flash-based memory module with prefetch mode that is adjusted based on feedback from prefetch accuracy that is calculated by comparing first decoded address and second decoded address, where the first decoded address is sent to memory controller, and the second decoded address is sent to prefetch buffer |
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| TW201719415A (en) * | 2015-11-17 | 2017-06-01 | 群聯電子股份有限公司 | Buffer memory management method, memory control circuit unit and memory storage device |
| TWI629591B (en) * | 2017-08-30 | 2018-07-11 | 慧榮科技股份有限公司 | Method for accessing flash memory module and associated flash memory controller and electronic device |
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