CN110888588A - Flash memory controller and related access method and electronic device - Google Patents
Flash memory controller and related access method and electronic device Download PDFInfo
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- CN110888588A CN110888588A CN201811043980.8A CN201811043980A CN110888588A CN 110888588 A CN110888588 A CN 110888588A CN 201811043980 A CN201811043980 A CN 201811043980A CN 110888588 A CN110888588 A CN 110888588A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0638—Organizing or formatting or addressing of data
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0658—Controller construction arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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Abstract
The present invention discloses a flash memory controller, which comprises an artificial intelligence module and a microprocessor. In the operation of the flash memory controller, the artificial intelligence module is used for receiving a read command from a main device and generating an auxiliary command according to the read command; and the microprocessor is used for reading data from a flash memory module by referring to a first logical address to physical address mapping table according to a logical address contained in the read command; and the microprocessor further reads a second logical address to physical address mapping table from the flash memory module according to the auxiliary command, wherein the second logical address to physical address mapping table does not include the logical address included in the read command.
Description
Technical Field
The invention relates to a flash memory controller.
Background
In the conventional flash memory controller, when a read command is received from the host device, a logical address in the read command is converted into a physical address according to an internal logical address-to-physical address mapping table (hereinafter referred to as L2P mapping table), so that the required data can be read from a flash memory module according to the physical address and sent back to the host device. However, as the capacity of the flash memory module increases, a plurality of L2P mapping tables are required in practice, and since the capacity of the buffer memory inside the flash memory controller may not be enough to store all L2P mapping tables, the L2P mapping table that is not needed for a while is stored in the flash memory module to avoid occupying the space of the buffer memory.
However, since most of the L2P mapping tables are stored in the flash memory module and are read from the flash memory module and temporarily stored in the buffer memory inside the flash memory controller when they need to be used, the reading speed of the required L2P mapping table from the flash memory module is slowed down, which affects the performance of the whole system.
Disclosure of Invention
It is therefore one of the objectives of the present invention to provide a flash memory controller, which can predict which L2P mapping table will be used next according to the current read command, and temporarily store the L2P mapping table in a buffer memory inside the flash memory controller after reading the mapping table from the flash memory module in advance, so as to quickly process the received read command and improve the performance of the whole system.
In one embodiment of the present invention, a flash memory controller is disclosed, which comprises an artificial intelligence module and a microprocessor. In the operation of the flash memory controller, the artificial intelligence module is used for receiving a read command from a main device and generating an auxiliary command according to the read command; and the microprocessor is used for reading data from a flash memory module by referring to a first logical address to physical address mapping table according to a logical address contained in the read command; and the microprocessor further reads a second logical address to physical address mapping table from the flash memory module according to the auxiliary command, wherein the second logical address to physical address mapping table does not include the logical address included in the read command.
In another embodiment of the present invention, a method for accessing a flash memory module is disclosed, which comprises the following steps: receiving a read command from a host device; generating an auxiliary command according to the read command; reading a data from a flash memory module according to a logical address included in the read command and referring to a first logical address to physical address mapping table; and reading a second logical address to physical address mapping table from the flash memory module according to the auxiliary command, wherein the second logical address to physical address mapping table does not include the logical address included in the read command.
In another embodiment of the present invention, an electronic device is disclosed, which comprises a flash memory module and a flash memory controller, wherein the flash memory controller comprises an artificial intelligence module and a microprocessor. In the operation of the flash memory controller, the artificial intelligence module is used for receiving a read command from a main device and generating an auxiliary command according to the read command; and the microprocessor is used for reading data from a flash memory module by referring to a first logical address to physical address mapping table according to a logical address contained in the read command; and the microprocessor further reads a second logical address to physical address mapping table from the flash memory module according to the auxiliary command, wherein the second logical address to physical address mapping table does not include the logical address included in the read command.
Drawings
Fig. 1 is a schematic diagram of an electronic device according to an embodiment of the invention.
FIG. 2 is a diagram illustrating L2P mapping tables stored in a flash memory module according to an embodiment of the invention.
FIG. 3 is a diagram illustrating a plurality of read commands and a read sequence of the L2P mapping table.
FIG. 4 is a flowchart illustrating a method for accessing a flash memory module according to an embodiment of the invention.
Description of the symbols:
100 electronic device
110 master device
120 flash memory controller
121 interface circuit
122 artificial intelligence module
124 microprocessor
126 buffer memory
128 read only memory
129 control logic
130 flash memory module
210_1 to 210_3 logical to physical address mapping tables
400 to 408 steps
LBA _0 to LBA _3071 logical addresses
Detailed Description
Fig. 1 is a schematic diagram of an electronic device 100 according to an embodiment of the invention. As shown in FIG. 1, the electronic device 100 includes a host device 110, a flash memory controller 120 and a flash memory module 130, wherein the flash memory controller 120 includes an interface circuit 121, an artificial intelligence module 122, a microprocessor 124, a buffer memory 126, a read only memory 128 and a control logic 129. The ROM 213 is used to store a plurality of program codes, and the microprocessor 122 is used to execute the program codes to control the access to the flash memory module 130, and the components in the flash memory controller 120 can perform data transmission through the bus shown in the figure. In the embodiment, the flash memory controller 120 and the flash memory module 130 can be regarded as a Solid-state drive (SSD), the electronic device 100 can be any computer or server with a Solid-state drive, and the host device 110 can be a processor for accessing the flash memory module 130 through the flash memory controller 120.
The flash memory module 130 comprises at least one flash memory chip, and each flash memory chip comprises a plurality of blocks (blocks), and each block comprises a plurality of pages (pages). In a related design of flash memory, each block is a minimum unit of erase, i.e. all data in the block is erased together and cannot be erased only a portion, and each page of data is a minimum unit of write.
A portion of the flash memory module 130 is used to store a plurality of logical address-to-physical address mapping tables (L2P mapping tables), wherein each L2P mapping table includes a plurality of consecutive logical addresses and/or their corresponding physical addresses, and each physical address is a serial number of a block and a data page serial number of the block in the flash memory module 130. FIG. 2 is a diagram illustrating a plurality of L2P mapping tables 210_1 to 210_3 stored in the flash memory module 130 according to an embodiment of the invention, in which the L2P mapping table 210_1 includes logical addresses LBA _0 to LBA _1023 and corresponding physical addresses, the L2P mapping table 210_2 includes logical addresses LBA _1024 to LBA _2047 and corresponding physical addresses, and the L2P mapping table 210_3 includes logical addresses LBA _2048 to LBA _3071 and corresponding physical addresses. It should be noted that the L2P mapping tables 210_1 to 210_3 shown in FIG. 2 are only an example and are not limiting, for example, each L2P mapping table may include different numbers of consecutive logical addresses, and not every logical address has a physical address (i.e., some logical addresses do not have corresponding physical addresses, or their corresponding physical addresses are invalid).
The artificial intelligence module 122 has an independent circuit structure, which can continuously receive and analyze the continuous read commands to establish/update a plurality of judgment logics for subsequent use. In the present embodiment, the plurality of determination logics in the artificial intelligence module 122 are used to determine or predict the sequence relationship between the read commands from the host device 110, particularly the sequence relationship between the logical addresses included in the plurality of read commands, and the sequence relationship of the L2P mapping tables corresponding to the logical addresses included in the plurality of read commands, so as to determine/predict which read command will be issued by the host device 110 after receiving a read command from the host device 110, so as to perform a priority process in the flash memory controller 120 in advance to read the required L2P mapping table from the flash memory module 130. Specifically, the artificial intelligence module 122 continuously receives the read command from the host device 110 during the operation of the electronic device 100, and generates a plurality of determination logics for determining the sequential relationship of the read command through recording and learning training, for example, if the artificial intelligence module 122 receives a read command requesting to read data with logical address LBA _123 and then receives a read command requesting to read data with logical address LBA _2500 after receiving a read command requesting to read data with logical address LBA _123 from the host device 110 many times, the artificial intelligence module 122 can determine that there is a high probability that data with logical addresses LBA _123 and LBA _2500 will be continuously requested to be read by the host device 110, so the artificial intelligence module 122 can establish the determination logic that logical address LBA _2500 is immediately after logical address LBA _ 123. In the present embodiment, since the logical address LBA _123 is contained in the L2P mapping table 210_1, and the logical address LBA _2500 is contained in the L2P mapping table 210_3, the artificial intelligence module 122 can establish the judgment logic that the requirement of the L2P mapping table 210_3 is immediately after the L2P mapping table 210_ 1. Therefore, after the artificial intelligence module 122 receives the read command with the logical address LBA _123 from the host device 110, the artificial intelligence module 122 can determine that the host device 110 is likely to issue the read command with the logical address LBA _2500 immediately before the L2P mapping table 210_3 is needed, so the microprocessor 124 can be notified for some pre-processing.
In one embodiment, the decision logic trained by the artificial intelligence module 122 is used to describe the sequence of L2P mapping tables that the flash memory controller 120 needs to read from the flash memory module 130. For example, referring to fig. 3, assuming that the artificial intelligence module 122 receives a plurality of read commands having logical addresses LBA _123, LBA _2500, LBA _300, LBA _301, LBA _130, and LBA _302 in sequence, since the L2P mapping tables corresponding to the logical addresses are 210_1, 210_3, 210_1, 210_2, and 210_1, respectively, the artificial intelligence module 122 can determine that the order of the L2P mapping tables that the flash memory controller 120 needs to read from the flash memory module 130 is 210_1, 210_3, and 210_2, and thus the order of the L2P mapping tables can be used to establish/update internal determination logic.
In one embodiment of the present invention, in consideration of the capability and efficiency of the artificial intelligence module 122, the artificial intelligence module 122 may be configured to generate/update the determination logics by receiving and reading specific read commands from the host device only during at least a specific period of time when the electronic device 100 performs at least a specific operation. For example, since the user most usually intends to start up the electronic device 100 and start up certain specific software/application programs, the user can set the artificial intelligence module 122 to train to generate/update the plurality of determination logics only when the electronic device 100 is started up or some specific software/application programs are executed through the user interface of the electronic device 100, and the artificial intelligence module 122 will not train to generate/update the plurality of determination logics at other times. Specifically, through the user setting, the artificial intelligence module 122 can be trained within 7 seconds after the electronic device 100 is powered on each time to generate/update the plurality of judgment logics, and because the files that the electronic device 100 needs to read during the power on each time have great similarity, the artificial intelligence module 122 can be trained accurately and efficiently through the training performed during the power on of the electronic device 100 for a plurality of times; in addition, since the determination logics in the artificial intelligence module 122 are not updated after 7 seconds of the electronic device 100 being turned on, it is avoided that the determination logics are interfered by a disordered read command during the subsequent operation of the electronic device 100 and the correctness thereof is affected. In another example, through user configuration, the artificial intelligence module 122 can train within 4 seconds of each time the electronic device 100 starts executing a specific application program to generate/update the plurality of determination logics, so that the artificial intelligence module 122 can accurately and efficiently complete the training of the plurality of determination logics; in addition, since the judgment logics in the artificial intelligence module 122 are not updated after 4 seconds when the specific application program starts to execute, it is able to avoid the disorder of the read command from interfering with the judgment logics during the subsequent operation of the electronic device 100 and affecting the correctness thereof.
In this embodiment, the user can stop the training of the artificial intelligence module 122 at any time through the user interface of the electronic device 100, i.e. stop updating the plurality of determination logics. For example, if the artificial intelligence module 122 has already undergone ten boot procedures of the electronic device 100 to update the plurality of determination logics, the artificial intelligence module 122 may stop training to reduce the system load because the plurality of determination logics should sufficiently reflect the sequence of the read commands of the host device 110 or the required sequence of the L2P mapping table when the electronic device 100 is booted.
In the overall operation of the electronic device 100, when the flash memory controller 120 receives a read command from the host device 110, the artificial intelligence module 122 analyzes the logical address included in the read command (i.e., the logical address corresponding to the data requested to be read by the read command) and/or the corresponding L2P mapping table, and determines an auxiliary command through the internal multiple determination logics, wherein the auxiliary command includes another L2P mapping table required by the artificial intelligence module 122 following the L2P mapping table during the previous training. For example, if the prior artificial intelligence module 122 establishes the logic for determining LBA _2500 immediately after LBA _123 or the requirement of mapping 210_3 of L2P immediately after the logic for determining mapping 210_1 of L2P, the auxiliary command includes the L2P mapping 210_3 when the read command received by the flash memory controller 120 includes the logic for determining LBA _ 123.
Then, the microprocessor 124 determines the corresponding L2P mapping table according to the logic address included in the read command. If the corresponding L2P mapping table already exists in the buffer memory 126, the microprocessor 124 can directly refer to the L2P mapping table to determine a physical address of the flash memory module 130; if the corresponding L2P mapping table does not exist in the buffer memory 126, the microprocessor 124 reads the corresponding L2P mapping table from the flash memory module 130, and the microprocessor 124 determines a physical address of the flash memory module 130 by referring to the read L2P mapping table. Then, the flash memory controller 120 reads a data from the physical address and immediately returns the data to the host device. In addition, if the flash controller 120 and the flash memory module have idle time next, the microprocessor 124 reads the L2P mapping table included in the auxiliary command from the flash memory module 130 according to the L2P mapping table included in the auxiliary command (which is not necessary if the L2P mapping table already exists in the buffer memory 126). It should be noted that, at this time, the flash controller 120 does not receive the next command of the read command, and the flash controller 120 does not need to use the L2P mapping table included in the auxiliary command, and the L2P mapping table included in the auxiliary command does not include the logical address included in the currently received read command. In other words, during the time period when the microprocessor 124 receives the read command and the microprocessor 124 reads the L2P mapping table included in the auxiliary command from the flash memory module 130, the microprocessor 124 does not receive any read command that needs to use the L2P mapping table included in the auxiliary command.
For example, assuming that the read command includes the logical address LBA _123 and the auxiliary command includes the L2P mapping table 210_3, the flash memory controller 120 will immediately read the L2P mapping table 210_1 corresponding to the logical address LBA _123 from the flash memory module 130 (in the case that the buffer memory 126 does not include the L2P mapping table 210_ 1), refer to the L2P mapping table 210_1 to determine a physical address corresponding to the logical address LBA _123, and read data from the flash memory module 130 according to the physical address and return the data to the host. Then, the flash controller 120 reads the L2P mapping table 210_3 from the flash memory module 130 in advance and stores it in the buffer memory 126.
Then, if the flash memory controller 120 subsequently receives another read command containing the logical address LBA _2500, since the required L2P mapping table 210_3 is already stored in the buffer memory 126, the flash memory controller 120 does not need to read the L2P mapping table 210_3 from the flash memory module 130, but can directly refer to the L2P mapping table 210_3 stored in the buffer memory 126 to determine a physical address corresponding to the logical address LBA _2500, and read data from the flash memory module 130 according to the physical address and return the data to the host. As described above, since the time for reading the L2P mapping table 210_3 is omitted, the speed of processing the other read command can be increased, and the performance of the electronic device 100 can be improved.
On the other hand, if the flash controller 120 does not receive a read command requiring the use of the L2P map 210_3 for a period of time, the flash controller 120 can restore the L2P map 210_3 from the buffer memory 126 to the flash memory module 130 at an appropriate timing to release the memory space.
FIG. 4 is a flowchart illustrating a method for accessing the flash memory module 130 according to an embodiment of the invention. Referring to fig. 1-3 and the disclosure thereof, the process is as follows.
Step 400: the process begins.
Step 402: a read command is received from a master device.
Step 404: an auxiliary command is generated according to the read command.
Step 406: reading a data from a flash memory module according to a logical address included in the read command and referring to a first logical address to physical address mapping table.
Step 408: reading a second logical address to physical address mapping table from the flash memory module according to the auxiliary command, wherein the second logical address to physical address mapping table does not include the logical address included in the read command.
Briefly summarized, the present invention includes an artificial intelligence module to predict the L2P mapping table to be used later, and the predicted L2P mapping table is read from the flash memory module in advance and stored in the buffer memory with faster access speed, so as to be able to be returned to the host device quickly when the relevant read command is received later. Through the present invention, the data reading speed can be accelerated and the system efficiency can be improved.
The above description is only a preferred embodiment of the present invention, and all equivalent changes and modifications made in accordance with the claims of the present invention should be covered by the present invention.
Claims (10)
1. A flash memory controller includes:
an artificial intelligence module for receiving a read command from a host device and generating an auxiliary command according to the read command; and
a microprocessor coupled to the artificial intelligence module for reading a data from a flash memory module according to a logical address included in the read command and referring to a first logical address to physical address mapping table (local address to physical address mapping table); and the microprocessor further reads a second logical address to physical address mapping table from the flash memory module according to the auxiliary command, wherein the second logical address to physical address mapping table does not include the logical address included in the read command.
2. The flash memory controller of claim 1, wherein at a point in time when the microprocessor reads the second logical address to physical address mapping table from the flash memory module, the microprocessor does not receive any read command that requires use of the second logical address to physical address mapping table.
3. The flash memory controller of claim 1, wherein the microprocessor does not receive any read command that requires use of the second logical to physical address mapping table within a time frame in which the microprocessor receives the read command and the microprocessor reads the second logical to physical address mapping table from the flash memory module.
4. The flash memory controller of claim 1, wherein the microprocessor reads the first logical address to physical address mapping table from the flash memory module according to the logical address included in the read command, and references the first logical address to physical address mapping table to read the data from the flash memory module.
5. The flash memory controller of claim 1, wherein the artificial intelligence module receives a plurality of specific read commands associated with the read command from the host device a plurality of times to generate/update a decision logic prior to receiving the read command from the host device; and the artificial intelligence module generates the auxiliary command according to the judgment logic and the reading command.
6. The flash memory controller of claim 5, wherein the plurality of specific read commands includes at least a first read command and at least a second read command, the at least a first read command and the read command include the same logical address, and the at least a second read command is subsequent to the at least a first read command at a time point of receipt.
7. The flash memory controller of claim 1, wherein the artificial intelligence module generates/updates the decision logic by receiving a plurality of specific read commands associated with the read command from the host device a plurality of times according to a user setting.
8. The flash memory controller of claim 7, wherein the flash memory controller is implemented in an electronic device, the user setting is at least a specific time period when the electronic device performs at least a specific operation, and the artificial intelligence module receives a plurality of specific read commands related to the read command from the host device only during the at least a specific time period to generate/update the determination logic.
9. A method for accessing a flash memory module includes:
receiving a read command from a host device;
generating an auxiliary command according to the read command;
reading a data from a flash memory module according to a logical address included in the read command and referring to a first logical address to physical address mapping table (local address to physical address mapping table); and
reading a second logical address to physical address mapping table from the flash memory module according to the auxiliary command, wherein the second logical address to physical address mapping table does not include the logical address included in the read command.
10. An electronic device, comprising:
a flash memory module; and
a flash memory controller for accessing the flash memory module, comprising:
an artificial intelligence module for receiving a read command from a host device and generating an auxiliary command according to the read command; and
a microprocessor coupled to the artificial intelligence module for reading a data from a flash memory module according to a logical address included in the read command and referring to a first logical address to physical address mapping table (local address to physical address mapping table); and the microprocessor further reads a second logical address to physical address mapping table from the flash memory module according to the auxiliary command, wherein the second logical address to physical address mapping table does not include the logical address included in the read command.
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