CN117894770A - Gallium nitride device with electric card refrigeration and heat dissipation enhancement functions and preparation method - Google Patents
Gallium nitride device with electric card refrigeration and heat dissipation enhancement functions and preparation method Download PDFInfo
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Abstract
The invention discloses a gallium nitride device with electric card refrigeration and enhanced heat dissipation, which mainly solves the problems that the existing GaN material is difficult to dissipate heat under high power and has serious self-heating phenomenon due to low heat conduction coefficient. The heat transfer interface layer, the electric card refrigerating layer, the substrate layer, the nucleation layer, the buffer layer, the channel layer, the barrier layer (1, 2,3,4,5,6,7, 8) and the metal electrode are arranged from bottom to top, and the passivation layer is wrapped on the periphery of the metal electrode; the upper and lower surfaces of the electric card refrigerating layer are respectively provided with an upper metal electrode layer (31, 32), one side from the surface of the upper metal electrode layer to the upper surface of the passivation layer is respectively provided with an upper electrode connecting through hole (10) and a lower electrode connecting through hole (11), and insulating materials and metal interconnection materials (12, 13) are filled in the through holes. The invention reduces the thermal resistance of the device, increases the heat transfer from the device substrate to the heat sink, improves the heat dissipation performance of the device, and can be used as a microwave power device and a power electronic device.
Description
Technical Field
The invention belongs to the technical field of semiconductor devices, and particularly relates to a GaN device and a preparation method thereof, which can be used as a microwave power device and a power electronic device.
Background
With the development of microelectronics, gaN devices have been widely used in various fields. Because the GaN material has high electron saturation drift velocity and electron mobility, the GaN device has high-efficiency power switching and large current processing capacity, so that the GaN material is excellent in high-power and high-frequency application, and an ideal solution is provided for a power amplifier, a radio-frequency power device and the like. The wide forbidden bandwidth and high breakdown field strength of the GaN material enable the GaN material to have excellent stability in a high-temperature environment, and the GaN material is suitable for extreme working conditions and is widely applied to the key fields of communication, energy sources, national defense and the like. In the future, with the continuous evolution of technology, the GaN device will continue to exert its advantages, providing strong support for innovation of electronic technology and expansion of application fields.
However, as device performance increases, power increases, heat flow increases, and electrical characteristics and long-term reliability tend to decrease due to severe self-heating effects present in the device. For GaN materials, the thermal resistance is high, the heat dissipation performance is poor, and the output power density and the efficiency of GaN devices are limited. Therefore, efficient thermal management techniques are needed to improve the electrical characteristics and reliability of the device.
Patent document with application number of CN20191036079. X discloses a GaN device based on a diamond substrate and a preparation method thereof, wherein the GaN device is epitaxially grown on the diamond substrate, so that diamond is in direct contact with GaN material, and the GaN device directly utilizes diamond with higher heat conductivity to dissipate heat. However, due to the fact that materials such as GaN materials and diamond have large lattice mismatch, the electrical performance of the device is affected.
Patent document CN202111149330.3 discloses a method for preparing a GaN-based diode device with a diamond passivation layer, which deposits a diamond passivation layer on the surface of the GaN diode to improve the heat dissipation performance of the device. However, the high thermal conductivity material directly grows on the surface of the device to bring additional stress, so that the electrical performance of the device is reduced, the reliability of the device is reduced, and the heat dissipation effect is poor.
Patent document CN202210051673.4 discloses a preparation method of HEMT based on ultra-thin GaN self-supporting substrate, which reduces heat transmission path and improves heat dissipation performance of device by thinning GaN substrate. However, the difficulty of the subsequent process is too great due to the fact that the substrate is too thin, the yield of devices is reduced, and meanwhile, the heat dissipation performance of the devices needs to be further improved.
Patent document CN202310485847.2 discloses a cooling integrated GaN module and a preparation method thereof, which etches a GaN device substrate to form a manifold type micro-channel, and the cooling liquid directly contacts with a device heat source to dissipate heat, so that the heat dissipation performance of the device is improved. But increases the energy consumption of the device due to the additional energy required for transportation of the cooling liquid.
Disclosure of Invention
Aiming at the defects of the prior art, the invention provides a GaN device with the electric card refrigeration and enhanced heat dissipation and a preparation method thereof, so as to avoid lattice mismatch and extra stress caused by direct contact of high-heat-conductivity materials and the GaN device, reduce the energy loss of the device and further improve the heat dissipation performance of the device.
The technical scheme for realizing the aim of the invention comprises the following steps:
1. The GaN device comprises a heat sink layer, a heat transfer interface layer, a substrate layer, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a metal electrode and a passivation layer which are wrapped on the periphery of the metal electrode from bottom to top, and is characterized in that:
an electric card refrigerating layer is arranged between the substrate layer and the heat transfer interface layer, and an upper metal electrode layer and a lower metal electrode layer are respectively arranged on the upper surface and the lower surface of the electric card refrigerating layer;
An upper electrode connecting through hole is formed on one side from the upper surface of the upper metal electrode layer to the upper surface of the passivation layer so as to lead out the upper metal electrode to the upper surface of the passivation layer;
A lower electrode connecting through hole is formed on one side from the upper surface of the lower metal electrode layer to the upper surface of the passivation layer so as to lead out the lower metal electrode to the upper surface of the passivation layer;
insulating materials and metal interconnection materials are arranged in the upper electrode connecting through hole and the lower electrode connecting through hole so as to realize electrical isolation between the upper metal electrode layer and the lower metal electrode layer and electrical connection between the upper metal electrode layer and the lower metal electrode layer and the through hole, and simultaneously play a role in enhancing heat dissipation.
Further, the heat sink layer is made of any one of copper alloy, aluminum alloy or high-heat-conductivity ceramic material, and the thickness of the heat sink layer is 0.1-5 mm, wherein the copper alloy comprises copper tungsten alloy and copper molybdenum alloy, and the aluminum alloy comprises aluminum-magnesium-silicon alloy and aluminum-silicon-carbon alloy;
the heat transfer interface layer adopts any one of heat conduction silica gel, heat conduction silicone grease or epoxy resin, and the thickness of the heat transfer interface layer is 0.5-5 mu m;
The electric card refrigerating layer adopts any one material with piezoelectric effect from barium titanate base piezoelectric ceramics, lead zirconate titanate piezoelectric film, polyvinylidene fluoride and copolymer thereof, and the thickness is 1-2000 mu m.
Further, the thickness of the upper metal electrode layer and the lower metal electrode layer is 0.2-2 μm, and the upper metal electrode layer and the lower metal electrode layer are formed by depositing metal Cu or metal Au or other high-heat-conductivity metals, and are used for applying voltage to the surface of the electric card refrigerating layer to form an electric field, so that the piezoelectric material is subjected to phase change, and the heat dissipation capacity of the device is improved.
Further, the substrate layer adopts Si or SiC, and the thickness of the substrate layer is 100-600 mu m;
the nucleation layer adopts AlN, and the thickness of the AlN is 150-250 nm;
The buffer layer adopts any one of GaN, alN or AlGaN, and the thickness of the buffer layer is 0.1-5 mu m;
the channel layer adopts GaN, and the thickness of the channel layer is 20-800 nm;
the barrier layer adopts AlGaN, and the thickness of the barrier layer is 10-30 nm.
Further, the passivation layer adopts SiO 2 or Si 3N4 insulating medium as electrical isolation, and the thickness of the passivation layer is 80-200 nm;
the upper electrode connecting through hole and the lower electrode connecting through hole are round holes or square holes, and the diameter of the upper electrode connecting through hole and the lower electrode connecting through hole is 5-100 mu m.
Further, the insulating materials in the upper electrode connecting through hole and the lower electrode connecting through hole adopt SiO 2, and the thickness of the insulating materials is 0.5-2 mu m;
The metal interconnection materials in the upper electrode connection through hole and the lower electrode connection through hole adopt Ti and Cu or Ti and Au, wherein Ti is used as a metal barrier layer.
2. The preparation method of the GaN device for enhancing heat dissipation by electric card refrigeration is characterized by comprising the following steps of:
s1: a nucleation layer, a buffer layer, a channel layer and a barrier layer are epitaxially deposited on the front surface of the substrate through metal organic chemical vapor deposition MOCVD in sequence;
S2: depositing electrode metal on the barrier layer by electron Beam evaporation E-Beam, then performing ion implantation isolation, and then depositing a passivation layer by atomic layer deposition ALD;
s3: connecting the upper surface of the passivation layer to an external carrier wafer through a bonding process;
s4: carrying out pretreatment of lapping thinning and surface polishing on the back surface of the substrate;
S5: etching an upper electrode connecting through hole from the back surface of the pretreated substrate to one side of the upper surface of the passivation layer, depositing an insulating material on the inner wall of the upper electrode connecting through hole by plasma enhanced chemical vapor deposition PECVD, sputtering a metal barrier layer and a metal seed layer, and finally electroplating metal to completely fill the upper electrode connecting through hole;
S6: depositing an upper metal electrode layer on the back of the pretreated substrate by electron Beam evaporation E-Beam, and manufacturing an electric card refrigerating layer on the lower surface of the upper metal electrode layer;
s7: etching a lower electrode connecting through hole from the back surface of the electric card refrigerating layer to one side of the upper surface of the passivation layer, depositing an insulating material on the inner wall of the lower electrode connecting through hole by plasma enhanced chemical vapor deposition PECVD, sputtering a metal barrier layer and a metal seed layer, electroplating metal to completely fill a second through hole, and finally depositing a lower metal electrode layer by electron Beam evaporation E-Beam;
s8: and bonding a heat sink material on the surface of the lower metal electrode layer through a heat transfer interface material, and removing the carrier wafer to finish the device manufacturing.
Compared with the prior art, the invention has the following advantages:
1) According to the invention, the electric card refrigerating layer is arranged between the substrate layer and the heat transfer interface layer, and the electric field is applied or withdrawn through the upper and lower metal electrode layers on the upper and lower surfaces of the electric card refrigerating layer, so that the piezoelectric material in the electric card refrigerating layer is subjected to phase change, the increase or decrease of the material temperature is realized, and the heat dissipation performance of the device is improved.
2) According to the invention, the through holes are formed in one side from the upper surfaces of the upper metal electrode layer and the lower metal electrode layer to the upper surface of the passivation layer, so that the upper metal electrode layer and the lower metal electrode layer are led out to the surface of the device, and meanwhile, the through holes are filled with high-heat-conductivity metal, so that the heat dissipation performance of the device is further improved.
3) Compared with the passive cooling technology using a high-heat-conductivity substrate or a high-heat-conductivity passivation layer, the electric card refrigeration technology used in the invention can better reduce the thermal resistance of the device, and meanwhile, the lattice mismatch and the extra stress caused by direct contact between the high-heat-conductivity material and the GaN device are avoided, so that the heat dissipation performance of the device is more excellent.
4) The electric card refrigeration technology only needs to apply a periodic electric field to the electric card refrigeration layer, so that compared with the micro-flow channel cooling technology, the energy consumed by transporting the coolant is reduced, and the energy loss is reduced.
5) According to the invention, the electric card refrigerating layer is directly and heterogeneously integrated on the back of the substrate, so that a shorter heat propagation path is realized, the overall heat dissipation efficiency of the device is improved, the device integration is facilitated, and the size and weight of equipment are reduced; meanwhile, as the electric card refrigerating layer is integrated on the substrate, the complexity of manufacturing the device is reduced, the reliability and stability of the device are improved, and the overall performance and flexibility are improved.
Drawings
FIG. 1 is a schematic illustration of a GaN HEMT structure with enhanced heat dissipation by electric card refrigeration;
FIG. 2 is a schematic diagram of a process flow for manufacturing a GaN device with electric card refrigeration and enhanced heat dissipation;
fig. 3 is a schematic diagram of a GaN SBD structure with enhanced cooling of an electric card manufactured in embodiment 3 of the present invention.
Detailed Description
The invention is described in further detail below with reference to the drawings and examples.
Referring to fig. 1, the inventive electronic card refrigeration enhanced heat dissipation GaN HEMT comprises a heat sink layer 1, a heat transfer interface layer 2, an electronic card refrigeration layer 3, a substrate layer 4, a nucleation layer 5, a buffer layer 6, a channel layer 7, a barrier layer 8, a passivation layer 9, and source S, drain D, and gate G. Wherein:
The substrate layer 4 adopts Si or SiC, and the thickness is 100-600 mu m.
The nucleation layer 5 is made of AlN and has a thickness of 150-250 nm, and is located above the substrate layer 4.
The buffer layer 6 is made of any one of GaN, alN or AlGaN, and has a thickness of 0.1-5 μm and is located above the nucleation layer 5.
The channel layer 7 is made of GaN, has a thickness of 20-800 nm, and is positioned above the buffer layer 6.
The barrier layer 8 is made of AlGaN, has a thickness of 10-30 nm, and is positioned above the channel layer 7.
The source electrode S and the drain electrode D are Ti/Al, the thickness is 20-60/80-160 nm, and the source electrode S and the drain electrode D are positioned on the barrier layer 8; the grid G adopts Ni/Al, the thickness is 20-60/60-200 nm, and the grid G is positioned between the source electrode S and the drain electrode D.
The passivation layer 9 is made of SiO 2 or Si 3N4, has a thickness of 80-200 nm, and is wrapped on the peripheries of the source electrode S, the drain electrode D and the grid electrode G.
The electric card refrigerating layer 3 is made of any one piezoelectric effect material selected from barium titanate-based piezoelectric ceramic, lead zirconate titanate piezoelectric film, polyvinylidene fluoride and copolymer thereof, and has a thickness of 1-2000 μm, and is positioned on the back surface of the substrate layer 4.
The upper and lower surfaces of the electric card refrigerating layer 3 are respectively provided with an upper metal electrode layer 31 and a lower metal electrode layer 32, the thickness of each of which is 0.2-2 mu m, and each of which is formed by depositing metal Cu or metal Au or other high-heat-conductivity metals.
An upper electrode connection through hole 10 is formed on one side from the upper surface of the upper metal electrode layer 31 to the upper surface of the passivation layer 9, a lower electrode connection through hole 11 parallel to the upper electrode connection through hole 10 is formed on one side from the upper surface of the lower metal electrode layer 32 to the upper surface of the passivation layer 9, and the two through holes are round holes or square holes with the diameter of 5-100 μm.
The upper electrode connecting through hole 10 and the lower electrode connecting through hole 11 are filled with an insulating material 12 and a metal interconnection material 13, wherein the insulating material 12 adopts SiO 2, and the filling thickness is 0.5-2 mu m; the metal interconnection material 13 is Ti and Cu or Ti and Au, which is located outside the insulating material 12 and completely fills the inner walls of the upper electrode connection via 10 and the lower electrode connection via 11.
The heat transfer interfacial layer 2 is made of any one of heat conductive silica gel, heat conductive silicone grease or epoxy resin, and has a thickness of 0.5-5 μm, and is located on the lower surface of the lower metal electrode layer 32.
The heat sink layer 1 is made of any one of copper alloy, aluminum alloy or high-heat-conductivity ceramic material, and has a thickness of 0.1-5 mm, and is positioned on the lower surface of the heat transfer interface layer 2.
Referring to fig. 2, the present invention is given as the following three examples, but embodiments of the present invention are not limited thereto. The experimental methods described in the following examples are all conventional methods unless otherwise specified; the reagents and materials, unless otherwise specified, are commercially available.
In the first embodiment, the manufacturing electric card refrigerating layer is polyvinylidene fluoride and copolymer thereof, the thickness is 20 mu m, the buffer layer is GaN, and the thickness is 1 mu m of GaN high electron mobility transistor HEMT.
Step 1: a group III nitride material is epitaxially deposited on the front side of Si substrate 4 as shown in fig. 2 (a).
1.1 Deposition of AlN nucleation layer 5:
selecting Si substrate with 6 inch size, 500 μm thickness and crystal orientation of [111 ];
An AlN nucleation layer 5 with the thickness of 200nm is epitaxially grown on the front surface of the Si substrate 4 under the process conditions that the flow rate ratio of NH 3 to TMAl is 1500, the temperature is 450 ℃ and the growth pressure is 100mbar by adopting a metal organic compound chemical vapor deposition MOCVD technology;
1.2 Deposition of GaN buffer layer 6:
Adopting a metal organic compound chemical vapor deposition MOCVD technology, and epitaxially growing a GaN buffer layer 6 with the thickness of 1 mu m and the Fe doping concentration of 4 multiplied by 10 18cm-3 on an AlN nucleation layer 5 under the process conditions that the flow rate ratio of NH 3 to TMGa is 1500, the temperature is 1000 ℃ and the growth pressure is 50 mbar;
1.3 Deposition of GaN channel layer 7):
Adopting a metal organic compound chemical vapor deposition MOCVD technology, and epitaxially growing a GaN channel layer 7 with the thickness of 200nm and unintentional doping on the GaN buffer layer 6 under the process conditions that the flow rate ratio of NH 3 to TMGa is 1800, the temperature is 950 ℃ and the growth pressure is 100 mbar;
1.4 Deposition of AlGaN barrier layer 8):
An AlGaN barrier layer 8 with an Al component of 0.25 and a thickness of 20nm is epitaxially grown on the GaN channel layer 7 under the process conditions of NH 3 and TMGa with a flow rate ratio of 2000, TMGa and TMAL with a flow rate ratio of 4, a temperature of 1000 ℃ and a growth pressure of 50mbar by adopting a metal organic chemical vapor deposition MOCVD technology.
Step 2: source S, drain D, gate G metal electrodes are deposited on the surface of the barrier layer 8, and device isolation and passivation layer 9 is deposited as shown in fig. 2 (b).
2.1 The surface of the barrier layer 8 is photoetched, namely, a layer of photoresist is coated on the barrier layer 8, then alignment, exposure, development and pattern detection are sequentially carried out to form source and drain regions of the device, and Ar plasma is used for bombarding the source and drain regions for 30s so as to reduce the contact resistance of the source and the drain;
2.2 E-Beam evaporation, vacuumizing to 2.0X10 -4 Pa in a working chamber, setting the accelerating voltage of electron gun at 10Kv, the Beam current of electron gun at 0.3A, and depositing Ti/Al with the thickness of 20/80nm in the source and drain regions as source S and drain D under the process condition of evaporation time of 100S, and then putting the wafer into photoresist stripping liquid to remove photoresist;
2.3 Placing the wafer with the source electrode and the drain electrode metal deposited in an annealing furnace, and rapidly annealing for 30s in an N 2 environment, wherein the annealing temperature in the furnace is 860 ℃ so as to realize ohmic contact on the contact surface of the source electrode, the drain electrode and the barrier layer 8;
2.4 Carrying out photoetching on the surface of the barrier layer 8 again to form a grid region, vacuumizing to 2.0X10 -4 Pa in a working chamber by using electron Beam evaporation E-Beam, setting the accelerating voltage of an electron gun to 10Kv, setting the Beam current of the electron gun to 0.3A, depositing Ni/Al with the thickness of 20/80nm in the grid region as a grid G under the process condition of 100s of evaporation time so as to form Schottky contact on the contact surface of the grid G and the barrier layer 8, and then putting a wafer into photoresist stripping liquid to remove photoresist;
2.5 Ion implantation technology is adopted, and under the process conditions that the implantation energy is 320keV and the ion concentration is 8 multiplied by 10 14cm-2, high-energy ion implantation is carried out on the surface of the barrier layer 8 outside the active region of the wafer, so that the isolation of the device is completed;
2.6 An atomic layer deposition ALD technology is adopted, and a Si 3N4 passivation layer 9 with the thickness of 100nm is epitaxially grown on the barrier layer 8 at the periphery of the source electrode S, the drain electrode D and the grid electrode G under the process condition that the temperature of a reaction chamber is 200 ℃ and the pressure is 1.2 mbar.
Step 3: the surface of the passivation layer 9 is bonded to the sapphire carrier wafer 202 by a high temperature paraffin layer 201 and pressure is applied thereto for bonding, as shown in fig. 2 (c).
Step 4: the back surface of the Si substrate 4 is processed as shown in fig. 2 (d).
4.1 The back side of the Si substrate 4, on which the substrate layer 4, the nucleation layer 5, the buffer layer 6, the channel layer 7, the barrier layer 8, the passivation layer 9, and the devices of the source electrode S, the drain electrode D and the grid electrode G are manufactured, is subjected to grinding and thinning to reduce the thickness to 100 mu m;
4.2 Polishing the back surface of the thinned Si substrate 4 by polishing technology to improve the smoothness and flatness of the wafer surface.
Step 5: an upper electrode connection via 10 is fabricated and filled with an insulating material 12 and a metal interconnection material 13 at the inner wall thereof as shown in fig. 2 (e).
5.1 An Inductively Coupled Plasma (ICP) etching technology is adopted, and an upper electrode connecting through hole 10 with the diameter of 20 mu m and the shape of a through hole being circular is etched on the upper surface of a passivation layer 9 from the back surface of the Si substrate 4 to the front surface of the Si substrate;
5.2 Adopting plasma enhanced chemical vapor deposition PECVD technology, under the process conditions that SiH 4 and N 2 O are used as precursor gases, the flow rate is 60cm 3/min、200cm3/min, the temperature is 260 ℃, the growth pressure is 100Pa, and the radio frequency power is 80W, depositing SiO 2 insulating material 12 with the thickness of 1 mu m on the inner wall of the upper electrode connecting through hole 10;
5.3 A sputtering technique is adopted to deposit a metal interconnection material 13 outside the insulating material 12, namely, a Ti barrier layer with the thickness of 0.3 mu m and a Cu seed layer with the thickness of 0.5 mu m are firstly sequentially deposited outside the insulating material 12, and then a periodic pulse reverse PPR electroplating technique is adopted to deposit metal Cu outside the Cu seed layer until the upper electrode connecting through hole 10 is completely filled.
Step 6: a metal electrode layer 31 is deposited on the back surface of the Si substrate 4, and an electric card refrigerating layer 3 is fabricated as shown in fig. 2 (f).
6.1 E-Beam evaporation, vacuum pumping to 2.5X10 -4 Pa in a working chamber, electron gun acceleration voltage of 8Kv, electron gun Beam current of 0.5A, and evaporation time of 1000s, and depositing metal Cu with thickness of 1 μm on the back of Si substrate 4 as upper metal electrode layer 31;
6.2 Dripping homogeneous solution of polyvinylidene fluoride and copolymer on the surface of the upper metal electrode layer 31, rotating for 60s at the rotating speed of 1000r/s, then placing the solution in an oven, drying at 60 ℃ for 12 hours to remove the organic solvent, and obtaining the polyvinylidene fluoride and copolymer film with the thickness of 20 mu m;
6.3 The dried flakes are placed into an annealing furnace to be annealed in a vacuum environment, wherein the annealing temperature is 100 ℃ and the time is 10 hours, so that the crystallinity of the polyvinylidene fluoride and copolymer films thereof and the bonding quality with the upper metal electrode layer 31 are improved, and the manufacture of the electric card refrigerating layer 3 is completed, wherein the polyvinylidene fluoride and copolymer used in the step is specifically poly (vinylidene fluoride-trifluoroethylene-fluorovinyl chloride) polymer.
Step 7: the lower electrode connection via 11 is fabricated, and the inner wall thereof is filled with an insulating material 12 and a metal interconnection material 13, and then a lower metal electrode layer 32 is deposited, as shown in fig. 2 (g).
7.1 An Inductively Coupled Plasma (ICP) etching technology is adopted, and a lower electrode connecting through hole 11 with the diameter of 20 mu m and the shape of a through hole being circular is etched on the upper surface of a passivation layer 9 from the back surface of the electric card refrigerating layer 3 to the front surface of the electric card refrigerating layer;
7.2 Adopting plasma enhanced chemical vapor deposition PECVD technology, under the process conditions that SiH 4 and N 2 O are used as precursor gases, the flow rate is 60cm 3/min、200cm3/min, the temperature is 260 ℃, the growth pressure is 100Pa, and the radio frequency power is 80W, depositing SiO 2 insulating material 12 with the thickness of 1 mu m on the inner wall of the lower electrode connecting through hole 11;
7.3 A sputtering technique is adopted to deposit a metal interconnection material 13 outside the insulating material 12, namely a Ti blocking layer with the thickness of 0.3 mu m and a Cu seed layer with the thickness of 0.5 mu m are firstly sequentially deposited outside the insulating material 12, and then a periodic pulse reverse PPR electroplating technique is adopted to deposit metal Cu outside the Cu seed layer until the lower electrode connecting through hole 11 is completely filled;
7.4 E-Beam evaporation, vacuum pumping to 2.5X10 -4 Pa, electron gun acceleration voltage of 8Kv, electron gun Beam current of 0.5A, and evaporation time of 1000s, and depositing metal Cu with thickness of 1 μm on the back of the electric card refrigerating layer 3 as the lower metal electrode layer 32.
Step 8: the heat sink layer 1 is bonded to the surface of the lower metal electrode layer 32 through the heat transfer interface layer 2 and the carrier wafer is removed as shown in fig. 2 (h).
8.1 After epoxy resin is dropped on the surface of the lower metal electrode layer 32, the epoxy resin is rotated for 40s at the rotating speed of 2000r/s to obtain an epoxy resin film with the thickness of 2 mu m, a copper-molybdenum alloy heat sink with the thickness of 1mm is placed on the epoxy resin film, and then the copper-molybdenum alloy heat sink is placed in an oven to cure the epoxy resin film for 10min at the temperature of 80 ℃ so as to finish heat sink connection;
8.2 The sapphire slide 202 adhered to the surface of the passivation layer is removed by adopting a dewaxing liquid, so that the preparation of the device is completed.
In the second embodiment, the manufacturing electric card refrigerating layer is barium titanate-based piezoceramic, the thickness is 500 μm, the buffer layer is AlGaN, the Al component is 0.05, and the thickness is 1.5 μm of GaN high electron mobility transistor HEMT with a back barrier structure.
Step one: a group III nitride material is epitaxially deposited on the front surface of SiC substrate 4 as in fig. 2 (a).
Selecting a SiC substrate with the size of 6 inches and the thickness of 500 mu m;
Setting the flow rate ratio of NH 3 to TMAL as 2000, the temperature as 680 ℃, the growth pressure as 150mbar, adopting MOCVD technology to epitaxially grow AlN nucleation layer 5 with thickness as 150nm on the front surface of SiC substrate 4;
Setting the flow rate ratio of NH 3 to TMGa to 2500, the flow rate ratio of TMGa to TMAL to 20, the temperature to 1100 ℃, the growth pressure to 100mbar, adopting a metal organic compound chemical vapor deposition MOCVD technology to epitaxially grow an AlGaN buffer layer 6 on the AlN nucleation layer 5, wherein the Al component is 0.05 and the thickness is 1.5 mu m;
Setting the flow rate ratio of NH 3 to TMGa as 2000, the temperature as 1000 ℃, the growth pressure as 80mbar, adopting the MOCVD technology to epitaxially grow an unintentionally doped GaN channel layer 7 on the AlGaN buffer layer 6, and the thickness is 250nm;
Setting the flow rate ratio of NH 3 and TMGa as 2500, the flow rate ratio of TMGa and TMAL as 4, the temperature as 1100 ℃, the growth pressure as 80mbar, adopting the MOCVD technology of metal organic compound chemical vapor deposition to epitaxially grow AlGaN barrier layer 8 on GaN channel layer 7, wherein the Al component is 0.25 and the thickness is 25nm.
Step two: source S, drain D, gate G metal electrodes are deposited on the surface of the barrier layer 8, and device isolation and passivation layer 9 is deposited as shown in fig. 2 (b).
Photoetching the surface of the barrier layer 8, namely coating a layer of photoresist on the barrier layer 8, sequentially aligning, exposing, developing and detecting patterns to form source and drain regions of the device, and bombarding the source and drain regions for 30s by Ar plasma to reduce the contact resistance of the source and the drain;
Setting the vacuum degree of a working chamber to be 2.0 multiplied by 10 -4 Pa, the accelerating voltage of an electron gun to be 9Kv, the Beam current of the electron gun to be 0.5A and the evaporation time to be 120S, depositing Ti/Al with the thickness of 40/80nm in source and drain regions to serve as a source S and a drain D through electron Beam evaporation E-Beam, and then putting the source S and the drain D into photoresist stripping liquid to remove photoresist;
putting the wafer with the source electrode and the drain electrode metal deposited into an annealing furnace, setting the annealing temperature in the furnace to 800 ℃, and rapidly annealing for 40s in an N 2 environment so as to form ohmic contact on the contact surfaces of the source electrode, the drain electrode and the barrier layer 8;
Photoetching the surface of the barrier layer 8 again to form a grid region, setting the vacuum degree of a working chamber to be 2.0 multiplied by 10 -4 Pa, the accelerating voltage of an electron gun to be 9Kv, the Beam current of the electron gun to be 0.5A and the evaporation time to be 120s, depositing Ni/Al with the thickness of 40/80nm as a grid G in the grid region by using the electron Beam to evaporate E-Beam so as to form Schottky contact on the contact surface of the grid G and the barrier layer 8, and then putting the Schottky contact into photoresist stripping liquid to remove photoresist;
Setting process conditions with the implantation energy of 320keV and the ion concentration of 8 multiplied by 10 14cm-2, and performing high-energy ion implantation on the surface of the barrier layer 8 outside the active region of the wafer by adopting an ion implantation technology to finish device isolation;
Setting the process condition that the temperature of the reaction chamber is 350 ℃ and the pressure is 2.0mbar, and epitaxially growing a SiO 2 passivation layer 9 with the thickness of 120nm on the barrier layer 8 at the periphery of the source electrode S, the drain electrode D and the grid electrode G by adopting an atomic layer deposition ALD technology.
Step three: the surface of the passivation layer 9 is bonded to the sapphire carrier wafer 202 by a high temperature paraffin layer 201 and pressure is applied thereto for bonding, as shown in fig. 2 (c).
Step four: the back surface of the SiC substrate 4 is processed as shown in fig. 2 (d).
Grinding and thinning the back of the SiC substrate 4 on which the devices of the substrate layer 4, the nucleation layer 5, the buffer layer 6, the channel layer 7, the barrier layer 8, the passivation layer 9, the source electrode S, the drain electrode D and the grid electrode G are manufactured, so that the thickness of the SiC substrate is reduced to 200 mu m;
And polishing the back surface of the thinned SiC substrate 4 by using a polishing technology to improve the smoothness and flatness of the surface of the wafer.
Step five: an upper electrode connection via 10 is fabricated and filled with an insulating material 12 and a metal interconnection material 13 at the inner wall thereof as shown in fig. 2 (e).
An Inductively Coupled Plasma (ICP) etching technology is adopted, and an upper electrode connecting through hole 10 with the diameter of 15 mu m and the shape of a through hole is etched on the upper surface of a passivation layer 9 from the back surface of the SiC substrate 4 to the front surface of the SiC substrate;
SiH 4 and N 2 O are set as precursor gases, the flow rates are respectively 70cm 3/min、180cm3/min, the temperature is 280 ℃, the growth pressure is 90Pa, the radio frequency power is 60W, a plasma enhanced chemical vapor deposition PECVD technology is adopted, and a SiO 2 insulating material 12 is deposited on the inner wall of the upper electrode connecting through hole 10, and the thickness is 0.5 mu m;
The metal interconnection material 13 is deposited outside the insulating material 12 by sputtering, namely, a Ti barrier layer with the thickness of 0.3 μm and an Au seed layer with the thickness of 0.5 μm are sequentially deposited outside the insulating material 12, and then the metal Au is deposited outside the Au seed layer by adopting a periodic pulse reverse PPR electroplating technology until the upper electrode connecting through hole 10 is completely filled.
Step six: a metal electrode layer 31 is deposited on the back surface of the SiC substrate 4, and an electric card refrigerating layer 3 is fabricated as shown in fig. 2 (f).
Setting a working chamber vacuum degree of 2.5×10 -4 Pa, an electron gun accelerating voltage of 6Kv, an electron gun Beam current of 0.8A and an evaporation time of 1200s, and depositing metal Au with a thickness of 1.2 μm on the back surface of the SiC substrate 4 as an upper metal electrode layer 31 by electron Beam evaporation E-Beam;
Filtering barium titanate-based piezoelectric ceramic slurry with a binder by adopting a casting process, introducing the filtered barium titanate-based piezoelectric ceramic slurry into a casting machine, spreading the ceramic slurry on the surface of an upper metal electrode layer 31 by using a casting scraper, and finally putting the slices into an oven to be dried and cured for 1h at 60 ℃ to obtain barium titanate-based piezoelectric ceramic with the thickness of 500 mu m;
compacting the cured barium titanate base pressure ceramic under the condition of 20Mpa, and calcining at 600 ℃ for 2 hours to obtain the densified barium titanate base pressure ceramic, thereby completing the manufacture of the electric card refrigerating layer 3.
Step seven: the lower electrode connection via 11 is fabricated, and the inner wall thereof is filled with an insulating material 12 and a metal interconnection material 13, and then a lower metal electrode layer 32 is deposited, as shown in fig. 2 (g).
Etching a lower electrode connecting through hole 11 with a diameter of 15 mu m and a circular through hole shape on the upper surface of a passivation layer 9 from the back surface of the electric card refrigerating layer 3 to the front surface of the electric card refrigerating layer by adopting an Inductively Coupled Plasma (ICP) etching technology;
SiH 4 and N 2 O are set as precursor gases, the flow rates are respectively 70cm 3/min、180cm3/min, the temperature is 280 ℃, the growth pressure is 90Pa, the radio frequency power is 60W, the plasma enhanced chemical vapor deposition PECVD technology is adopted, and the SiO 2 insulating material 12 is deposited on the inner wall of the lower electrode connecting through hole 11, and the thickness is 0.5 mu m;
Depositing a metal interconnection material 13 outside the insulating material 12 by adopting a sputtering technology, namely sequentially depositing a Ti blocking layer with the thickness of 0.3 mu m and an Au seed layer with the thickness of 0.5 mu m outside the insulating material 12, and depositing metal Au outside the Au seed layer by adopting a periodic pulse reverse PPR electroplating technology until the lower electrode connecting through hole 11 is completely filled;
the working chamber vacuum degree was set at 2.5X10 -4 Pa, electron gun acceleration voltage at 6Kv, electron gun Beam current at 0.8A, evaporation time at 1200s, and metal Au with thickness of 1.2 μm was deposited as the lower metal electrode layer 32 on the back of the electric card refrigerating layer 3 by electron Beam evaporation E-Beam.
Step eight: the heat sink layer 1 is bonded to the surface of the lower metal electrode layer 32 through the heat transfer interface layer 2 and the carrier wafer is removed as shown in fig. 2 (h).
Dripping heat-conducting silicone grease on the surface of the lower metal electrode layer 32, rotating for 50s at the rotating speed of 1800r/s to obtain a heat-conducting silicone grease film with the thickness of 2.5 mu m, placing a copper-molybdenum alloy heat sink with the thickness of 1.5mm on the heat-conducting silicone grease film, and then placing the heat-conducting silicone grease film into an oven to cure the heat-conducting silicone grease film for 8min at the temperature of 100 ℃ so as to finish heat sink connection;
And removing the sapphire slide 202 adhered to the surface of the passivation layer by adopting a dewaxing liquid to finish the preparation of the device.
In the third embodiment, the manufacturing electric card refrigeration layer is a lead zirconate titanate piezoelectric film, the thickness is 2 μm, the buffer layer is AlN, and the thickness is 2 μm of GaN Schottky diode SBD.
Step A: a group III nitride material is epitaxially deposited on the front side of the Si substrate 4.
Selecting Si substrate with 6 inch size, 500 μm thickness and crystal orientation of [111 ];
A1 An AlN nucleation layer 5 having a thickness of 250nm was epitaxially grown on the front surface of the Si substrate 4 using a metal organic chemical vapor deposition MOCVD technique, in which the process conditions of the metal organic chemical vapor deposition MOCVD are as follows:
The flow rate ratio of NH 3 to TMAL is 2500,
The temperature was 750 c,
The growth pressure is 200mbar;
A2 An AlN buffer layer 6 with a thickness of 2 μm is epitaxially grown on the AlN nucleation layer 5 by adopting a metal organic chemical vapor deposition MOCVD technique, wherein the process conditions of the metal organic chemical vapor deposition MOCVD are as follows:
The flow rate ratio of NH 3 to TMAL is 2500,
The temperature was 700 c,
The growth pressure is 150mbar;
A3 Using a metal organic chemical vapor deposition MOCVD technique, epitaxially growing a 300nm thick unintentionally doped GaN channel layer 7 on the AlN buffer layer 6, wherein the process conditions for the metal organic chemical vapor deposition MOCVD are as follows:
The flow rate ratio of NH 3 to TMGa is 2500,
The temperature was 1100 c,
The growth pressure is 50mbar;
A4 Using metal organic chemical vapor deposition MOCVD technique, epitaxially growing AlGaN barrier layer 8 with Al composition of 0.25 and thickness of 30nm on GaN channel layer 7, wherein the process conditions of metal organic chemical vapor deposition MOCVD are as follows:
The flow rate ratio of NH 3 to TMGa is 2500,
The flow rate ratio of TMGa to TMAl is 4,
The temperature is 900 ℃,
The growth pressure was 50mbar.
And (B) step (B): cathode and anode metal electrodes are deposited on the surface of the barrier layer 8, and device isolation and passivation layer 9 are deposited.
B1 The surface of the barrier layer 8 is photoetched, namely, a layer of photoresist is coated on the barrier layer 8, then alignment, exposure, development and pattern detection are sequentially carried out to form a device cathode region, and Ar plasma is used for bombarding the cathode region for 30s so as to reduce the contact resistance;
B2 Depositing Ti/Al with the thickness of 40/160nm as a cathode in a cathode region by electron Beam evaporation of E-Beam, and then placing the wafer into a photoresist stripping solution to remove the photoresist, wherein the process conditions of the electron Beam evaporation of E-Beam are as follows:
The vacuum degree of the working chamber is 2.0X10 -4 Pa,
The acceleration voltage of the electron gun was 8Kv,
The beam current of the electron gun is 0.7A,
The evaporation time is 200s;
b3 Placing the wafer subjected to cathode metal deposition into an annealing furnace, and rapidly annealing for 45s in an N 2 environment, wherein the annealing temperature in the furnace is 760 ℃ so as to realize ohmic contact on the contact surface of the cathode and the barrier layer 8;
B4 Performing photoetching on the surface of the barrier layer 8 again to form an anode region, depositing Ni/Al with the thickness of 40/160nm in the anode region as an anode by using electron Beam evaporation E-Beam to form Schottky contact on the contact surface of the anode and the barrier layer 8, and then placing the wafer into photoresist stripping liquid to remove photoresist, wherein the process conditions of the electron Beam evaporation E-Beam are as follows:
The vacuum degree of the working chamber is 2.0X10 -4 Pa,
The acceleration voltage of the electron gun was 8Kv,
The beam current of the electron gun is 0.7A,
The evaporation time is 200s;
B5 Ion implantation technology is adopted to perform high-energy ion implantation on the surface of the barrier layer 8 outside the active region of the wafer to finish device isolation, wherein the process conditions of the ion implantation are as follows:
the implantation energy was set to 320keV,
Ion concentration is 8×10 14cm-2;
B6 Using atomic layer deposition ALD, epitaxially growing a Si 3N4 passivation layer 9 having a thickness of 200nm on the barrier layer 8 at the periphery of the cathode and anode, wherein the process conditions for atomic layer deposition ALD are as follows:
The reaction chamber temperature was 400 c,
The reaction chamber pressure is 5mbar;
Step C: the surface of the passivation layer 9 is stuck to the sapphire carrier wafer through a high-temperature paraffin layer, and pressure is applied to bond the passivation layer.
Step D: the back surface of the Si substrate 4 is processed.
D1 A back surface of the Si substrate 4 on which the substrate layer 4, the nucleation layer 5, the buffer layer 6, the channel layer 7, the barrier layer 8, the passivation layer 9, and the cathode and anode devices are formed is lapped and thinned to reduce the thickness thereof to 150 μm;
D2 Polishing the back surface of the thinned Si substrate 4 by polishing technology to improve the smoothness and flatness of the wafer surface.
Step E: an upper electrode connection via 10 is fabricated and filled with an insulating material 12 and a metal interconnection material 13 at the inner wall thereof.
E1 An Inductively Coupled Plasma (ICP) etching technology is adopted, and an upper electrode connecting through hole 10 with the diameter of 25 mu m and the shape of a square through hole is etched on the upper surface of a passivation layer 9 from the back surface of the Si substrate 4 to the front surface of the Si substrate;
E2 Using a plasma enhanced chemical vapor deposition PECVD technique, depositing a SiO 2 insulating material 12 having a thickness of 1.5 μm on the inner wall of the upper electrode connection via 10, wherein the process conditions of the plasma enhanced chemical vapor deposition PECVD are as follows:
SiH 4 and N 2 O are precursor gases,
The flow rates are respectively 80cm 3/min、160cm3/min,
The temperature was 300 c,
The growth pressure was set at 80Pa,
The radio frequency power is 100W;
e3 A sputtering technique is adopted to deposit a metal interconnection material 13 outside the insulating material 12, namely, a Ti barrier layer with the thickness of 0.3 mu m and a Cu seed layer with the thickness of 0.5 mu m are firstly sequentially deposited outside the insulating material 12, and then a periodic pulse reverse PPR electroplating technique is adopted to deposit metal Cu outside the Cu seed layer until the upper electrode connecting through hole 10 is completely filled.
Step F: a metal electrode layer 31 is deposited on the back of the Si substrate 4 and an electrical card refrigeration layer 3 is fabricated.
F1 Depositing a metal Cu having a thickness of 0.5 μm as the upper metal electrode layer 31 on the back surface of the Si substrate 4 by electron Beam evaporation of E-Beam under the following process conditions:
The vacuum degree of the working chamber is 2.5X10 -4 Pa,
The acceleration voltage of the electron gun was 8Kv,
The beam current of the electron gun is 0.5A,
The evaporation time is 500s;
F2 Dropping lead zirconate titanate sol on the surface of the upper metal electrode layer 31, rotating for 30s at a rotating speed of 3000r/s, then placing the lead zirconate titanate sol in an oven at 300 ℃ for 3min to remove organic substances, and then drying and curing the lead zirconate titanate sol at 500 ℃ for 3min to obtain a lead zirconate titanate piezoelectric film with a thickness of 2 mu m;
F3 Placing the dried sheet into an annealing furnace, and performing rapid annealing in an air environment at 650 ℃ for 10min to improve the crystallinity of the lead zirconate titanate piezoelectric film and the bonding quality with the upper metal electrode layer 31, thereby completing the manufacture of the electric card refrigerating layer 3.
Step G: the lower electrode connection via 11 is formed, and the inner wall thereof is filled with an insulating material 12 and a metal interconnection material 13, and then the lower metal electrode layer 32 is deposited.
G1 An Inductively Coupled Plasma (ICP) etching technology is adopted, and a lower electrode connecting through hole 11 with the diameter of 25 mu m and the shape of a square through hole is etched on the upper surface of a passivation layer 9 from the back surface of the electric card refrigerating layer 3 to the front surface of the electric card refrigerating layer;
G2 By plasma enhanced chemical vapor deposition PECVD technique, siO 2 insulating material 12 with thickness of 1.5 μm is deposited on the inner wall of the lower electrode connecting through hole 11, wherein the process conditions of the plasma enhanced chemical vapor deposition PECVD are as follows:
SiH 4 and N 2 O are precursor gases,
The flow rates are respectively 80cm 3/min、160cm3/min,
The temperature was 300 c,
The growth pressure was set at 80Pa,
The radio frequency power is 100W;
G3 A sputtering technique is adopted to deposit a metal interconnection material 13 outside the insulating material 12, namely a Ti blocking layer with the thickness of 0.3 mu m and a Cu seed layer with the thickness of 0.5 mu m are firstly sequentially deposited outside the insulating material 12, and then a periodic pulse reverse PPR electroplating technique is adopted to deposit metal Cu outside the Cu seed layer until the lower electrode connecting through hole 11 is completely filled;
g4 Depositing a metal Cu with a thickness of 0.5 μm as the lower metal electrode layer 32 on the back surface of the electronic card refrigerating layer 3 by electron Beam evaporation of E-Beam under the following process conditions:
The vacuum degree of the working chamber is 2.5X10 -4 Pa,
The acceleration voltage of the electron gun was 8Kv,
The beam current of the electron gun is 0.5A,
The evaporation time was 500s.
Step H: the heat sink layer 1 is bonded to the surface of the lower metal electrode layer 32 via the heat transfer interface layer 2 and the carrier wafer is removed.
H1 Dripping heat-conducting silica gel on the surface of the lower metal electrode layer 32, rotating for 30s at the rotating speed of 2500r/s to obtain a heat-conducting silica gel film with the thickness of 1 mu m, placing an aluminum-magnesium-silicon alloy heat sink with the thickness of 0.5mm on the heat-conducting silica gel film, and then placing the heat-conducting silica gel film in an oven to cure the heat-conducting silica gel film for 8min at the temperature of 80 ℃ so as to finish heat sink connection;
H2 The sapphire slide adhered to the surface of the passivation layer is removed by adopting a dewaxing liquid, so that the GaN Schottky diode SBD is obtained, as shown in figure 3.
The foregoing description is only three embodiments of the invention and is not intended to limit the invention in any way, and it will be apparent to those skilled in the art that various modifications and changes in form and detail may be made without departing from the spirit and scope of the invention. For example, the heat sink layer can use copper-tungsten alloy in copper alloy, aluminum-silicon-carbon alloy in aluminum alloy and high-heat-conductivity ceramic material besides copper-molybdenum alloy and aluminum-magnesium-silicon alloy; besides barium titanate-based piezoelectric ceramics, lead zirconate titanate piezoelectric films, polyvinylidene fluoride and copolymers thereof, other materials with piezoelectric effect can be used for the electric card refrigerating layer; other high thermal conductivity metals may be used for the upper and lower metal electrode layers in addition to Cu or Au, but these modifications and changes based on the inventive concept are still within the scope of the claims of the present invention.
Claims (10)
1. The GaN device for enhancing heat dissipation of electric card refrigeration comprises a heat sink layer (1), a heat transfer interface layer (2), a substrate layer (4), a nucleation layer (5), a buffer layer (6), a channel layer (7), a barrier layer (8), a metal electrode and a passivation layer (9) from bottom to top, and is characterized in that:
An electric card refrigerating layer (3) is arranged between the substrate layer (4) and the heat transfer interface layer (2), and an upper metal electrode layer (31) and a lower metal electrode layer (32) are respectively arranged on the upper surface and the lower surface of the electric card refrigerating layer (3);
An upper electrode connecting through hole (10) is formed from the upper surface of the upper metal electrode layer (31) to one side of the upper surface of the passivation layer (9) so as to lead out the upper metal electrode to the upper surface of the passivation layer (9);
a lower electrode connecting through hole (11) is formed from the upper surface of the lower metal electrode layer (32) to one side of the upper surface of the passivation layer (9) so as to lead out the lower metal electrode to the upper surface of the passivation layer (9);
Insulating materials (12) and metal interconnection materials (13) are arranged in the upper electrode connecting through hole (10) and the lower electrode connecting through hole (11) so as to realize the electrical isolation of the upper and lower metal electrode layers and the channel layer (7) and the electrical connection of the upper and lower metal electrode layers and the through hole, and simultaneously play a role in enhancing heat dissipation.
2. The device of claim 1, wherein:
The heat sink layer (1) is made of any one of copper alloy, aluminum alloy or high-heat-conductivity ceramic material, and the thickness of the heat sink layer is 0.1-5 mm, wherein the copper alloy comprises copper tungsten alloy and copper molybdenum alloy, and the aluminum alloy comprises aluminum-magnesium-silicon alloy and aluminum-silicon-carbon alloy;
the heat transfer interface layer (2) adopts any one of heat conduction silica gel, heat conduction silicone grease or epoxy resin, and the thickness of the heat transfer interface layer is 0.5-5 mu m;
The electric card refrigerating layer (3) adopts any one material with piezoelectric effect from barium titanate base piezoelectric ceramics, lead zirconate titanate piezoelectric film, polyvinylidene fluoride and copolymer thereof, and the thickness is 1-2000 mu m.
3. The device according to claim 1, wherein the upper metal electrode layer (31) and the lower metal electrode layer (32) have a thickness of 0.2-2 μm, and are formed by depositing metal Cu or metal Au or other high thermal conductivity metal, and are used for applying a voltage to the surface of the electric card refrigerating layer (3) to form an electric field, so that the piezoelectric material is transformed into a phase, and the heat dissipation capability of the device is improved.
4. The device of claim 1, wherein:
The substrate layer (4) adopts Si or SiC, and the thickness of the substrate layer is 100-600 mu m;
the nucleation layer (5) adopts AlN, and the thickness of the AlN is 150-250 nm;
The buffer layer (6) adopts any one of GaN, alN or AlGaN, and the thickness of the buffer layer is 0.1-5 mu m;
the channel layer (7) adopts GaN, and the thickness of the GaN is 20-800 nm;
The barrier layer (8) is made of AlGaN, and has a thickness of 10-30 nm.
5. The device of claim 1, wherein:
The passivation layer (9) adopts SiO 2 or Si 3N4 insulating medium as electrical isolation, and the thickness of the passivation layer is 80-200 nm;
The upper electrode connecting through hole (10) and the lower electrode connecting through hole (11) are round holes or square holes, and the diameter of the upper electrode connecting through hole is 5-100 mu m.
6. The device of claim 5, wherein:
The insulating materials (12) in the upper electrode connecting through hole (10) and the lower electrode connecting through hole (11) are SiO 2, and the thickness of the insulating materials is 0.5-2 mu m;
The metal interconnection material (13) in the upper electrode connection through hole (10) and the lower electrode connection through hole (11) adopts Ti and Cu or Ti and Au, wherein Ti is used as a metal barrier layer.
7. The preparation method of the GaN device for enhancing heat dissipation by electric card refrigeration is characterized by comprising the following steps of:
s1: a nucleation layer, a buffer layer, a channel layer and a barrier layer are epitaxially deposited on the front surface of the substrate through metal organic chemical vapor deposition MOCVD in sequence;
S2: depositing electrode metal on the barrier layer by electron Beam evaporation E-Beam, then performing ion implantation isolation, and then depositing a passivation layer by atomic layer deposition ALD;
s3: connecting the upper surface of the passivation layer to an external carrier wafer through a bonding process;
s4: carrying out pretreatment of lapping thinning and surface polishing on the back surface of the substrate;
S5: etching an upper electrode connecting through hole from the back surface of the pretreated substrate to one side of the upper surface of the passivation layer, depositing an insulating material on the inner wall of the upper electrode connecting through hole by plasma enhanced chemical vapor deposition PECVD, sputtering a metal barrier layer and a metal seed layer, and finally electroplating metal to completely fill the upper electrode connecting through hole;
S6: depositing an upper metal electrode layer on the back of the pretreated substrate by electron Beam evaporation E-Beam, and manufacturing an electric card refrigerating layer on the lower surface of the upper metal electrode layer;
S7: etching a lower electrode connecting through hole from the back surface of the electric card refrigerating layer to one side of the upper surface of the passivation layer, depositing an insulating material on the inner wall of the lower electrode connecting through hole by plasma enhanced chemical vapor deposition PECVD, sputtering a metal barrier layer and a metal seed layer, electroplating metal to completely fill the lower electrode connecting through hole, and finally depositing a lower metal electrode layer by electron Beam evaporation E-Beam;
s8: and bonding a heat sink material on the surface of the lower metal electrode layer through a heat transfer interface material, and removing the carrier wafer to finish the device manufacturing.
8. The method according to claim 7, wherein the metal-organic chemical vapor deposition MOCVD in step S1 is performed under the following process conditions:
TMGa is used as a precursor of Ga, TMAL is used as a precursor of Al, mixed gas of H 2 and N 2 is used as carrier gas, and NH 3 is used as a nitrogen source;
The flow rate ratio of NH 3 and TMAL of the deposited AlN is 1500-2500, the temperature is kept at 450-750 ℃, and the growth pressure is kept at 100-200 mbar;
The flow rate ratio of NH 3 and TMGa of deposited GaN is 1500-2500, the temperature is kept at 900-1100 ℃, and the growth pressure is kept at 50-150 mbar;
The flow rate ratio of NH 3 and TMGa of deposited AlGaN is 1500-2500, the flow rate ratio of TMGa and TMAL is 4-20, the temperature is kept at 900-1100 ℃, and the growth pressure is kept at 50-100 mbar.
9. The method of claim 7, wherein the plasma enhanced chemical vapor deposition PECVD process conditions in step S5 and step S7 are as follows:
SiH 4 and N 2 O are used as precursor gases, the flow rates are respectively kept at 50-80 cm 3/min、160～200cm3/min, the temperature is kept at 250-300 ℃, the growth pressure is kept at 80-100 Pa, and the radio frequency power is set at 60-100W.
10. The method according to claim 7, wherein:
The E-Beam evaporation in the step S2 is carried out under the following process conditions:
Vacuumizing the working chamber to 2.0X10 -4 Pa, accelerating the electron gun to 8-10 Kv, and evaporating for 80-220 s, wherein the beam current of the electron gun is 0.2-0.8A;
The E-Beam is evaporated by the electron Beam in the step S6 and the step S7, and the process conditions are as follows:
The working chamber is vacuumized to 2.5X10 -4 Pa, the accelerating voltage of the electron gun is 6-10 Kv, the beam current of the electron gun is 0.3-1A, and the evaporating time is 200-2000 s.
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