CN117881045B

CN117881045B - LED linear driving thermal derating and over-temperature protection system

Info

Publication number: CN117881045B
Application number: CN202410271165.6A
Authority: CN
Inventors: 毛星贵; 杨瑞聪; 高耿辉
Original assignee: Xiamen Yuanshun Microelectronics Technology Co ltd
Current assignee: Xiamen Yuanshun Microelectronics Technology Co ltd
Priority date: 2024-03-11
Filing date: 2024-03-11
Publication date: 2024-06-11
Anticipated expiration: 2044-03-11
Also published as: CN117881045A

Abstract

The invention relates to the field of over-temperature protection, in particular to a thermal derating and over-temperature protection system driven by an LED (light-emitting diode) linearly, which comprises a V _REF&I_PTAT generation module, a low-temperature drift current generation module, a thermal derating module and an over-temperature protection module; the V _REF&I_PTAT generation module outputs reference voltage V _REF and positive temperature coefficient current I _PTAT; the low-temperature drift current generation module generates low-temperature coefficient current I _o and outputs the low-temperature coefficient current I _o to the thermal derating module and the over-temperature protection module; the output end of the thermal derating module is electrically connected with the output end of the V _REF&I_PTAT generating module; the over-temperature protection module is electrically connected with the drive control module of the external LED linear drive unit, the external LED linear drive unit is turned off, and the circuit has good detection precision by adopting a common-source common-gate structure formed by the inverted ratio tube.

Description

LED linear driving thermal derating and over-temperature protection system

Technical Field

The invention relates to the field of high-temperature protection, in particular to a thermal derating and over-temperature protection system for linear driving of an LED.

Background

Thermal derating circuits and over-temperature protection circuits are critical circuits used to protect electronic devices and circuits from damage from excessive heat. It is able to monitor the temperature of the device or circuit and take corresponding measures to prevent overheating of the device when the temperature exceeds a set threshold. The thermal derating circuit and the over-temperature protection circuit are widely applied to various electronic equipment and circuits, such as computers, mobile phones, televisions, power adapters and the like. The device can be effectively protected from being damaged by overheat, the service life of the device is prolonged, and the safety and reliability of the device are improved. Therefore, high temperature protection circuits play a very important role in modern electronic devices.

The existing thermal derating and over-temperature protection circuit generally judges the temperature by detecting the voltage with a temperature coefficient, and then realizes the protection function through the subsequent circuits such as a comparator, a switching tube and the like, so that the whole circuit is complex. And the circuits such as a comparator, a switching tube and the like and the device have defects such as offset, process, temperature correlation and the like. Meanwhile, the characteristics of the conventional thermal derating circuit and the over-temperature protection circuit cannot be freely changed after the design is completed, and the practicality is poor.

Disclosure of Invention

The invention aims to provide a thermal derating and over-temperature protection system for linear driving of an LED, which aims to solve the problems that the circuit structure of the traditional over-temperature protection circuit is complex, the component devices have defects such as offset, process, temperature correlation and the like, and the characteristics cannot be freely changed, and the practicability is high.

In order to achieve the above purpose, the present invention adopts the following technical scheme:

A thermal derating and over-temperature protection system driven by an LED (light-emitting diode) comprises a V _REF&I_PTAT generation module, a low-temperature drift current generation module, a thermal derating module and an over-temperature protection module;

The V _REF&I_PTAT generation module outputs a reference voltage V _REF to a positive input end of an operational amplifier of an external LED linear driving unit, the V _REF&I_PTAT generation module outputs a positive temperature coefficient current I _PTAT, the I _PTAT current is reduced or amplified and then is output to the thermal derating module and the over-temperature protection module, and the V _REF&I_PTAT generation module outputs a modulation current to the thermal derating module;

the low-temperature drift current generation module generates low-temperature coefficient current I _o and outputs the low-temperature coefficient current I _o to the thermal derating module and the over-temperature protection module;

The output end of the thermal derating module is electrically connected with the output end of the V _REF&I_PTAT generating module, and the thermal derating module changes the reference voltage V _REF to adjust the power of the external LED linear driving unit;

The over-temperature protection module is electrically connected with the driving control module of the external LED linear driving unit, and the external LED linear driving unit is turned off until the temperature is reduced below the hysteresis quantity.

Further, the V _REF&I_PTAT generation module comprises a starting circuit, a band gap reference circuit and an I _PTAT scaling circuit, wherein the power input ends of the starting circuit, the band gap reference circuit and the I _PTAT scaling circuit are electrically connected with an external power supply, the output end of the starting circuit is electrically connected with the input end of the band gap reference circuit, the starting circuit controls the band gap reference circuit to generate a reference voltage V _REF and a positive temperature coefficient current I _PTAT,

The first output end of the band gap reference circuit outputs a reference voltage V _REF to the positive input end of the operational amplifier of the external LED linear driving unit, the second output end of the band gap reference circuit outputs positive temperature coefficient currents I _PTAT to I _PTAT, the output end of the I _PTAT scaling circuit is electrically connected with the thermal derating module and the over-temperature protection module, and the third output end of the band gap reference circuit is electrically connected with the thermal derating module.

Further, the low-temperature drift current generating module comprises a low-temperature drift current generating circuit and an I _o scaling circuit, wherein the power input ends of the low-temperature drift current generating circuit and the I _o scaling circuit are electrically connected with an external power supply, the output end of the low-temperature drift current generating circuit is electrically connected with the input end of the I _o scaling circuit, and the output end of the I _o scaling circuit is electrically connected with the thermal derating module and the over-temperature protection module.

Further, the thermal derating module comprises a thermal derating point determining circuit and a derating curve slope modulating circuit;

The power input ends of the thermal derate point determining circuit and the derate curve slope modulating circuit are electrically connected with an external power supply, the thermal derate point determining circuit is electrically connected with the output ends of the I _o scaling circuit and the I _PTAT scaling circuit, and the output end of the thermal derate point determining circuit is electrically connected with the derate curve slope modulating circuit;

the derating curve slope modulation circuit is electrically connected between the band gap reference circuit and the thermal derating point determining circuit.

Further, the over-temperature protection module comprises an over-temperature protection circuit, a trigger circuit and an inverter circuit, wherein the power input ends of the over-temperature protection circuit, the trigger circuit and the inverter circuit are electrically connected with an external power supply, the input ends of the over-temperature protection circuit are electrically connected with the output ends of the I _o scaling circuit and the I _PTAT scaling circuit, the output end of the over-temperature protection circuit is electrically connected with the input end of the trigger circuit, the output end of the trigger circuit is electrically connected with the input end of the inverter circuit, and the inverter circuit outputs OTP signals to the driving control module of the external LED linear driving unit and the feedback input end of the over-temperature protection circuit.

Further, the low-temperature drift current generating circuit comprises a mos tube P7, a mos tube P8, a mos tube N11, a triode Q4 and a resistor R3;

the I _o scaling circuit comprises a mos pipe P9, a mos pipe P10, a mos pipe P11, a mos pipe P12, a mos pipe N13, a mos pipe N14 and a mos pipe N15;

The sources of the mos tube P7, the mos tube P9 and the mos tube P11 are electrically connected with an external power supply, and the grid electrode and the drain electrode of the mos tube P7 are electrically connected with the grid electrode of the mos tube P9 and the source electrode of the mos tube P8;

The drain electrode of the mos tube P9 is electrically connected with the source electrode of the mos tube P10;

The drain electrode and the grid electrode of the mos tube P11 are electrically connected with the source electrode of the mos tube P12, the thermal derate point determining circuit and the over-temperature protection circuit;

The grid electrode and the drain electrode of the mos transistor P8 are electrically connected with the grid electrode of the mos transistor P10, one end of the resistor R3 and the emitter electrode of the triode Q4;

The other end of the resistor R3 is electrically connected with the base electrode of the triode Q4, the drain electrode of the mos transistor N11 and the grid electrode;

The drain electrode of the mos transistor P10 is electrically connected with the drain electrode and the grid electrode of the mos transistor N12, the grid electrode of the mos transistor N14, the thermal derating point determining circuit and the over-temperature protection module,

The drain electrode and the grid electrode of the mos tube P12 are electrically connected with the drain electrode of the mos tube N14, the thermal derate point determining circuit and the over-temperature protection circuit;

the source electrode of the mos tube N12 is electrically connected with the drain electrode and the grid electrode of the mos tube N13, the grid electrode of the mos tube N15, the thermal derate point determining circuit and the over-temperature protection module;

the source electrode of the mos tube N14 is electrically connected with the drain electrode of the mos tube N15;

The collector of the triode Q4, the source of the mos transistor N11, the source of the mos transistor N13 and the source of the mos transistor N15 are all grounded.

Further, the thermal derate determining circuit comprises a mos pipe P17, a mos pipe P18, a mos pipe P19, a mos pipe P20, a mos pipe P21, a mos pipe P22, a mos pipe P23, a mos pipe P24, a mos pipe N20, a mos pipe N21, a switch K1, a switch K2 and a switch K3;

The sources of the mos transistors P17, P19, P21 and P23 are electrically connected with an external power supply,

The grid electrode of the mos tube P17 is electrically connected with the I _PTAT scaling circuit and the over-temperature protection circuit,

The gates of the mos tube P19, the mos tube P21 and the mos tube P23 are electrically connected with the I _o scaling circuit and the over-temperature protection circuit;

the drains of the mos transistors P17, P19, P21 and P23 are electrically connected with the sources of the mos transistors P18, P20, P22 and P24, respectively;

the grid electrode of the mos tube P18 is electrically connected with the I _PTAT scaling circuit and the over-temperature protection circuit,

The gates of the mos tube P20, the mos tube P22 and the mos tube P24 are electrically connected with the I _o scaling circuit and the over-temperature protection circuit;

The drains of the mos tube P20, the mos tube P22 and the mos tube P24 are respectively electrically connected with one ends of the switch K1, the switch K2 and the switch K3; the drain electrode of the mos tube P18 is electrically connected with the derating curve slope modulation circuit, the drain electrode of the mos tube N20 and the other ends of the switch K1, the switch K2 and the switch K3;

The grid electrode of the mos tube N20 is electrically connected with the I _o scaling circuit and the over-temperature protection circuit; the source electrode of the mos tube N20 is electrically connected with the drain electrode of the mos tube N21, and the grid electrode of the mos tube N21 is electrically connected with the I _o scaling circuit and the over-temperature protection circuit; the source electrode of the mos tube N21 is grounded.

Further, the derating curve slope modulation circuit comprises a mos tube N1, a mos tube N2, a mos tube N3, a mos tube N4, a mos tube N5, a mos tube N6, a mos tube N7, a mos tube N8, a mos tube N9, a mos tube N10, a switch K7, a switch K8 and a switch K9;

The output end of the band gap reference circuit is electrically connected with one ends of a switch K7, a switch K8 and a switch K9 and the drain electrode of a mos tube N7, the other end of the switch K7 is electrically connected with the drain electrode of a mos tube N5, the other end of the switch K8 is electrically connected with the drain electrode of a mos tube N3, and the other end of the switch K9 is electrically connected with the drain electrode of a mos tube N1; the grid electrode of the mos tube N1 is electrically connected with the grid electrode of the mos tube N3, the grid electrode of the mos tube N5, the grid electrode of the mos tube N7, the grid electrode and the drain electrode of the mos tube N9 and the drain electrode of the mos tube P18; the source electrode of the mos tube N1 is electrically connected with the drain electrode of the mos tube N2;

the grid electrode of the mos tube N2 is electrically connected with the grid electrode of the mos tube N4, the grid electrode of the mos tube N6, the grid electrode of the mos tube N8, the source electrode of the mos tube N9 and the grid electrode and the drain electrode of the mos tube N10;

The sources of the mos transistors N3, N5 and N7 are respectively and electrically connected with the drains of the mos transistors N4, N6 and N8; the sources of the mos tube N2, the mos tube N4, the mos tube N6, the mos tube N8 and the mos tube N10 are all grounded.

Further, the over-temperature protection circuit comprises a mos tube P25, a mos tube P26, a mos tube P27, a mos tube P28, a mos tube P29, a mos tube P30, a mos tube P31, a mos tube P32, a mos tube N22, a mos tube N23, a mos tube NS, a switch K4, a switch K5 and a switch K6;

The sources of the mos transistors P25, P27, P29 and P31 are electrically connected with an external power supply, and the grid of the mos transistor P25 is electrically connected with the I _PTAT scaling circuit and the thermal deration point determining circuit; the gates of the mos tube P27, the mos tube P29 and the mos tube P31 are electrically connected with the I _o scaling circuit and the thermal deration point determining circuit;

the drains of the mos transistors P25, P27, P29 and P31 are electrically connected with the sources of the mos transistors P26, P28, P30 and P32, respectively; the grid electrode of the mos tube P26 is electrically connected with the I _PTAT scaling circuit and the thermal deration point determining circuit; the gates of the mos tube P28, the mos tube P30 and the mos tube P32 are electrically connected with the I _o scaling circuit and the thermal deration point determining circuit;

The drain electrode of the mos tube P26 is electrically connected with the drain electrode of the mos tube N22, the source electrode of the mos tube NS and the trigger circuit; the drains of the mos transistors P28, P30 and P32 are respectively electrically connected with one ends of the switches K4, K5 and K6, the other ends of the switches K4, K5 and K6 are electrically connected with the drain of the mos transistor NS, and the grid of the mos transistor NS is electrically connected with the inverter circuit;

The grid electrode of the mos tube N22 is electrically connected with the I _o scaling circuit and the thermal deration point determining circuit, the source electrode of the mos tube N22 is electrically connected with the drain electrode of the mos tube N23, the grid electrode of the mos tube N23 is electrically connected with the I _o scaling circuit and the thermal deration point determining circuit, and the source electrode of the mos tube N23 is grounded.

Further, the trigger circuit comprises a mos pipe P33, a mos pipe P34, a mos pipe P35, a mos pipe N24, a mos pipe N25 and a mos pipe N26;

The source electrode of the mos transistor P34 and the drain electrode of the mos transistor N26 are electrically connected with an external power supply, the gate electrode of the mos transistor P34 is electrically connected with the gate electrode of the mos transistor P33, the gate electrode of the mos transistor N24, the gate electrode of the mos transistor N25 and the drain electrode of the mos transistor P26, the drain electrode of the mos transistor P34 is electrically connected with the source electrode of the mos transistor P33 and the source electrode of the mos transistor P35, the drain electrode of the mos transistor P33 is electrically connected with the gate electrode of the mos transistor P35, the drain electrode of the mos transistor N24, the gate electrode of the mos transistor N26 and the inverter circuit, the source electrode of the mos transistor N24 is electrically connected with the drain electrode of the mos transistor N25 and the source electrode of the mos transistor N26, and the drain electrode of the mos transistor P35 are grounded.

Further, the inverter circuit comprises a mos transistor P36 and a mos transistor N27;

The source electrode of the mos tube P36 is electrically connected with an external power supply, the grid electrode of the mos tube P36 is electrically connected with the grid electrode of the mos tube N27 and the drain electrode of the mos tube P33, and the drain electrode of the mos tube P36 is electrically connected with the drain electrode of the mos tube N27 and the grid electrode of the mos tube NS, and is used as an OTP interface to be electrically connected with a driving control module of an external LED linear driving unit; the source electrode of the mos tube N27 is grounded.

After the technical scheme is adopted, compared with the background technology, the invention has the following advantages:

1. In the scheme, the thermal derating module and the over-temperature protection module are realized by adopting a current technology, and the current copied by the current mirror is I _PTAT and I _o which are related to the number proportion of the mos tubes, so that the thermal derating characteristic and the over-temperature protection characteristic are related to the number proportion of the mos tubes only, and devices such as a comparator and a switch tube are not needed, and a common-source common-gate structure formed by the inverted ratio tubes is adopted, so that the circuit has good precision. Compared with a common thermal derating and over-temperature protection circuit, the circuit has the advantages of simple and accurate structure, quantization adjustment, adjustability and no process imbalance.

2. In this scheme, the quantization adjustment that heat derate module and excess temperature protection module are all can be nimble to realize parameter trimming, variable heat derate characteristic and variable excess temperature protection characteristic, heat derate bent limit grade function such as, have better practicality.

Drawings

FIG. 1 is a system block diagram of a LED linear drive thermal derating and overtemperature protection system of the present invention;

FIG. 2 is a waveform diagram of exemplary functions of a linear-driven thermal derating and overtemperature protection system for LEDs according to the present invention;

FIG. 3 is a circuit diagram of a LED linear drive thermal derating and overtemperature protection system according to the present invention;

FIG. 4 is a graph showing the variation of the low temperature drift current I _o1 of the LED linear driving thermal derating and over-temperature protection system according to the present invention with temperature;

Fig. 5 is a transient temperature scanning experimental diagram of the low temperature drift current I _o1 of the LED linear driving thermal derating and over-temperature protection system according to the present invention;

FIG. 6 is a graph of low temperature drift current I _o2 with temperature for a smaller value of the LED linear drive thermal derating and over-temperature protection system of the present invention;

FIG. 7 is a current simulation diagram of the LED linear driving thermal derating and over-temperature protection system after current scaling of the low temperature drift I _o;

FIG. 8 is a variable thermal derate point simulation of the LED linear drive thermal derate and over-temperature protection system of the present invention;

FIG. 9 is a graph of a variable thermal derate slope simulation of the LED linear drive thermal derate and over-temperature protection system of the present invention;

FIG. 10 is a simulation diagram of current source conflict and OTP state flip transient temperature scan of the LED linear drive thermal derating and over-temperature protection system of the present invention;

FIG. 11 is a graph showing the simulation of the current source and OTP state change with temperature under DC of the LED linear driving thermal derating and over-temperature protection system according to the present invention;

FIG. 12 is a graph of hysteresis simulation of an OTP after the feedback current of the LED linear drive thermal derate and over-temperature protection system of the present invention is set to I _K4;

FIG. 13 is a graph of a simulation of the current source I _P25 of the LED linear drive thermal derating and over-temperature protection system of the present invention incorporated into I _K4 to yield I _{P25_1};

FIG. 14 is a graph of a simulation of the current source I _P25 of the LED linear drive thermal derating and over-temperature protection system of the present invention incorporated into I _K4、I_K5 to yield I _{P25_2};

FIG. 15 is a graph of a simulation of the current source I _P25 of the LED linear drive thermal derating and over-temperature protection system of the present invention incorporated into I _K4、I_K5、I_K6 to yield I _{P25_3};

FIG. 16 is a graph of simulated OTP inversion point variation for a LED linear drive thermal derate and over-temperature protection system according to the present invention after quantization current adjustment;

FIG. 17 is a graph of simulated changes in the thermal derate and over-temperature protection hysteresis of the LED linear drive system after quantization current adjustment;

fig. 18 is a schematic diagram showing the derating curve classification of the LED linear driving thermal derating and over-temperature protection system according to the present invention.

Detailed Description

The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.

In addition, it should be noted that: the terms "upper," "lower," "left," "right," "vertical," "horizontal," "inner," "outer," and the like are based on the orientation or positional relationship shown in the drawings, and are merely for convenience of description and to simplify the description, and do not denote or imply that the apparatus or elements of the present invention must have a particular orientation, and thus should not be construed as limiting the invention.

When an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.

Unless specifically stated or limited otherwise, the terms "mounted," "connected," and "coupled" are to be construed broadly, and may be, for example, fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communicated with the inside of two elements or the interaction relationship of the two elements. The specific meaning of the above terms in the invention will be understood by those skilled in the art according to the specific circumstances.

Examples

Referring to fig. 1-18, the present embodiment provides a thermal derating and over-temperature protection system for LED linear driving, which includes a low-temperature drift current generating module, a V _REF&I_PTAT generating module, a thermal derating module and an over-temperature protection module. The low-temperature drift current generating module generates low-temperature coefficient current (zero-temperature coefficient current) I _o,I_o, and outputs the low-temperature coefficient current (zero-temperature coefficient current) I _o,I_o to the input end of the thermal derating module and the over-temperature protection module after scaling. The V _REF&I_PTAT generating module outputs a reference voltage V _REF to the positive input end of the operational amplifier of the external LED linear driving unit, and the V _REF&I_PTAT generating module outputs a positive temperature coefficient current I _PTAT,I_PTAT to the input ends of the thermal derating module and the over-temperature protection module after scaling. The input end of the thermal derating module is electrically connected with the input end of the over-temperature protection module, the output end of the low-temperature drift current generation module and the output end of the V _REF&I_PTAT generation module, the output end of the thermal derating module is electrically connected with the output end of the V _REF&I_PTAT generation module, and the thermal derating module changes the reference voltage V _REF to adjust the power of the external LED linear driving unit, so that the heating of the external LED is reduced. The output end of the over-temperature protection module is electrically connected with the driving control module of the external LED linear driving unit, and when the temperature reaches a threshold value, the external LED linear driving unit is turned off through the over-temperature protection module until the temperature drops below the hysteresis quantity.

In this embodiment, the V _REF&I_PTAT generating module includes a start-up circuit, a bandgap reference circuit, and an I _PTAT scaling circuit, where power input terminals of the start-up circuit, the bandgap reference circuit, and the I _PTAT scaling circuit are electrically connected to an external power source. The output end of the starting circuit is electrically connected with the input end of the band gap reference circuit, and the starting circuit controls the band gap reference circuit to generate reference voltage V _REF and positive temperature coefficient current I _PTAT. The first output end of the band gap reference circuit outputs a reference voltage V _REF to the positive input end of the operational amplifier of the external LED linear driving unit; the second output of the bandgap reference circuit outputs positive temperature coefficient currents I _PTAT through I _PTAT to the input of the scaling circuit. The output end of the I _PTAT scaling circuit is electrically connected with the thermal derating module and the over-temperature protection module. The third output end of the band gap reference circuit is electrically connected with the thermal derating module.

Specifically, the starting circuit includes a mos transistor PS1, a mos transistor PS2, a mos transistor PS3, a mos transistor PS4, a mos transistor NS1, a mos transistor NS2, a mos transistor NS3, a capacitor CS1, and a transistor QS1; the band gap reference circuit comprises a mos transistor P1, a mos transistor P2, a mos transistor P3, a mos transistor P4, a mos transistor P5, a mos transistor P6, a mos transistor NA, a mos transistor NB, a mos transistor NR, a triode Q1, a triode Q2, a triode Q3, a resistor R1 and a resistor R2; the I _PTAT scaling circuit includes a mos pipe P13, a mos pipe P14, a mos pipe P15, a mos pipe P16, a mos pipe N17, a mos pipe N18, and a mos pipe N19.

The source of the mos transistor PS1, the source of the mos transistor PS2, the source of the mos transistor PS3, the source of the mos transistor P1, the source of the mos transistor P3, and the source of the mos transistor P5 are all electrically connected to an external power source.

The drain electrode of the mos tube PS1 is electrically connected with the gate electrode and the drain electrode of the mos tube NS1 and the gate electrode of the mos tube NS2, the drain electrode of the mos tube PS2 is electrically connected with the drain electrode of the mos tube NS2 and one end of the capacitor CS1, and the source electrode of the mos tube NS2 is electrically connected with the other end of the capacitor CS1, the gate electrode of the mos tube NS3, the drain electrode of the mos tube NA and the drain electrode of the mos tube P2.

The drain electrode and the gate electrode of the mos transistor PS3 are electrically connected with the source electrode of the mos transistor PS4, the gate electrode of the mos transistor P1, the gate electrode of the mos transistor P3, the gate electrode of the mos transistor P5 and the I _PTAT scaling circuit, that is, the drain electrode and the gate electrode of the mos transistor PS3 are electrically connected with the source electrode of the mos transistor PS4, the gate electrode of the mos transistor P1, the gate electrode of the mos transistor P3, the gate electrode of the mos transistor P5 and the gate electrode of the mos transistor P13.

The drains of the mos transistors P1, P3, P5 are electrically connected to the sources of the mos transistors P2, P4, P6, respectively.

The drain and gate of the mos transistor PS4 are electrically connected to the drain of the mos transistor NS3, the gates of the mos transistors P2, P4, P6, and the I _PTAT scaling circuit, i.e., the drain and gate of the mos transistor PS4 are electrically connected to the drain of the mos transistor NS3, the gates of the mos transistors P2, P4, P6, and P14.

The drain electrode of the mos transistor P4 is electrically connected with the drain electrode of the mos transistor NB, the gate electrode of the mos transistor NA. The drain electrode of the mos transistor P6 is electrically connected to the gate electrode and the drain electrode of the mos transistor NR, and the thermal derating module. The source of the mos transistor NS3, the source of the mos transistor NA, the source of the mos transistor NB, and the source of the mos transistor NR are electrically connected to the emitter of the transistor QS1, the emitter of the transistor Q1, one end of the resistor R1, and one end of the resistor R2, where the end of the resistor R2 electrically connected to the source of the mos transistor NR is used as the output VBG of the bandgap reference, and used as the positive input reference voltage VREF of the op-amp in the external LED linear driving unit, and the other ends of the resistor R1 and the resistor R2 are electrically connected to the emitter of the transistor Q2 and the emitter of the transistor Q3, respectively.

The gate of mos transistor PS1, the gate of mos transistor PS2, the source of mos transistor NS1, the collector and base of transistor QS1, the collector and base of transistor Q2, and the collector and base of transistor Q3 are all grounded.

Likewise, the start-up circuit and bandgap reference circuit may be comprised of other electronic components.

(W/L)_P1：(W/L)_P3：(W/L)_P5=1,(W/L)_P2：(W/L)_P4：(W/L)_P6=1,(W/L)_NB：(W/L)_NA=1,Q2：Q1=1:8

After the circuit is started and stabilized, the circuit is used for obtaining:

Wherein VT has a known positive temperature coefficient and so the I _PTAT current has a corresponding positive temperature coefficient, I _P5 is loaded on R2 to form V _R2,V_R2 added to V _BE3 of Q3:

V _BE has a known negative temperature coefficient at room temperature, so taking the appropriate R2/R1 can cancel the positive and negative temperature coefficients to form the zero temperature coefficient reference voltage V _REF. The width-to-length ratio of (W/L) _x to mos tube x is, for example, (W/L) _P1 is the width-to-length ratio of mos tube P1; i _x the current generated by the corresponding component, for example I _P1 the current generated by mos transistor P1, I _C1 the collector current of transistor Q1, and I _Q1 the current when transistor Q1 just reaches saturation.

The sources of the mos transistors P13 and P15 are electrically connected to an external power source. The gate of the mos transistor P13 is electrically connected to the bandgap reference circuit and the start-up circuit, i.e. the drain of the gate mos transistor PS3 of the mos transistor P13 is electrically connected to the gate, the source of the mos transistor PS4, the gate of the mos transistor P1, the gate of the mos transistor P3, and the gate of the mos transistor P5. The drain electrode of the mos transistor P13 is electrically connected with the source electrode of the mos transistor P14, and the gate electrode of the mos transistor P14 is electrically connected with the bandgap reference circuit and the start-up circuit, that is, the gate electrode of the mos transistor P14, the gate electrode and the drain electrode of the mos transistor PS4, and the drain electrode of the mos transistor NS3, the gate electrode of the mos transistor P2, the gate electrode of the mos transistor P4, and the gate electrode of the mos transistor P6 are electrically connected. The drain of mos transistor P14 is electrically connected to the drain and gate of mos transistor N16 and the gate of mos transistor N18. The source of mos transistor N16 is electrically connected to the drain and gate of mos transistor N17 and the gate of mos transistor N19.

The gate and the drain of the mos transistor P15 are electrically connected to the source, the thermal derating module and the over-temperature protection module of the mos transistor P16. The gate and the drain of the mos transistor P16 are electrically connected, and are electrically connected with the drain of the mos transistor N18, the thermal derating module and the over-temperature protection module. The source of mos transistor N18 is electrically connected to the drain of mos transistor N19. The source of mos transistor N17 and the source of mos transistor N19 are both grounded.

The low-temperature drift current generation module comprises a low-temperature drift current generation circuit and an I _o scaling circuit; the output end of the low-temperature drift current generation module is electrically connected with the input end of the I _o scaling circuit, and the output end of the I _o scaling circuit is electrically connected with the thermal derating module and the over-temperature protection module.

The low-temperature drift current generation circuit comprises a mos tube P7, a mos tube P8, a mos tube N11, a triode Q4 and a resistor R3; the I _o scaling circuit comprises a mos pipe P9, a mos pipe P10, a mos pipe P11, a mos pipe P12, a mos pipe N13, a mos pipe N14 and a mos pipe N15;

The source of mos transistor P7 is electrically connected to an external power source. The gate and the drain of the mos transistor P7 are electrically connected to the gate of the mos transistor P9 and the source of the mos transistor P8. The grid electrode and the drain electrode of the mos transistor P8 are electrically connected with the grid electrode of the mos transistor P10, one end of a resistor R3 and the emitter electrode of a triode Q4, the other end of the resistor R3 is electrically connected with the base electrode of the triode Q4, the drain electrode of the mos transistor N11 and the grid electrode, and the collector electrode of the triode Q4 and the source electrode of the mos transistor N11 are grounded.

In this embodiment, the low temperature drift current generating module generates a low temperature drift current I _o, which is "zero temperature coefficient current". The VBE4 of the triode Q4 has a fixed temperature coefficient, after the sizes of the mos tube P7 and the mos tube P8 are fixed, a resistor with a proper type and a proper resistance value is selected to compensate the change of the VBE4, so that low-temperature drift current can be obtained, if smaller low-temperature drift current is required to be obtained, the size of the mos tube P7 is reduced, and then the proper resistor R3 is selected for the size of the mos tube P8.

Referring to fig. 4, fig. 4 is a graph showing a change of low-temperature drift current I _o1 with temperature under direct current, wherein the maximum change value of the current is 65nA within the range of-40 ℃ to 180 ℃ as can be seen from the graph, and the maximum change value is obtained by a temperature drift coefficient formula:

Referring to fig. 5, fig. 5 is a graph showing a transient temperature scan experiment of the low temperature drift current I _o1, in which the change between I _o1 at 20 ℃ per step can be seen, which is substantially the same as that in fig. 4 of the dc simulation.

Referring to fig. 6, fig. 6 is a graph showing the change of the generated low temperature drift current I _o2 with temperature after reducing the size of the mos tube P7 and changing the resistance value of the resistor R3, wherein the maximum change value of the low temperature drift current I _o2 is 45nA within the range of-40 ℃ to 180 ℃ as can be seen in the graph, and the maximum change value is obtained by a temperature drift coefficient formula:

The sources of the mos transistors P9 and P11 are electrically connected to an external power source. The drain of mos transistor P9 is electrically connected to the source of mos transistor P10. The drain electrode and the grid electrode of the mos tube P11 are electrically connected with the source electrode, the thermal derating module and the over-temperature protection module of the mos tube P12. The drain electrode of the mos transistor P10 is electrically connected with the drain electrode of the mos transistor N12, the gate electrode of the mos transistor N14, the thermal derating module and the over-temperature protection module. The drain electrode and the grid electrode of the mos tube P12 are electrically connected with the drain electrode of the mos tube N14, the thermal derating module and the over-temperature protection module. The source electrode of the mos transistor N12 is electrically connected with the drain electrode and the grid electrode of the mos transistor N13, the grid electrode of the mos transistor N15, the thermal derating module and the over-temperature protection module. The source electrode of the mos transistor N14 is electrically connected with the drain electrode of the mos transistor N15. The source of mos transistor N13 and the source of mos transistor N15 are grounded.

And a current mirror circuit is arranged to generate proper I _PTAT and I _o current, so that the current mirror unit copy current of the subsequent low-temperature drift I _o current is changed, and the trimming and characteristic adjustment are facilitated.

In this embodiment, (W/L) _N12：(W/L)_N14=(W/L)_N13：(W/L)_N15 =n, in order to make the current mirror replicate more accurately, the current mirror adopts a cascode structure of an inverted ratio tube, resulting in a scaled down or amplified replication current:

Since the temperature coefficient of the I _PTAT after passing through the current mirror will change, the quantized translation I _PTAT can be realized by adding or subtracting a zero temperature coefficient current, please refer to fig. 7, fig. 7 is a simulation diagram of current scaling of the low temperature drift I _o; from the graph, it can be seen that the current of the current I _o after scaling by multiple maintains the low temperature drift characteristic.

The thermal derating module comprises a thermal derating point determining circuit and a derating curve slope modulating circuit; the power input ends of the thermal derate point determining circuit and the derate curve slope modulating circuit are electrically connected with an external power supply, the thermal derate point determining circuit is electrically connected with the output ends of the I _o scaling circuit and the I _PTAT scaling circuit, and the output end of the thermal derate point determining circuit is electrically connected with the derate curve slope modulating circuit; the derating curve slope modulation circuit is electrically connected between the band gap reference circuit and the thermal derating point determining circuit.

The thermal derating point determining circuit comprises a mos pipe P17, a mos pipe P18, a mos pipe P19, a mos pipe P20, a mos pipe P21, a mos pipe P22, a mos pipe P23, a mos pipe P24, a mos pipe N20, a mos pipe N21, a switch K1, a switch K2 and a switch K3;

The derating curve slope modulation circuit comprises a mos tube N1, a mos tube N2, a mos tube N3, a mos tube N4, a mos tube N5, a mos tube N6, a mos tube N7, a mos tube N8, a mos tube N9, a mos tube N10, a switch K7, a switch K8 and a switch K9.

The sources of the mos transistors P17, P19, P21 and P23 are electrically connected with an external power supply, and the grid of the mos transistor P17 is electrically connected with the I _PTAT scaling circuit and the over-temperature protection module, namely the grid of the mos transistor P17 is electrically connected with the grid, the drain and the over-temperature protection module of the mos transistor P15. The gates of the mos transistors P19, P21 and P23 are electrically connected with the I _o scaling circuit and the over-temperature protection module, i.e. the gates of the mos transistors P19, P21 and P23 are electrically connected with the gates, the drains and the over-temperature protection module of the mos transistor P11. The drains of the mos transistors P17, P19, P21 and P23 are electrically connected to the sources of the mos transistors P18, P20, P22 and P24, respectively. The grid electrode of the mos transistor P18 is electrically connected with the I _PTAT scaling circuit and the over-temperature protection module, namely, the grid electrode of the mos transistor P18 is electrically connected with the grid electrode, the drain electrode and the over-temperature protection module of the mos transistor P16. The gates of the mos transistors P20, P22 and P24 are electrically connected with the I _o scaling circuit and the over-temperature protection module, i.e. the gates of the mos transistors P20, P22 and P24 are electrically connected with the gates, the drains and the over-temperature protection module of the mos transistor P12.

Drains of the mos transistors P20, P22 and P24 are respectively electrically connected with one ends of the switches K1, K2 and K3; the drain electrode of the mos transistor P18 is electrically connected with the derating curve slope modulation circuit, the drain electrode of the mos transistor N20, the other ends of the switch K1, the switch K2 and the switch K3, namely, the drain electrode of the mos transistor P18 is electrically connected with the gate electrode of the mos transistor N1, the gate electrode of the mos transistor N3, the gate electrode of the mos transistor N5, the gate electrode of the mos transistor N7, the gate electrode of the mos transistor N9, the drain electrode of the mos transistor N20, the other ends of the switch K1, the switch K2 and the switch K3.

The grid electrode of the mos transistor N20 is electrically connected with the I _o scaling circuit and the over-temperature protection module, namely, the grid electrode of the mos transistor N20 is electrically connected with the drain electrode of the mos transistor N12, the grid electrode of the mos transistor N14 and the over-temperature protection module. The source electrode of the mos tube N20 is electrically connected with the drain electrode of the mos tube N21, the grid electrode of the mos tube N21 is electrically connected with the I _o scaling circuit and the over-temperature protection module, namely, the grid electrode of the mos tube N21 is electrically connected with the drain electrode of the mos tube N13, the grid electrode of the mos tube N15 and the over-temperature protection module, and the source electrode of the mos tube N21 is grounded. The thermal derate point determining circuit forms a current sum circuit, each current mirror current branch is connected to a node, and the current of each branch can be summed at the node according to KCL theorem. When the switch K1, the switch K2 and the switch K3 are closed, the working temperature range of the circuit is set between-40 ℃ and 180 ℃.

PMOS provides current down to the current source as:

The current provided by the NMOS for the current sink receiving upper side is noted as:

I _N-all is zero temperature coefficient current and I _P-all is positive temperature coefficient current, I _P-all at-40 ℃ is set smaller than I _N-all, then as temperature rises, I _P-all must exceed I _N-all at a temperature that causes the PMOS current source to provide excess current from the node to the branches of mos transistor N9 and mos transistor N10, denoted as Δi, which strips away a portion of the current applied to resistor R2 in the bandgap reference through the current mirror formed by mos transistor N9, mos transistor N10, and the subsequent mos transistor to change the V _REF voltage:

The linear LED drives the voltage drop of the low dropout regulator V _REF to determine the constant value resistor:

Therefore, the LED power control device can linearly reduce the output power of the LED at high temperature.

Referring to fig. 8, fig. 8 is a simulation diagram of a variable thermal derating point, I _P-all、I_N-all is a current linearly varying with temperature, and the derating temperature point is determined by an intersection point of two current functions of I _P-all and I _N-all varying with temperature, and a zero temperature coefficient current is connected in parallel to a current source according to a quantization ratio to increase or decrease I _{P-all Or (b)}I_N-all, and the current function is shifted correspondingly to change the thermal derating point.

The output end of the band gap reference circuit is electrically connected with one end of the switch K7, the switch K8 and the switch K9 and the drain electrode of the mos tube N7, namely, the grid electrode and the drain electrode of the mos tube NR are electrically connected with one end of the switch K7, the switch K8 and the switch K9 and the drain electrode of the mos tube N7. The other end of the switch K7 is electrically connected with the drain electrode of the mos tube N5, the other end of the switch K8 is electrically connected with the drain electrode of the mos tube N3, and the other end of the switch K9 is electrically connected with the drain electrode of the mos tube N1; the grid electrode of the mos tube N1 is electrically connected with the grid electrode of the mos tube N3, the grid electrode of the mos tube N5, the grid electrode of the mos tube N7, the grid electrode and the drain electrode of the mos tube N9 and the drain electrode of the mos tube P18. The source of the mos transistor N1 is electrically connected to the drain of the mos transistor N2. The grid electrode of the mos tube N2 is electrically connected with the grid electrode of the mos tube N4, the grid electrode of the mos tube N6, the grid electrode of the mos tube N8, the source electrode of the mos tube N9, the grid electrode of the mos tube N10 and the drain electrode. The sources of the mos transistors N3, N5 and N7 are respectively and electrically connected with the drains of the mos transistors N4, N6 and N8; the sources of the mos transistors N2, N4, N6, N8 and N10 are all grounded.

The rate at which the LED power drops depends on the slope of the I _leakage current, as the power begins to drop:

the de-rated LED power can be obtained from the above:

Referring to fig. 9, fig. 9 is a simulation diagram of a variable thermal derating slope. The faster I _leakage changes with temperature, the faster the power drops, and since DeltaI is a function derived from the thermal derating point, the current function I _leakage obtained by scaling the current mirror will not translate because the current at the derating point is always 0, so the slope is changed, thus controlling the slope of the power drop.

The over-temperature protection module comprises an over-temperature protection circuit, a trigger circuit and an inverter circuit, wherein the input end of the over-temperature protection circuit is electrically connected with the output ends of the I _o scaling circuit and the I _PTAT scaling circuit, the output end of the over-temperature protection circuit is electrically connected with the trigger circuit, the trigger circuit is connected with the inverter circuit, and the inverter circuit outputs OTP signals to the driving control module of the external LED linear driving unit and the feedback input end of the over-temperature protection circuit.

The over-temperature protection circuit comprises a mos tube P25, a mos tube P26, a mos tube P27, a mos tube P28, a mos tube P29, a mos tube P30, a mos tube P31, a mos tube P32, a mos tube N22, a mos tube N23, a switch K4, a switch K5 and a switch K6.

The flip-flop circuit includes a mos transistor P33, a mos transistor P34, a mos transistor P35, a mos transistor N24, a mos transistor N25, and a mos transistor N26.

The inverter circuit includes mos transistor P36 and mos transistor N27.

The sources of the mos transistors P25, P27, P29, and P31 are electrically connected to an external power source. The grid electrode of the mos transistor P25 is electrically connected with the I _PTAT scaling circuit and the thermal deration point determining circuit, namely, the grid electrode of the mos transistor P25 is electrically connected with the grid electrode and the drain electrode of the mos transistor P15, the source electrode of the mos transistor P16 and the grid electrode of the mos transistor P17. The gates of the mos transistors P27, P29 and P31 are electrically connected to the I _o scaling circuit and the thermal deration point determining circuit, i.e. the gates of the mos transistors P27, P29 and P31 are electrically connected to the gate and drain of the mos transistor P11, the source of the mos transistor P12, the gate of the mos transistor P19, P21 and P23.

The drains of the mos transistors P25, P27, P29, and P31 are electrically connected to the sources of the mos transistors P26, P28, P30, and P32, respectively.

The gate of the mos transistor P26 is electrically connected with the I _PTAT scaling circuit and the thermal deration point determining circuit, namely, the gate of the mos transistor P26 is electrically connected with the gate and the drain of the mos transistor P16, the drain of the mos transistor N18 and the gate of the mos transistor P18. The gates of the mos transistors P28, P30 and P32 are electrically connected with the I _o scaling circuit and the thermal derating point determining circuit, i.e. the gates of the mos transistors P28, P30 and P32 are electrically connected with the gate and drain of the mos transistor P12, the drain of the mos transistor N14, the gate of the mos transistor P20, P22 and P24.

The drain electrode of the mos transistor P26 is electrically connected with the drain electrode of the mos transistor N22, the source electrode of the mos transistor NS and the trigger circuit, i.e., the drain electrode of the mos transistor P26 is electrically connected with the drain electrode of the mos transistor N22, the source electrode of the mos transistor NS, the gate electrode of the mos transistor P33, the gate electrode of the mos transistor P34, the gate electrode of the mos transistor N24 and the gate electrode of the mos transistor N25.

The drains of the mos transistors P28, P30 and P32 are electrically connected with one ends of the switches K4, K5 and K6 respectively, the other ends of the switches K4, K5 and K6 are electrically connected with the drain of the mos transistor NS, and the gate of the mos transistor NS is electrically connected with the inverter circuit, i.e. the gate of the mos transistor NS is electrically connected with the drain of the mos transistor P36 and the drain of the mos transistor N27.

The grid electrode of the mos transistor N22 is electrically connected with the I _o scaling circuit and the thermal deration point determining circuit, namely, the grid electrode of the mos transistor N22 is electrically connected with the grid electrode, the drain electrode, the grid electrode of the mos transistor N14 and the grid electrode of the mos transistor N20. The source electrode of the MOS transistor N22 is electrically connected with the drain electrode of the MOS transistor N23, and the gate electrode of the MOS transistor N23 is electrically connected with the I _o scaling circuit and the thermal deration point determining circuit, i.e., the gate electrode of the MOS transistor N23 is electrically connected with the drain electrode and the gate electrode of the MOS transistor N13, the gate electrode of the MOS transistor N15 and the gate electrode of the MOS transistor N21. The source of mos transistor N23 is grounded.

The source of the mos transistor P34 and the drain of the mos transistor N26 are electrically connected to an external power source, and the gate of the mos transistor P34 is electrically connected to the gate of the mos transistor P33, the gate of the mos transistor N24, the gate of the mos transistor N25, and the drain of the mos transistor P26. The drain of mos transistor P34 is electrically connected to the source of mos transistor P33 and the source of mos transistor P35. The drain electrode of the mos transistor P33 is electrically connected with the gate electrode of the mos transistor P35, the drain electrode of the mos transistor N24, the gate electrode of the mos transistor N26, and the inverter circuit, that is, the drain electrode of the mos transistor P33 is electrically connected with the gate electrode of the mos transistor P35, the drain electrode of the mos transistor N24, the gate electrode of the mos transistor N26, the gate electrode of the mos transistor P36, and the gate electrode of the mos transistor N27. The source electrode of the mos transistor N24 is electrically connected with the drain electrode of the mos transistor N25 and the source electrode of the mos transistor N26, and the drain electrode of the mos transistor P35 and the source electrode of the mos transistor N25 are grounded.

The drain electrode of the mos tube P36 is electrically connected with an external power supply, the grid electrode of the mos tube P36 is electrically connected with the grid electrode of the mos tube N27 and the drain electrode of the mos tube P33, the drain electrode of the mos tube P36 is electrically connected with the drain electrode of the mos tube N27 and the grid electrode of the mos tube NS, and the drain electrode of the mos tube P36 is electrically connected with a driving control module of an external LED linear driving unit as an OTP interface; the source of mos transistor N27 is grounded.

When there are two current sources on a branch, the current of the branch is determined by the smaller current source, and the rule mapped to the circuit consisting of mos transistors can be expressed as: when two mos transistor current sources in a saturation region are arranged on the same branch, if the Id currents of the two mos transistors are different, the mos transistor providing larger Id current enters a linear region, but because the mos transistor has a second-order effect (channel length modulation effect), the saturation current is not constant but has a certain slope as can be known from the infinite voltage, if the ro resistance of the mos transistor is increased when the mos transistor is saturated, the current curve of the two mos transistors when the mos transistor is saturated is flatter, the intersection range of the two saturation currents is smaller, that is, the two mos transistor current sources are more likely to collide, so that a common-source common-gate structure of the inverted ratio transistor is adopted.

The common-source common-gate current source I _P25、I_N22 is connected to the same node, no other current path exists in the node, I _N22 is zero-temperature coefficient current, I _P25 is positive-temperature coefficient current, I _P25 at the temperature of minus 40 ℃ is set smaller than I _N22, so that the common-source common-gate current source of the mos tube P25 and the mos tube P26 collides with the common-source common-gate current source of the mos tube N22 and the mos tube N23, the larger current sources of the mos tube N22 and the mos tube N23 are forced to enter a linear region so that the node voltage is expressed as low level, and the node voltage is overturned by I _P25 which is certainly exceeding I _N22 at a certain temperature along with the temperature rise, so that the external LED module is turned off.

Referring to fig. 10, fig. 10 is a simulation diagram of current source collision and OTP state flip transient temperature scan, and fig. 10 shows that the I _P25 current starts to collide and deviate from the rule of the current increase with temperature at 172 ℃ and OTP is flipped accurately at this time.

Referring to fig. 11, fig. 11 is a simulation diagram of the current source and OTP state change with temperature under dc, and it can be seen from fig. 11 that the dc simulation result is consistent with the transient simulation result.

To avoid thermal oscillations, a positive feedback mos transistor NS is introduced, the mos transistor NS is turned on after an OTP event occurs, and a zero temperature coefficient current I _NS, which introduces additional feedback to the PMOS current source, translates the PMOS current curve upward to form a temperature hysteresis curve.

Referring to fig. 11 and 12, fig. 12 is a hysteresis simulation graph of the OTP after the feedback current is set to I _K4. The hysteresis state of the OTP when no hysteresis current is added, i.e., the hysteresis is 0, is shown in fig. 11, and when the current source I _K4 of the K4 switch leg is added through feedback, a certain hysteresis occurs as shown in fig. 12.

The switch K1, the switch K2, the switch K3, the switch K4, the switch K5, the switch K6, the switch K7, the switch K8 and the switch K9 control whether the corresponding branch current sources are connected with the nodes or not, and more PMOS current sources or NMOS current sinks can be additionally added. The current source of the trimming branch circuit is set with current proportion according to practical condition consideration, and the FUSE resistor trimming circuit controls the current sources of the branch circuits and the current sink switch, so that parameter trimming in a certain range can be realized. Similar to the trimming principle, the characteristics of the circuit are to be freely adjusted through the LOGIC circuit, and then the current proportion of the current source for adjusting parameters is set, and the corresponding branch switch is connected into the LOGIC circuit to realize the change of the derating point, the overtemperature point and the hysteresis quantity through controllable LOGIC signals.

Referring to fig. 13-15, the original I _P25 current is denoted as I _{P25_0}, the LOGIC closes the switch K, the I _K current is increased and then denoted as I _{P25_1}, and so on. Taking OTP over-temperature point adjustment as an example, assume that K4, K5, and K6 current branches (I _K4=I_K5=I_K6) are connected in parallel to an I _P25 current source, and sequentially turn off and turn on to increase I _P25, resulting in a gradually increasing I _{P25_1}、I_{P25_2}、I_{P25_3}. FIG. 13 is a simulation graph of the current source I _P25 incorporated into I _K4 to yield I _{P25_1}; FIG. 14 is a simulation graph of the current source I _P25 incorporated into I _K4、I_K5 to yield I _{P25_2}; fig. 15 is a simulation graph of I _{P25_3} obtained after the current source I _P25 is incorporated into I _K4、I_K5、I_K6. The OTP inversion points corresponding to I _{P25_1}、I_{P25_2} and I _{P25_3} in fig. 13-15 are shown in fig. 16, i.e. fig. 16 is a simulation diagram of the OTP inversion point change after quantization current adjustment. It can be seen from fig. 16 that the more current branches are incorporated, the greater the amount of change in the switching point.

Referring to fig. 17, taking over-temperature protection hysteresis adjustment as an example, the current branches (I _K4=I_K5=I_K6) of K4, K5 and K6 are connected in parallel to the current source of the feedback, and the switch is sequentially closed to obtain a simulation graph of I _{NS_1}、I_{NS_2}、I_{NS_3} that gradually increases, as shown in fig. 17, as the integrated current branch increases, the hysteresis also increases.

Referring to fig. 18, through presetting the variation of the derating slope corresponding to each current branch, when the temperature reaches T1, the LED power is reduced by K1 slope until the temperature reaches T2, the first switch is closed, the derating slope is increased to K2 by incorporating the set first current until the temperature reaches T3, the second switch is opened, and the derating slope is increased to K3 by incorporating the set second current until the temperature reaches T4, so as to trigger the OTP event, thereby realizing different power reduction capabilities in segments in different temperature ranges.

In the embodiment, the thermal derating module and the over-temperature protection module are realized by adopting a current technology, and the current copied by the current mirror is I _PTAT and I _o which are related to the number proportion of the mos tubes, so that the thermal derating characteristic and the over-temperature protection characteristic are related to the number proportion of the mos tubes only, and devices such as a comparator and a switch tube are not needed, and the circuit structure adopts a common-source common-gate structure formed by the inverted ratio tubes, so that the circuit has good precision.

The present invention is not limited to the above-mentioned embodiments, and any changes or substitutions that can be easily understood by those skilled in the art within the technical scope of the present invention are intended to be included in the scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. The LED linear driving thermal derating and over-temperature protection system is characterized by comprising a V _REF&I_PTAT generation module, a low-temperature drift current generation module, a thermal derating module and an over-temperature protection module; the V _REF&I_PTAT generation module outputs a reference voltage V _REF to a positive input end of an operational amplifier of an external LED linear driving unit, the V _REF&I_PTAT generation module outputs a positive temperature coefficient current I _PTAT, the I _PTAT current is reduced or amplified and then is output to the thermal derating module and the over-temperature protection module, and the V _REF&I_PTAT generation module outputs a modulation current to the thermal derating module;

2. The LED linear-drive thermal derating and overtemperature protection system of claim 1, wherein: the V _REF&I_PTAT generating module comprises a starting circuit, a band gap reference circuit and an I _PTAT scaling circuit, wherein the power input ends of the starting circuit, the band gap reference circuit and the I _PTAT scaling circuit are electrically connected with an external power supply, the output end of the starting circuit is electrically connected with the input end of the band gap reference circuit, the starting circuit controls the band gap reference circuit to generate a reference voltage V _REF and a positive temperature coefficient current I _PTAT,

3. The LED linear-drive thermal derating and overtemperature protection system of claim 2, wherein: the low-temperature drift current generation module comprises a low-temperature drift current generation circuit and an I _o scaling circuit, wherein the power input ends of the low-temperature drift current generation circuit and the I _o scaling circuit are electrically connected with an external power supply, the output end of the low-temperature drift current generation circuit is electrically connected with the input end of the I _o scaling circuit, and the output end of the I _o scaling circuit is electrically connected with the thermal derating module and the over-temperature protection module.

4. The LED linear-drive thermal derating and overtemperature protection system of claim 3, wherein: the thermal derating module comprises a thermal derating point determining circuit and a derating curve slope modulating circuit;

5. The LED linear-drive thermal derating and overtemperature protection system of claim 4, wherein: the over-temperature protection module comprises an over-temperature protection circuit, a trigger circuit and an inverter circuit, wherein the power input ends of the over-temperature protection circuit, the trigger circuit and the inverter circuit are electrically connected with an external power supply, the input ends of the over-temperature protection circuit are electrically connected with the output ends of the I _o scaling circuit and the I _PTAT scaling circuit, the output end of the over-temperature protection circuit is electrically connected with the input end of the trigger circuit, the output end of the trigger circuit is electrically connected with the input end of the inverter circuit, and the inverter circuit outputs OTP signals to the driving control module of the external LED linear driving unit and the feedback input end of the over-temperature protection circuit.

6. The LED linear-drive thermal derating and overtemperature protection system of claim 5, wherein: the low-temperature drift current generation circuit comprises a mos tube P7, a mos tube P8, a mos tube N11, a triode Q4 and a resistor R3;

7. The LED linear-drive thermal derating and overtemperature protection system of claim 5, wherein: the thermal derate point determining circuit comprises a mos pipe P17, a mos pipe P18, a mos pipe P19, a mos pipe P20, a mos pipe P21, a mos pipe P22, a mos pipe P23, a mos pipe P24, a mos pipe N20, a mos pipe N21, a switch K1, a switch K2 and a switch K3;

8. The LED linear-drive thermal derating and overtemperature protection system of claim 7, wherein: the derating curve slope modulation circuit comprises a mos tube N1, a mos tube N2, a mos tube N3, a mos tube N4, a mos tube N5, a mos tube N6, a mos tube N7, a mos tube N8, a mos tube N9, a mos tube N10, a switch K7, a switch K8 and a switch K9;

9. The LED linear-drive thermal derating and overtemperature protection system of claim 5, wherein: the over-temperature protection circuit comprises a mos tube P25, a mos tube P26, a mos tube P27, a mos tube P28, a mos tube P29, a mos tube P30, a mos tube P31, a mos tube P32, a mos tube N22, a mos tube N23, a mos tube NS, a switch K4, a switch K5 and a switch K6;

10. The LED linear-drive thermal derating and overtemperature protection system of claim 9, wherein: the trigger circuit comprises a mos pipe P33, a mos pipe P34, a mos pipe P35, a mos pipe N24, a mos pipe N25 and a mos pipe N26;

11. The LED linear-drive thermal derating and overtemperature protection system of claim 10, wherein: the inverter circuit comprises a mos pipe P36 and a mos pipe N27;