CN117879582A

CN117879582A - Interface circuit and method for supporting forward and negative pressure MLVDS signal receiving and transmitting

Info

Publication number: CN117879582A
Application number: CN202311743024.1A
Authority: CN
Inventors: 张溢华; 田泽; 刘颖; 吕俊盛; 李潇
Original assignee: Xian Xiangteng Microelectronics Technology Co Ltd
Current assignee: Xian Xiangteng Microelectronics Technology Co Ltd
Priority date: 2023-12-18
Filing date: 2023-12-18
Publication date: 2024-04-12

Abstract

The invention relates to an interface circuit and a method for receiving and transmitting MLVDS signals supporting positive and negative pressure. The invention adopts the mode of connecting the PMOS tube and the NMOS tube in series to realize the interface circuit, can realize the functions, can be widely applied to various processes, and has higher applicability and universality.

Description

Interface circuit and method for supporting forward and negative pressure MLVDS signal receiving and transmitting

Technical Field

The invention belongs to the field of integrated circuits, and particularly relates to an interface circuit and a method for receiving and transmitting MLVDS signals supporting positive and negative pressure.

Background

MLVDS (multi-point LVDS) is a similar standard for multi-point applications. The MLVDS uses differential signals and the receiving circuit will detect data from the voltage difference between two complementary electrical signals. This can greatly improve noise immunity and minimize noise emissions. The MLVDS bus may transmit a positive voltage above VDD and may transmit a negative voltage below GND.

For half-duplex transceiver chips, the gate terminal is connected to the bus line as a receiving circuit without leakage, but the drain terminal is connected to the bus line as a transmitting circuit with leakage. When the chip operates as a receiving circuit, transmitting the voltage on the MLVDS bus, the transmitting circuit in the chip needs to be completely turned off from the bus to avoid generating a large leakage current. When the chip is powered down, signal transmission still exists on the MLVDS bus, and the signal transmission also needs to be turned off inside the chip, so that leakage current is avoided. Meanwhile, because the transmission voltage on the bus is lower than GND and higher than VDD, a special ESD protection circuit is also needed to ensure the normal operation of the circuit.

In a traditional MLVDS driver circuit, the substrate of a PMOS switch tube receives the highest potential VDD, when the power supply of the circuit is powered down, the voltage on a bus can be potentially connected to the power supply VDD through the drain-substrate parasitic diode of the PMOS tube, and current is leaked from the bus to the VDD, so that the power supply cannot be powered down normally. After improvement, an interface circuit is added, a PMOS tube under a special process is adopted, and the substrate is suspended, so that leakage current flowing into the driver can not be generated when the chip is powered down. However, in the common process, when the chip is powered down, the PMOS transistor is turned on, and a signal is transmitted to the inside of the transmitting circuit, so that leakage current of hundreds of milliamperes can be generated, and the transmission of the signal on the bus is affected. The method has high process requirements and is difficult to apply under common processes.

Disclosure of Invention

In order to solve the technical problems in the background art, the invention provides the interface circuit and the method for supporting the forward and negative pressure MLVDS signal receiving and transmitting, which adopt a mode of connecting PMOS tubes and NMOS tubes in series to realize the interface circuit, can realize the functions and can be widely applied to various processes, and have higher applicability and universality.

The technical scheme of the invention is as follows: the invention relates to an interface circuit supporting forward and negative pressure MLVDS signal receiving and transmitting, which is characterized in that: the interface circuit supporting the forward and negative pressure MLVDS signal receiving and transmitting comprises a transmitting circuit, a receiving circuit and an interface circuit, wherein the interface circuit comprises a PMOS tube and an NMOS tube, the transmitting circuit comprises an NMOS tube, the NMOS tube is connected with the PMOS tube in series, and the PMOS tube is connected with the receiving circuit.

Further, the PMOS tube is selected from a 5V voltage-resistant PMOS tube, the NMOS tube is selected from a 3.3V voltage-resistant independent trap DNNMOS tube, the grid electrode of the DNNMOS tube is connected with an enable end EN, the grid electrode of the PMOS tube is connected with an enable end nEN, the substrates of the PMOS tube and the DNNMOS tube are connected with source ends, and the deep N trap potential of the DNNMOS tube is connected with the highest potential VDD of the chip.

Further, the device also comprises an ESD circuit which is connected between the PMOS tube and the receiving circuit.

Further, the ESD circuit is formed by connecting three reverse biased diodes in parallel with six forward biased diodes.

The method for realizing the interface circuit supporting the forward and negative pressure MLVDS signal receiving and transmitting is characterized by comprising the following steps of: the method comprises the following steps:

1) When the chip works as a transmitting circuit, the receiving circuit is turned off, the interface circuit is required to be turned on, normal output of signals is guaranteed, EN is high level, nEN is low level, the PMOS tube and the NMOS tube are both turned on, and at the moment, the chip normally outputs signals;

2) When the chip works as a receiving circuit and the sending circuit is turned off, the MLVDS bus transmits-1.4-3.8V voltage, the interface circuit needs to be turned off, so that the sending circuit and the bus in the chip have no transmission path to avoid generating larger leakage current, EN is low level, nEN is high level, the PMOS tube and the NMOS tube are turned off, at the moment, the bus transmits-1.4-3.8V voltage, and the signal is not transmitted to the sending circuit but transmitted to the receiving circuit;

3) When the chip is powered down, the transmitting circuit and the receiving circuit are both turned off; the bus and the transmitting circuit need not to have a passage, so that leakage current is avoided; EN and nEN are both low level, the PMOS tube is on, and the NMOS tube is off, so that no matter what signal is transmitted on the bus, the signal cannot be transmitted into the transmitting circuit.

Furthermore, step 3) is followed by step 4) of connecting the ESD circuit to ESD protect the voltage.

Further, in step 4), the ESD protection circuit adopts a mode of connecting three reverse-biased diodes with six forward-biased diodes in parallel, the turn-on voltage of the three reverse-biased diodes is lower than-2.1V, and the turn-on voltage of the six forward-biased diodes is higher than 4.2V, so as to realize ESD protection with-1.4-3.8V.

When the chip works as a receiving circuit and transmits-1.4-3.8V voltage on the MLVDS bus, the transmitting circuit in the chip needs to be completely shut off with the bus to avoid generating larger leakage current. Meanwhile, because the transmission voltage on the bus is lower than GND and higher than VDD, a special ESD protection circuit is also needed to ensure the normal operation of the circuit. When the chip is powered down, signal transmission still exists on the MLVDS bus, and the signal transmission also needs to be turned off inside the chip, so that leakage current is reduced. The interface circuit and the method for receiving and transmitting the MLVDS signal supporting the positive and negative pressure, provided by the invention, adopt a mode of connecting the PMOS tube and the NMOS tube in series to form the interface circuit, can realize the functions, can be widely applied to various processes, and has higher applicability and universality. The interface circuit selects a PMOS tube with 5V withstand voltage and a DNNMOS tube with 3.3V withstand voltage to be connected in series. In order to reduce the voltage drop of the MLVDS output signal, according to layout area constraint, selecting as many MOS tubes as possible to be connected in parallel to reduce the on-resistance of the switching tube. The substrates of PMOS and DNNMOS in the circuit are connected with the source end, and the deep N-well potential of DNNMOS is connected with the highest potential VDD of the chip. Meanwhile, because the transmission voltage on the bus is lower than GND and higher than VDD, a special ESD protection circuit is also needed to ensure the normal operation of the circuit. The ESD circuit adopts a mode that three reverse diodes are connected with six positive diodes in parallel, and can realize ESD protection of-1.4-3.8V voltage.

Drawings

Fig. 1 is a circuit configuration diagram of the present invention.

Detailed Description

The invention is described in further detail below with reference to the attached drawings and to specific embodiments:

referring to fig. 1, in an embodiment of the present invention, the chip is divided into a transmitting circuit and a-1.4 to 3.8V receiving circuit, and shares an I/O port. The ports are input ports of the receiving circuit and output ports of the transmitting circuit. When the chip works as a receiving circuit, the port is an input end, the interface circuit is required to be turned off, and a signal flows to the receiving circuit; when the chip works as a transmitting circuit, the port is an output end, the interface circuit is required to be conducted, and signals flow to the bus from the transmitting circuit.

The interface circuit selects a PMOS tube with 5V withstand voltage and a DNNMOS tube with 3.3V withstand voltage to be connected in series. In order to reduce the voltage drop of the MLVDS output signal, according to layout area constraint, as many MOS tubes as possible are selected to be connected in parallel so as to reduce the on-resistance of the switching tube. In the circuit, the grid electrode of the NNMOS tube is connected with an enabling end EN, the grid electrode of the PMOS tube is connected with an enabling end nEN, the substrates of the PMOS tube and the DNNMOS tube are both connected with source ends, and the potential of a deep N well of the DNNMOS tube is connected with the highest potential VDD of the chip.

The invention also provides a method for realizing the interface circuit supporting the forward and negative pressure MLVDS signal receiving and transmitting, which comprises the following steps:

1) When the chip works as a transmitting circuit, the receiving circuit is turned off. The interface circuit needs to be conducted to ensure the normal output of the signal. EN is high level, nEN is low level, and the PMOS tube and the NMOS tube are all conducted. At this time, the chip normally outputs a signal.

2) When the chip works as a receiving circuit, the transmitting circuit is turned off. When the MLVDS bus transmits-1.4-3.8V voltage, the interface circuit needs to be turned off to make the transmission circuit and the bus in the chip have no transmission path so as to avoid generating larger leakage current. EN is low level, nEN is high level, and the PMOS tube and the NMOS tube are both turned off. At this time, a voltage of-1.4 to 3.8V is transmitted on the bus, and the signal is not transmitted to the transmitting circuit but to the receiving circuit.

3) When the chip is powered down, the transmitting circuit and the receiving circuit are both turned off. The bus and the transmitting circuit need to have no passage, so that leakage current is avoided. EN and nEN are both low level, the PMOS tube is on, and the NMOS tube is off, so that no matter what signal is transmitted on the bus, the signal cannot be transmitted into the transmitting circuit.

4) The ESD circuit adopts a mode that three reverse bias diodes are connected with six forward bias diodes in parallel to realize ESD protection of-1.4-3.8V voltage. The on voltage of the three reverse bias diodes is lower than-2.1V, and the on voltage of the six forward bias diodes is higher than 4.2V, so that the protection of the voltage of-1.4-3.8V can be realized.

The technical matters not specifically described in the foregoing embodiments are the same as those in the prior art.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and are not limiting; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. An interface circuit supporting positive and negative pressure MLVDS signal receiving and transmitting, which is characterized in that: the interface circuit supporting the forward and negative pressure MLVDS signal receiving and transmitting comprises a transmitting circuit, a receiving circuit and an interface circuit, wherein the interface circuit comprises a PMOS tube and an NMOS tube, the transmitting circuit is connected with the NMOS tube, the NMOS tube is connected with the PMOS tube in series, and the PMOS tube is connected with the receiving circuit.

2. The interface circuit supporting positive and negative pressure MLVDS signal transceiving according to claim 1, wherein: the PMOS tube is selected to be a 5V withstand voltage PMOS tube, the NMOS tube is selected to be a 3.3V withstand voltage independent trap DNNMOS tube, the grid electrode of the DNNMOS tube is connected with an enable end EN, the grid electrode of the PMOS tube is connected with an enable end nEN, the substrates of the PMOS tube and the DNNMOS tube are both connected with source ends, and the deep N trap potential of the DNNMOS tube is connected with the highest potential VDD of the chip.

3. Interface circuit supporting positive and negative pressure MLVDS signaling according to claim 1 or 2, characterized in that: the interface circuit also comprises an ESD circuit which is connected between the PMOS tube and the receiving circuit.

4. The interface circuit supporting positive and negative pressure MLVDS signal transceiving according to claim 3, wherein: the ESD circuit is formed by connecting three reverse bias diodes and six forward bias diodes in parallel.

5. A method of implementing the interface circuit of claim 1 for supporting positive and negative MLVDS signaling, comprising: the method comprises the following steps:

6. The method of the interface circuit supporting positive and negative pressure MLVDS signal transceiving according to claim 5, wherein: and step 4) is connected with an ESD circuit to carry out ESD protection on the voltage.

7. The method of the interface circuit supporting positive and negative pressure MLVDS signaling according to claim 6, wherein: in the step 4), the ESD protection circuit adopts a mode of connecting three reverse bias diodes and six forward bias diodes in parallel, the turn-on voltage of the three reverse bias diodes is lower than-2.1V, and the turn-on voltage of the six forward bias diodes is higher than 4.2V, so as to realize the ESD protection of-1.4-3.8V.