CN117878212B - Deep ultraviolet LED flip chip and preparation method thereof - Google Patents
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Abstract
The invention belongs to the technical field of LED flip chips, and particularly relates to a deep ultraviolet LED flip chip and a preparation method thereof, wherein an AlN buffer layer grows on a substrate, an n-type semiconductor layer grows on the AlN buffer layer, a quantum well layer grows on the n-type semiconductor layer, a p-type semiconductor layer grows on the quantum well layer, the p-type semiconductor layer is etched until the n-type semiconductor layer exposes out of an n-type semiconductor table top, an n-type contact electrode is arranged on the n-type semiconductor table top, a p-type contact electrode is arranged on the p-type semiconductor layer, the n-type contact electrode and/or the p-type contact electrode are composite electrodes, the n-type composite electrode and the p-type composite electrode both comprise an electrode expansion barrier layer and a reflecting electrode, and the reflecting electrode is evaporated on the electrode expansion barrier layer. The invention blocks migration of Al and prevents the LED flip chip from forming a leakage channel when working under high current and long time.
Description
Technical Field
The invention belongs to the technical field of LED flip chips, and particularly relates to a deep ultraviolet LED flip chip and a preparation method thereof.
Background
Light Emitting Diodes (LEDs) are used as the most potential novel light source, and are widely applied to the fields of illumination, display, polymer curing, sterilization, disinfection, communication and the like due to the characteristics of high light efficiency, low voltage, long service life, small volume, low energy consumption, environmental protection, short response time and the like. In recent years, in the chip field, flip chip technology is protruding in the forensic field, and flip LED chips are popular in the application market and mature gradually due to the advantages of good heat dissipation, low voltage, high brightness, high reliability, and high saturation current density.
In order to improve the light-emitting efficiency, currently, n-contact electrodes and p-contact electrodes of flip-chip LEDs mostly adopt reflective metals such as Al, ag and the like, so that light emitted from an active region can be emitted from a sapphire surface more. However, due to higher mobility of metals such as Al, ag and the like, an electric leakage channel is easy to form when the LED chip works under high current for a long time, so that the device is invalid, and the reliability of the device is greatly influenced.
For another example, the n-type contact electrode commonly used in LEDs has a metal system such as CrAlTiAu, tiAlTiAu, crAlCrPtAu, which typically contains metallic Al. The melting point of Al is 660 ℃, and when ohmic contact is formed by high-temperature rapid annealing, the temperature is generally more than 800 ℃, and at the moment, the metal Al is in a molten overflow state, so that the migration of Al metal due to the fact that the Al metal breaks through the barrier of other metal layers is further increased.
Disclosure of Invention
Aiming at the technical problem that the LED chip is easy to form a leakage channel when working under high current for a long time due to higher mobility of metals such as Al, ag and the like, the invention provides a deep ultraviolet LED flip chip and a preparation method thereof.
In order to solve the technical problems, the invention adopts the following technical scheme:
The preparation method of the deep ultraviolet LED flip chip comprises the following steps:
S1, sequentially preparing an AlN buffer layer, an n-type semiconductor layer, a quantum well layer and a p-type semiconductor layer on the surface of a substrate from bottom to top to form an epitaxial wafer structure;
S2, defining an n-type semiconductor table-board on the p-type semiconductor layer by adopting photoresist on the basis of the S1 structure, etching the n-type semiconductor layer by a dry etching method, and exposing the n-type semiconductor table-board;
S3, respectively preparing contact electrodes on the surfaces of the p-type semiconductor layer and the n-type semiconductor mesa, wherein the contact electrodes are composite electrodes, the composite electrodes comprise one or two of n-type composite electrodes and p-type composite electrodes, the n-type composite electrodes and the p-type composite electrodes comprise an electrode expansion barrier layer and a reflecting electrode, and the reflecting electrode is evaporated on the electrode expansion barrier layer;
s4, sequentially preparing the passivation layer, the conductive through hole and the bonding pad electrode, and thus preparing the deep ultraviolet LED flip chip.
The step S3 specifically comprises the following steps:
S3A, defining an n-type electrode expansion barrier layer in the n-type composite electrode by using photoresist on the basis of the S2 structure, and evaporating the n-type electrode expansion barrier layer on an n-type semiconductor mesa;
S3B, defining an n-reflecting electrode in the n-type composite electrode by using photoresist on the basis of the S3A structure, and evaporating the n-reflecting electrode on the n-type electrode expansion barrier layer;
And S3C, n type composite electrode is annealed at high temperature in nitrogen atmosphere to form n type ohmic contact.
The step S3 specifically comprises the following steps:
s3a, defining a p-type electrode expansion barrier layer in the p-type composite electrode by using photoresist, and evaporating the p-type electrode expansion barrier layer on the p-type semiconductor layer;
s3b, forming p-type ohmic contact between the p-type electrode expansion barrier layer and the epitaxial wafer structure on the basis of the S3a structure;
And S3c, defining a p-type reflecting electrode in the p-type composite electrode by using photoresist on the basis of the S3b structure, and evaporating the p-type reflecting electrode on the p-type electrode expansion barrier layer, wherein the p-type reflecting electrode at least comprises 1 reflecting metal.
The n-type electrode expansion barrier layer in the S3A adopts one or two of metal Cr or Ti, the thickness is 1 nm-20 nm, and the coating rate is 0.2A/S-2A/S; the n-type reflective electrode in S3B comprises at least 1 reflective metal.
The n-reflecting electrode adopts AlTiAu, alTiAuTi, alNiAuTi, alCrPtAu or AlCrPtAuTi reflecting metal system.
The n-type electrode expansion barrier layer in the S3A and the S3B is formed on the upper surface of the n-type semiconductor mesa, and the n-reflection electrode is formed on the upper surface of the n-type electrode expansion barrier layer; the n-type electrode expansion barrier layer is 1 μm to 15 μm larger than the n-reflection electrode width in a direction parallel to the n-type semiconductor mesa.
The annealing temperature of the high-temperature annealing in the S3C is 600-1000 ℃ and the annealing time is 30-400S.
The p-type electrode expansion barrier layers in the S3a, the S3b and the S3c adopt Ni, niAu, niAuNiAu or NiRh metal systems, and the p-reflecting electrode adopts Al, ag, alTi, agTi, alTiAu or AgTiAu reflecting metal systems.
The p-type electrode expansion barrier layer in the S3a, the S3b and the S3c is formed on the upper surface of the p-type semiconductor layer, and the p-reflection electrode is formed on the upper surface of the p-type electrode expansion barrier layer; the p-type electrode expansion barrier layer is 1 μm to 15 μm larger than the p-reflection electrode width in a direction parallel to the p-type semiconductor layer.
The deep ultraviolet LED flip chip comprises a substrate, an AlN buffer layer, an n-type semiconductor layer, a quantum well layer, a p-type semiconductor layer, an n-type contact electrode and a p-type contact electrode, wherein the AlN buffer layer grows on the substrate, the n-type semiconductor layer grows on the AlN buffer layer, the quantum well layer grows on the n-type semiconductor layer, the p-type semiconductor layer grows on the quantum well layer, the p-type semiconductor layer is etched until the n-type semiconductor layer exposes out of an n-type semiconductor table top, the n-type contact electrode is arranged on the n-type semiconductor table top, the p-type contact electrode and/or the p-type contact electrode are/is arranged on the p-type semiconductor layer, the n-type composite electrode and the p-type composite electrode both comprise an electrode expansion barrier layer and a reflecting electrode, and the reflecting electrode is evaporated on the electrode expansion barrier layer.
Compared with the prior art, the invention has the beneficial effects that:
The composite electrode of the present invention includes an electrode expansion blocking layer formed on an upper surface of a semiconductor layer and a reflective electrode formed on an upper surface of the electrode expansion blocking layer. In the direction parallel to the n-type semiconductor mesa, the total width of the n-type electrode expansion barrier layer is larger than the total width of the n-type reflective electrode, migration of Al is blocked, and electric leakage is prevented. The invention can prevent the LED flip chip from forming a leakage channel when working under high current and long time.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below. It will be apparent to those skilled in the art from this disclosure that the drawings described below are merely exemplary and that other embodiments may be derived from the drawings provided without undue effort.
The structures, proportions, sizes, etc. shown in the present specification are shown only for the purposes of illustration and description, and are not intended to limit the scope of the invention, which is defined by the claims, so that any structural modifications, changes in proportions, or adjustments of sizes, which do not affect the efficacy or the achievement of the present invention, should fall within the scope of the invention.
FIG. 1 is a schematic diagram of a light-emitting epitaxial wafer structure of the present invention;
Fig. 2 is a schematic diagram of a chip structure according to the present invention.
Wherein: 101 is a substrate, 102 is an AlN buffer layer, 103 is an n-type semiconductor layer, 104 is a quantum well layer, 105 is a p-type semiconductor layer, 201 is an n-type electrode expansion barrier layer, 202 is an n-reflection electrode, 301 is a p-type electrode expansion barrier layer, and 302 is a p-reflection electrode.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions in the embodiments of the present application will be clearly and completely described below, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments, and these descriptions are only for further illustrating the features and advantages of the present application, not limiting the claims of the present application; all other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The following describes in further detail the embodiments of the present invention with reference to the drawings and examples. The following examples are illustrative of the invention and are not intended to limit the scope of the invention.
In the description of the present application, it should be noted that, unless explicitly specified and limited otherwise, the terms "mounted," "connected," and "connected" are to be construed broadly, and may be either fixedly connected, detachably connected, or integrally connected, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.
Example 1
As shown in fig. 1, an AlN buffer layer 102, an n-type semiconductor layer 103, a quantum well layer 104, and a p-type semiconductor layer 105 are sequentially grown on a sapphire substrate 101 to form an epitaxial wafer structure.
Step two, on the basis of the epitaxial wafer structure in the step one, photoresist is paved on the surface of the p-type semiconductor layer 105 to define the position of an n-type semiconductor mesa, the p-type semiconductor layer 105 is etched to the n-type semiconductor layer 103 by a dry etching method, and the n-type semiconductor mesa is exposed so as to facilitate the preparation of a subsequent contact electrode.
And thirdly, respectively growing contact electrodes on the surfaces of the p-type semiconductor layer 105 and the n-type semiconductor mesa, wherein the contact electrodes are preferably composite electrodes, the composite electrodes comprise one or two of n-type composite electrodes or p-type composite electrodes, the n-type composite electrodes and the p-type composite electrodes comprise an electrode expansion barrier layer and a reflecting electrode, and the reflecting electrode is evaporated on the electrode expansion barrier layer. The composite electrode blocks migration of Al and prevents the LED flip chip from forming a leakage channel when working under high current and long time.
And step four, conventional steps such as manufacturing p-type contact electrodes, passivation layers, conductive through holes and bonding pad electrodes of a chip process are carried out, so that the deep ultraviolet LED flip chip is obtained.
Example two
In the first step, as shown in fig. 1, an AlN buffer layer 102, an n-type semiconductor layer 103, a quantum well layer 104, and a p-type semiconductor layer 105 are grown in this order on a sapphire substrate 101.
Step two, as shown in fig. 2, defining an n-type semiconductor mesa by using photoresist, etching to the n-type semiconductor layer 103 by a dry etching method, and exposing the n-type semiconductor mesa, wherein the etching depth of the n-type semiconductor mesa is 400 nm-900nm. Preferably, the etching depth of the n-type semiconductor mesa is 450nm.
Step three, as shown in fig. 2, defining an n-type electrode expansion barrier layer 201 in the n-type composite electrode by using photoresist, evaporating the n-type electrode expansion barrier layer 201 on an n-type semiconductor mesa, wherein the n-type electrode expansion barrier layer 201 can be one or two of metal Cr and Ti, the thickness is 1 nm-20 nm, and the film coating rate is 0.2A/S-2A/S. Preferably, the n-type electrode expansion barrier layer 201 is metal Ti, the thickness is 5nm, and the coating rate is 0.2A/S.
Cr has a work function of 4.50, ti has a work function of 4.33, and is low, and can form ohmic contact with the n-type semiconductor layer 103 as a barrier layer, and Cr and Ti have a high melting point and low atomic diffusion capability, thereby preventing Al from diffusing to the surface of AlGaN material, and Cr and Ti have good adhesion. Cr and Ti are too thin to form a uniform film during vapor deposition, so that the effect of blocking metal migration cannot be achieved; if the thickness is too thick, the electrode absorbs light.
Step four, as shown in fig. 2, defining an n-type reflecting electrode 202 in the n-type composite electrode by using photoresist, evaporating the n-type reflecting electrode 202 on the n-type electrode expansion barrier layer 201, wherein the n-type reflecting electrode 202 at least comprises 1 kind of reflecting metal, and a AlTiAu, alTiAuTi, alNiAuTi, alCrPtAu, alCrPtAuTi reflection metal system can be selected. Preferably, the n-type contact electrode is AlTiAu.
Further, the total width of the n-type electrode expansion barrier layer 201 is larger than the total width of the n-type reflective electrode 202 in a direction parallel to the n-type semiconductor mesa. The n-type electrode expansion barrier 201 is 1 μm to 15 μm wider than the n-reflective electrode 202, preferably 6 μm, and more preferably 3 μm wider on each side.
And fifthly, carrying out high-temperature annealing on the n-type composite electrode in a nitrogen atmosphere to form n-type ohmic contact, wherein the annealing temperature is 600-1000 ℃ and the annealing time is 30-400 s. Preferably, the high temperature annealing temperature is 850 ℃ and the annealing time is 150s.
Thus, the n-type composite electrode is manufactured.
And then conventional steps of manufacturing p-type contact electrodes, passivation layers, conductive through holes, bonding pad electrodes and the like of the chip process are carried out.
Example III
In the first step, as shown in fig. 1, an AlN buffer layer 102, an n-type semiconductor layer 103, a quantum well layer 104, and a p-type semiconductor layer 105 are grown in this order on a sapphire substrate 101.
Step two, as shown in fig. 2, defining an n-type semiconductor mesa by using photoresist, etching to the n-type semiconductor layer 103 by a dry etching method, and exposing the n-type semiconductor mesa, wherein the etching depth of the n-type semiconductor mesa is 400 nm-900nm. Preferably, the etching depth of the n-type semiconductor mesa is 450nm.
And thirdly, defining an n-type contact electrode by adopting photoresist, evaporating the n-type contact electrode on an n-type semiconductor mesa, wherein the n-type contact electrode can be CrAlTiAu, tiAlTiAu or CrAlCrPtAu. Preferably, tiAlTiAu is used as the n-type contact electrode.
And fourthly, carrying out high-temperature annealing on the n-type contact electrode in a nitrogen atmosphere to form n-type ohmic contact, wherein the annealing temperature is 600-1000 ℃ and the annealing time is 30-400 s. Preferably, the high temperature annealing temperature is 850 ℃ and the annealing time is 150s.
And fifthly, defining a p-type electrode expansion barrier layer 301 in the p-type composite electrode by using photoresist, evaporating the p-type electrode expansion barrier layer 301 on the p-type semiconductor layer 105, wherein the p-type electrode expansion barrier layer 301 can be a Ni, niAu, niAuNiAu, niRh reflecting metal system. Preferably, niRh a corresponding to a thickness of 1 nm/5 nm is used for the p-type electrode expansion barrier 301.
And step six, forming p-type ohmic contact between the p-type electrode expansion barrier layer 301 and the epitaxial wafer structure, and forming ohmic contact by adopting high-temperature annealing or directly contacting at normal temperature without high-temperature annealing. Preferably, ohmic contact is formed by direct contact at normal temperature without high temperature annealing.
The Ni work function is 4.60 and the rh work function is 4.98, and the nirh metal system can directly form ohmic contact with the p-type semiconductor layer 105 without high temperature annealing.
And step seven, defining a p-type reflecting electrode 302 in the p-type composite electrode by using photoresist, evaporating the p-type reflecting electrode 302 on the p-type electrode expansion barrier layer 301, wherein the p-type reflecting electrode 302 at least comprises 1 reflecting metal, and a Al, ag, alTi, agTi, alTiAu, agTiAu reflecting metal system can be selected. Preferably, the p-reflecting electrode 302 is AlTi, and the corresponding thickness is 50nm/10nm.
Further, a p-type electrode expansion barrier layer 301 is formed on the upper surface of the p-type semiconductor layer 105, and a p-reflection electrode 302 layer is formed on the upper surface of the p-type electrode expansion barrier layer 301; the total width of the p-type electrode expansion barrier layer 301 is greater than the total width of the p-reflective electrode 302 in a direction parallel to the p-type semiconductor layer 105. The p-type electrode expansion barrier 301 is 1-15 μm wider than the p-reflective electrode 302, preferably 6 μm wide, and more preferably 3 μm wide on each side.
And then conventional steps such as passivation layer, conductive through hole, pad electrode manufacture and the like of the chip process are carried out.
Example IV
In the first step, as shown in fig. 1, an AlN buffer layer 102, an n-type semiconductor layer 103, a quantum well layer 104, and a p-type semiconductor layer 105 are grown in this order on a sapphire substrate 101.
Step two, as shown in fig. 2, defining an n-type semiconductor mesa by using photoresist, etching to the n-type semiconductor layer 103 by a dry etching method, and exposing the n-type semiconductor mesa, wherein the etching depth of the n-type semiconductor mesa is 400 nm-900nm. Preferably, the etching depth of the n-type semiconductor mesa is 450nm.
Step three, as shown in fig. 2, defining an n-type electrode expansion barrier layer 201 in the n-type composite electrode by using photoresist, evaporating the n-type electrode expansion barrier layer 201 on an n-type semiconductor mesa, wherein the n-type electrode expansion barrier layer 201 can be one or two of metal Cr and Ti, the thickness is 1 nm-20 nm, and the film coating rate is 0.2A/S-2A/S. Preferably, the n-type electrode expansion barrier layer 201 is metal Ti, the thickness is 5nm, and the coating rate is 0.2A/S.
Cr has a work function of 4.50, ti has a work function of 4.33, is low, can form ohmic contact with the n-type semiconductor layer 103 as a barrier layer, has a high melting point and low atomic diffusion capacity, can prevent Al from diffusing to the surface of an AlGaN material, and has good adhesion. Cr and Ti are too thin to form a uniform film during vapor deposition, so that the effect of blocking metal migration cannot be achieved; if the thickness is too thick, the electrode absorbs light.
Step four, as shown in fig. 2, defining an n-type reflecting electrode 202 in the n-type composite electrode by using photoresist, evaporating the n-type reflecting electrode 202 on the n-type electrode expansion barrier layer 201, wherein the n-type reflecting electrode 202 at least comprises 1 kind of reflecting metal, and a AlTiAu, alTiAuTi, alNiAuTi, alCrPtAu, alCrPtAuTi reflection metal system can be selected. Preferably, the n-type contact electrode is AlTiAu.
Further, the total width of the n-type electrode expansion barrier layer 201 is larger than the total width of the n-type reflective electrode 202 in a direction parallel to the n-type semiconductor mesa. The n-type electrode expansion barrier 201 is 1 μm to 15 μm wider than the n-reflective electrode 202, preferably 6 μm, and more preferably 3 μm wider on each side.
And fifthly, carrying out high-temperature annealing on the n-type composite electrode in a nitrogen atmosphere to form n-type ohmic contact, wherein the annealing temperature is 600-1000 ℃ and the annealing time is 30-400 s. Preferably, the high temperature annealing temperature is 850 ℃ and the annealing time is 150s.
And step six, defining a p-type electrode expansion barrier layer 301 in the p-type composite electrode by using photoresist, evaporating the p-type electrode expansion barrier layer 301 on the p-type semiconductor layer 105, wherein the p-type electrode expansion barrier layer 301 can be a Ni, niAu, niAuNiAu, niRh reflecting metal system. Preferably, niRh a corresponding to a thickness of 1 nm/5 nm is used for the p-type electrode expansion barrier 301.
And step seven, forming p-type ohmic contact between the p-type electrode expansion barrier layer 301 and the epitaxial wafer structure, and forming ohmic contact by adopting high-temperature annealing or directly contacting at normal temperature without high-temperature annealing. Preferably, ohmic contact is formed by direct contact at normal temperature without high temperature annealing.
The Ni work function is 4.60 and the rh work function is 4.98, and the nirh metal system can directly form ohmic contact with the p-type semiconductor layer 105 without high temperature annealing.
And step eight, defining a p-type reflecting electrode 302 in the p-type composite electrode by using photoresist, evaporating the p-type reflecting electrode 302 on the p-type electrode expansion barrier layer 301, wherein the p-type reflecting electrode 302 at least comprises 1 reflecting metal, and a Al, ag, alTi, agTi, alTiAu, agTiAu reflecting metal system can be selected. Preferably, the p-reflecting electrode 302 is AlTi, and the corresponding thickness is 50nm/10nm.
Further, a p-type electrode expansion barrier layer 301 is formed on the upper surface of the p-type semiconductor layer 105, and a p-reflection electrode 302 layer is formed on the upper surface of the p-type electrode expansion barrier layer 301; the total width of the p-type electrode expansion barrier layer 301 is greater than the total width of the p-reflective electrode 302 in a direction parallel to the p-type semiconductor layer 105. The p-type electrode expansion barrier 301 is 1 μm to 15 μm wider than the p-reflective electrode 302, preferably 6 μm wide, and more preferably 3 μm wide on each side.
And then conventional steps such as passivation layer, conductive through hole, pad electrode manufacture and the like of the chip process are carried out.
Taking a 20mil by 20mil chip as an example, the deep ultraviolet LED flip chip with the n-type composite electrode of the second embodiment and the deep ultraviolet LED flip chip with the n-type ohmic contact electrode in the prior art are packaged into lamp beads for aging test, and the aging test is carried out at normal temperature and 168 hours under three conditions of 100mA, normal temperature and 200mA, 60 ℃ and 100mA respectively, wherein 1 accompanying sheet and 9 samples are aged on each PCB, the aging leakage current is limited by 1 mu A, and 10 PCBs are aged under each aging condition. Through the test, as shown in table 1, in the comparative example, the deep ultraviolet LED flip chip with the n-type ohmic contact electrode in the prior art is packaged into the lamp bead, and compared with the comparative example, the lamp bead aging and leakage of the lamp bead on which the deep ultraviolet LED flip chip of the second embodiment is mounted are greatly reduced.
Table 1 comparative example and 168h aging test lamp bead leakage statistics table of this example two
The preferred embodiments of the present invention have been described in detail, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of those skilled in the art without departing from the spirit of the present invention, and the various changes are included in the scope of the present invention.
Claims (3)
1. The preparation method of the deep ultraviolet LED flip chip is characterized by comprising the following steps of:
S1, sequentially preparing an AlN buffer layer (102), an n-type semiconductor layer (103), a quantum well layer (104) and a p-type semiconductor layer (105) on the surface of a substrate (101) from bottom to top to form an epitaxial wafer structure;
S2, defining an n-type semiconductor table-board on the p-type semiconductor layer (105) by adopting photoresist on the basis of the S1 structure, etching the n-type semiconductor table-board to the n-type semiconductor layer (103) by a dry etching method, and exposing the n-type semiconductor table-board;
S3, respectively preparing contact electrodes on the surfaces of the p-type semiconductor layer (105) and the n-type semiconductor mesa, wherein the contact electrodes adopt composite electrodes, the composite electrodes comprise one or two of n-type composite electrodes or p-type composite electrodes, the n-type composite electrodes and the p-type composite electrodes comprise an electrode expansion barrier layer and a reflecting electrode, and the reflecting electrode is evaporated on the electrode expansion barrier layer;
the preparation method of the n-type composite electrode comprises the following steps:
S3A, defining an n-type electrode expansion barrier layer (201) in the n-type composite electrode by adopting photoresist on the basis of the S2 structure, and evaporating the n-type electrode expansion barrier layer (201) on an n-type semiconductor mesa; the n-type electrode expansion barrier layer (201) in the S3A adopts one or two of metal Cr or Ti, the thickness is 1nm-20nm, and the coating rate is
S3B, defining an n-reflecting electrode (202) in the n-type composite electrode by using photoresist on the basis of the S3A structure, and evaporating the n-reflecting electrode (202) on the n-type electrode expansion barrier layer (201); the n reflecting electrode (202) in the S3B at least comprises 1 reflecting metal; the n-reflecting electrode (202) adopts AlTiAu, alTiAuTi, alNiAuTi, alCrPtAu or AlCrPtAuTi reflecting metal system;
S3C, n type composite electrode is annealed at high temperature in nitrogen atmosphere to form n type ohmic contact;
An n-type electrode expansion barrier layer (201) in the S3A and the S3B is formed on the upper surface of the n-type semiconductor mesa, and an n-reflection electrode (202) is formed on the upper surface of the n-type electrode expansion barrier layer (201); the n-type electrode expansion barrier layer (201) is 1 mu m-15 mu m larger than the n-type reflecting electrode (202) in the direction parallel to the n-type semiconductor mesa;
the preparation method of the p-type composite electrode comprises the following steps:
S3a, defining a p-type electrode expansion barrier layer (301) in the p-type composite electrode by using photoresist, and evaporating the p-type electrode expansion barrier layer (301) on the p-type semiconductor layer (105);
s3b, on the basis of the S3a structure, the p-type electrode expansion barrier layer (301) and the epitaxial wafer structure form p-type ohmic contact;
S3c, defining a p-type reflecting electrode (302) in the p-type composite electrode by adopting photoresist on the basis of the S3b structure, evaporating the p-type reflecting electrode (302) on the p-type electrode expansion barrier layer (301), wherein the p-type reflecting electrode (302) at least comprises 1 reflecting metal;
the p-type electrode expansion barrier layers (301) in the S3a, the S3b and the S3c adopt Ni, niAu, niAuNiAu or NiRh metal systems, and the p-reflecting electrodes (302) adopt Al, alTi, agTi, alTiAu or AgTiAu reflecting metal systems;
The p-type electrode expansion barrier layer (301) in the S3a, the S3b and the S3c is formed on the upper surface of the p-type semiconductor layer (105), and the p-reflection electrode (302) is formed on the upper surface of the p-type electrode expansion barrier layer (301); the p-type electrode expansion barrier layer (301) is 1 [ mu ] m-15 [ mu ] m wider than the p-reflecting electrode (302) in a direction parallel to the p-type semiconductor layer (105);
s4, sequentially preparing the passivation layer, the conductive through hole and the bonding pad electrode, and thus preparing the deep ultraviolet LED flip chip.
2. The method for manufacturing the deep ultraviolet LED flip chip according to claim 1, wherein the method comprises the following steps: the annealing temperature of the high-temperature annealing in the S3C is 600-1000 ℃ and the annealing time is 30-400S.
3. The LED flip chip prepared by the preparation method of the deep ultraviolet LED flip chip according to claim 1 or 2, wherein: the semiconductor device comprises a substrate (101), an AlN buffer layer (102), an n-type semiconductor layer (103), a quantum well layer (104), a p-type semiconductor layer (105), an n-type contact electrode and a p-type contact electrode, wherein the AlN buffer layer (102) is grown on the substrate (101), the n-type semiconductor layer (103) is grown on the AlN buffer layer (102), the quantum well layer (104) is grown on the n-type semiconductor layer (103), the p-type semiconductor layer (105) is grown on the quantum well layer (104), the p-type semiconductor layer (105) is etched until the n-type semiconductor layer (103) is exposed out of the n-type semiconductor table, the n-type contact electrode is arranged on the n-type semiconductor table, the p-type contact electrode and/or the p-type contact electrode are composite electrodes, the n-type composite electrode and the p-type composite electrode comprise an electrode expansion barrier layer and a reflecting electrode, and the reflecting electrode is evaporated on the electrode barrier layer.
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| KR100609118B1 (en) * | 2005-05-03 | 2006-08-08 | 삼성전기주식회사 | Flip chip light emitting diode and method of manufactureing the same |
| JP2005340860A (en) * | 2005-08-12 | 2005-12-08 | Toshiba Electronic Engineering Corp | Semiconductor light-emitting element |
| KR101101954B1 (en) * | 2010-05-24 | 2012-01-02 | 고려대학교 산학협력단 | Vertical structured group n-type nitride-based semiconductors having electrode structures with diffusion barrier, and light emitting diodes comprising said semiconductors |
| JP6640815B2 (en) * | 2017-10-26 | 2020-02-05 | 日機装株式会社 | Method for manufacturing semiconductor light emitting device |
| JP6890707B1 (en) * | 2020-10-20 | 2021-06-18 | Ｄｏｗａエレクトロニクス株式会社 | Semiconductor light emitting element and manufacturing method of semiconductor light emitting element |
| CN117878214A (en) * | 2021-09-14 | 2024-04-12 | 泉州三安半导体科技有限公司 | Light emitting diode chip, light emitting device and display device |
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