CN117875228A

CN117875228A - Adjustment method, device, equipment and medium for chip coverage rate analysis process

Info

Publication number: CN117875228A
Application number: CN202410046520.XA
Authority: CN
Inventors: 范晓钊; 刘洁; 苏衍浩
Original assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Current assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority date: 2024-01-11
Filing date: 2024-01-11
Publication date: 2024-04-12

Abstract

The invention relates to the technical field of chip verification, and discloses a method, a device, equipment and a medium for adjusting a chip coverage rate analysis process, wherein the method comprises the following steps: the coverage rate analysis is carried out on the chip to obtain a coverage rate file, and a filtering file is generated according to the coverage rate file; converting the filtered file into a target file; the method comprises the steps of obtaining annotation information of hardware logic codes in a target file, a first code list and a second code list, wherein the first code list is used for determining hardware logic codes allowing filtering, and the second code list is used for determining hardware logic codes not allowing filtering; and adjusting the target file according to the annotation information, the first code list and the second code list to obtain an adjusted target file, and adjusting the chip coverage rate analysis process according to the adjusted target file. The method solves the problems that the data information of the filtered file is huge, various filtered contents are crossed, and the coverage rate analysis process is difficult to adjust according to the filtered file.

Description

Adjustment method, device, equipment and medium for chip coverage rate analysis process

Technical Field

The invention relates to the technical field of chip verification, in particular to a method, a device, equipment and a medium for adjusting a chip coverage rate analysis process.

Background

In the chip verification work, coverage rate analysis is one of indispensable important links. The coverage rate analysis is to judge the completeness of the verification function by analyzing the function coverage rate and the code coverage rate of the RTL (Register-Transfer Level) code, and is an important means for evaluating the quality of the RTL code. Whether the coverage analysis process is accurate and sufficiently directly related to whether each functional scene or some corer (CORNER scene) path of the chip design can be sufficiently covered, if some RTL codes are incorrectly filtered in the coverage analysis process, the coverage of the individual functional scenes or corer paths is missed, and the coverage is missed, so that serious errors occur to the chip.

The coverage rate analysis process filters part of RTL codes without specific effect, and the filtered RTL codes form an Exclude file (filter file). Currently, in order to avoid the above-mentioned missed coverage situation in the coverage rate analysis process, by analyzing the include file, it is determined which RTL codes are filtered out, and whether to further adjust the coverage rate analysis process, so that the coverage rate analysis process will not have the above-mentioned missed coverage situation. However, the data information contained in the include file is huge, there is no fixed format rule and the filtered content of the contained classes are crossed, for example: assertion (Assertion), line (Line), etc., if the project group later needs to look over, multiplex or review the Exclude file for a second time, it is difficult to read, and the process of analyzing the Exclude file is inefficient, and it is difficult to adjust the coverage analysis process.

Therefore, the prior art has the problems that the data information of the filtered file is huge, various filtered contents are crossed, and the coverage rate analysis process is difficult to adjust according to the filtered file.

Disclosure of Invention

In view of the above, the invention provides a method, a device, equipment and a medium for adjusting a chip coverage rate analysis process, so as to solve the problems that the coverage rate analysis process is difficult to adjust according to a filtered file due to huge information of the filtered file data and crossing of various filtered contents.

In a first aspect, the present invention provides a method for adjusting a chip coverage rate analysis process, the method comprising:

the method comprises the steps of carrying out coverage rate analysis on a chip to obtain a coverage rate file, and generating a filter file according to the coverage rate file, wherein the filter file is used for determining a filtered hardware logic code when the coverage rate analysis is carried out on the chip;

converting the filter file into a target file, wherein the target file is used for classifying hardware logic codes in the filter file;

the method comprises the steps of obtaining annotation information of hardware logic codes in a target file, a first code list and a second code list, wherein the first code list is used for determining hardware logic codes allowing filtering, and the second code list is used for determining hardware logic codes not allowing filtering;

And adjusting the target file according to the annotation information, the first code list and the second code list to obtain an adjusted target file, and adjusting the chip coverage rate analysis process according to the adjusted target file.

According to the method for adjusting the chip coverage rate analysis process, the filter file generated after the coverage rate analysis of the chip is obtained. The filtered file is converted into a target file. And adjusting the target file according to the annotation information, the first code list and the second code list to obtain an adjusted target file, and adjusting the chip coverage rate analysis process according to the adjusted target file. The content of the filter file is classified and filtered through the target file, the process of checking and analyzing the filter file is simplified, the chip coverage rate analysis process is adjusted according to the target file, and the coverage rate analysis quality is effectively improved. The method solves the problems that the related technology has huge information of the data of the filtered file and various filtered contents are crossed, and the coverage rate analysis process is difficult to adjust according to the filtered file.

In an alternative embodiment, converting the filtered file into the target file includes:

Acquiring a script calling command, and determining path information of a file conversion script according to the script calling command, wherein the script calling command is also used for designating a filter file and a target file to be converted, and the file conversion script is used for converting the filter file to be converted into the target file;

according to the path information, calling a file conversion script, reading a filter file based on the file conversion script, and searching a preset keyword in the filter file to obtain a searched keyword, wherein the searched keyword is contained in the preset keyword;

classifying the retrieved keywords and counting the number to obtain a first number of keyword categories and the number of keywords in each keyword category;

extracting row information corresponding to all keywords in the keyword category from the filter file, judging whether the row information is complete according to the number of the keywords, and caching the row information to obtain cache information corresponding to each keyword category if the row information is complete, wherein the row information comprises hardware logic codes;

and generating the target file according to the cache information.

In this embodiment, a file conversion script is called, a preset keyword is used to search in a filter file, line information of the keyword is extracted from the filter file according to a search result and cached, and a target file is generated according to the cached information. The filtered files with huge data information and crossed contents are converted into target files, so that filtered hardware logic codes can be conveniently determined, and the chip coverage rate analysis process can be adjusted.

In an optional implementation manner, extracting line information corresponding to all keywords in the keyword category from the filter file, judging whether the line information is complete according to the number of the keywords, and if the line information is complete, caching the line information to obtain cache information corresponding to each keyword category, wherein the method comprises the following steps:

determining a target keyword category from all keyword categories;

extracting row information corresponding to all keywords under the target keyword category from the filter file;

judging whether the number of the row information is equal to the number of the keywords of the target keyword category;

if the target keyword categories are equal, the line information is complete, and the line information is cached to obtain cache information corresponding to the target keyword categories;

and starting to execute the subsequent steps from determining the target keyword category in all the keyword categories until the cache information corresponding to each keyword category is obtained.

In this embodiment, row information corresponding to all keywords in each keyword category is extracted sequentially, and whether the row information is complete is determined by comparing whether the number of the row information is equal to the number of the keywords in the target keyword category, so as to ensure that cache information corresponding to each keyword category is obtained. The method is simple, effective and convenient to implement, and can avoid missing extraction of row information.

In an alternative embodiment, the adjusting the target file according to the annotation information, the first code list and the second code list to obtain the adjusted target file includes:

adding annotation information into the target file to obtain a first intermediate file;

determining hardware logic codes which are lack in the target file and allow filtering according to the first code list and the first intermediate file;

determining hardware logic codes which exist in the target file and are not allowed to be filtered according to the second code list and the first intermediate file;

and marking the hardware logic codes which are allowed to be filtered and the hardware logic codes which are not allowed to be filtered in the first intermediate file, and obtaining the adjusted target file.

In the embodiment, annotation information is added in the target file, and the hardware logic codes which are lack in the target file and allow filtering and the hardware logic codes which are not allowed to be filtered are determined and marked by the first code list and the second code list, so that the hardware logic codes filtered in the coverage rate analysis process are conveniently subjected to review work of disc multiplexing or verification stage acceptance in the later verification stage, and the adjusted target file can be used as an archive file and reserved for use.

In an alternative embodiment, the chip coverage rate analysis process is adjusted according to the adjusted target file, including:

obtaining a hardware logic code allowing filtering and a hardware logic code not allowing filtering according to the adjusted target file;

and executing a first adjustment strategy or a second adjustment strategy according to the hardware logic codes which are allowed to be filtered and the hardware logic codes which are not allowed to be filtered, and adjusting the chip coverage rate analysis process, wherein the first adjustment strategy is used for adjusting the random strategy of the verification use cases according to the hardware logic codes which are allowed to be filtered and the hardware logic codes which are not allowed to be filtered, and the second adjustment strategy is used for generating new verification use cases according to the hardware logic codes which are allowed to be filtered and adding the new verification use cases into the chip coverage rate analysis process.

In this embodiment, according to the hardware logic code that allows filtering and the hardware logic code that does not allow filtering, the first adjustment policy or the second adjustment policy is executed to adjust the chip coverage analysis process, so as to implement complete coverage of the hardware logic code that does not allow filtering, and implement complete filtering of the hardware logic code that allows filtering. The quality of coverage rate analysis of the chip is improved, and acceptance progress of chip verification work is accelerated.

In an alternative embodiment, the coverage analysis is performed on the chip to obtain a coverage file, and a filter file is generated according to the coverage file, including:

acquiring a coverage rate collection command, and executing a code simulator compiling command according to the coverage rate collection command;

compiling a test environment according to the compiling command of the code simulator;

based on the test environment, executing the code simulator simulation command or executing the submitted regression flow to generate a coverage rate file, wherein the coverage rate file can be generated by executing the code simulator simulation command and the submitted regression flow;

and loading the coverage rate file by using a preset tool to generate a filter file.

In this embodiment, the execution code emulator compiles commands and compiles the test environment. Based on the test environment, executing the code simulator to simulate the command or executing the submitted regression flow to generate a coverage rate file. And loading the coverage rate file by using a preset tool to generate a filter file. And recording all filtered hardware logic codes in the coverage rate analysis of the chip through the filter file, and providing a basis for the subsequent adjustment of the coverage rate analysis process of the chip.

In an alternative embodiment, executing the code simulator to simulate the command or to execute the commit regression process generates the coverage file, including:

Executing a code simulator simulation command or executing a submitting regression flow to generate a preset number of second intermediate files;

and merging the second intermediate files to obtain the coverage rate file.

In this embodiment, the second intermediate files generated by the multiple execution code simulator simulation commands or execution submitting regression flows are combined to obtain the coverage rate file. The coverage rate file can more accurately represent the coverage rate condition of the hardware logic code.

In a second aspect, the present invention provides an apparatus for adjusting a chip coverage analysis process, the apparatus comprising:

the generating module is used for carrying out coverage rate analysis on the chip to obtain a coverage rate file, and generating a filtering file according to the coverage rate file, wherein the filtering file is used for determining a hardware logic code filtered out when the coverage rate analysis is carried out on the chip;

the conversion module is used for converting the filter file into a target file, wherein the target file is used for classifying hardware logic codes in the filter file;

the system comprises an acquisition module, a first code list and a second code list, wherein the acquisition module is used for acquiring annotation information of hardware logic codes in a target file, the first code list is used for determining hardware logic codes which are allowed to be filtered, and the second code list is used for determining hardware logic codes which are not allowed to be filtered;

And the adjusting module is used for adjusting the target file according to the annotation information, the first code list and the second code list to obtain an adjusted target file, and adjusting the chip coverage rate analysis process according to the adjusted target file.

In a third aspect, the present invention provides a computer device comprising: the memory and the processor are in communication connection, the memory stores computer instructions, and the processor executes the computer instructions, so that the adjustment method of the chip coverage rate analysis process of the first aspect or any implementation manner corresponding to the first aspect is executed.

In a fourth aspect, the present invention provides a computer-readable storage medium having stored thereon computer instructions for causing a computer to execute the adjustment method of the chip coverage analysis process of the first aspect or any one of the embodiments corresponding thereto.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the related art, the drawings that are required to be used in the description of the embodiments or the related art will be briefly described, and it is apparent that the drawings in the description below are some embodiments of the present invention, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.

FIG. 1 is a flow chart of a method for adjusting a chip coverage analysis process according to an embodiment of the invention;

FIG. 2 is a flow chart of a target Excel file conversion process according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a target Excel file in accordance with embodiments of the present invention;

FIG. 4 is a flow chart of target Excel file analysis, filtering, and review in accordance with embodiments of the present invention;

FIG. 5 is a flow chart of generating a filter file according to an embodiment of the invention;

FIG. 6 is a block diagram of an adjustment device for a chip coverage analysis process according to an embodiment of the present invention;

fig. 7 is a schematic diagram of a hardware structure of a computer device according to an embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

Coverage in verification work generally comprises functional coverage and code coverage, and whether the functional coverage is sufficient and complete mainly depends on the understanding degree of a verification responsible person on a module, a subsystem or a system scene and a developed functional coverage model; the code coverage rate is automatically produced by a logic simulation tool, the coverage degree of the verification case on the RTL code is mainly collected, and the code coverage rate reflects the coverage degree of the RTL code more objectively. Therefore, the method is mainly suitable for the code coverage rate scene, the target file is obtained by processing the filter file generated in the code coverage rate analysis process, and the chip coverage rate analysis process is adjusted according to the target file.

The embodiment of the invention provides a method for adjusting a chip coverage rate analysis process, which is used for forming an include file (filter file) after the coverage rate analysis of a chip. And identifying keywords in the Exclude file, respectively extracting and caching information corresponding to the keywords, classifying and processing the cached data, and generating a target file which can present irregular contents in the Exclude file in a classified and item mode. When verification work is advanced to a coverage rate analysis stage, only the target file is checked row by row according to the annotation information and the code list, the content which is required to be filtered and not required to be filtered in the coverage rate analysis process is determined, the corresponding reasons are marked, and then the chip coverage rate analysis process is adjusted by pertinently adjusting the random strategy of the verification case, or increasing the directional verification case or increasing the regression frequency. The method and the device achieve the effects of classifying and filtering the content of the filter file through the target file, simplifying the process of checking and analyzing the filter file, facilitating verification of later-stage copying and review, adjusting the chip coverage rate analysis process according to the target file, and effectively improving the coverage rate analysis quality.

According to an embodiment of the present invention, an embodiment of a method for adjusting a chip coverage analysis process is provided, and it should be noted that, steps shown in a flowchart of the accompanying drawings may be performed in a computer device having data processing capability, for example: computers, servers, etc., and, although a logical order is depicted in the flowchart, in some cases, the steps shown or described may be performed in a different order than presented herein.

In this embodiment, a method for adjusting a chip coverage rate analysis process is provided, which may be used in the computer device described above, and fig. 1 is a flowchart of a method for adjusting a chip coverage rate analysis process according to an embodiment of the present invention, as shown in fig. 1, where the flowchart includes the following steps:

step S101, coverage rate analysis is carried out on the chip to obtain a coverage rate file, and a filter file is generated according to the coverage rate file, wherein the filter file is used for determining hardware logic codes filtered out when the coverage rate analysis is carried out on the chip.

Specifically, coverage rate analysis is performed on the chip to be tested to obtain a coverage rate file, and coverage rate analysis is performed, for example: VCS simulation (compiled code simulator) or regression testing is performed, coverage files such as: vdb document. And loading and filtering the coverage rate file, and storing the filtered RTL code (hardware logic code) in coverage rate analysis into an include file (filter file).

Step S102, converting the filter file into a target file, wherein the target file is used for classifying hardware logic codes in the filter file.

Specifically, keywords in the include file are identified based on the Python script, for example: assertion (Assertion), line (Line), state machine (FSM), branch (Branch), expression (Condition), and Toggle (Toggle), python script is a script of a commonly used search key. Extracting and caching information corresponding to the keywords in the Exclude file respectively, wherein the cached content comprises hardware logic codes, classifying the hardware logic codes and generating a target file, for example: target Excel (spreadsheet software) file. The generated target Excel file can be used for presenting all irregular contents in the Excel file in a classified and item mode, and the irregular contents comprise hardware logic codes.

Step S103, annotation information of the hardware logic codes in the target file, a first code list and a second code list are obtained, wherein the first code list is used for determining the hardware logic codes allowing filtering, and the second code list is used for determining the hardware logic codes not allowing filtering.

Specifically, annotation information of the hardware logic code in the target file is obtained, where the annotation information is, for example: the function of the hardware logic code, whether the hardware logic code needs filtering, the reason for the filtering, and the like. And acquiring a first code list, wherein the first code list stores hardware logic codes which are allowed to be filtered, namely RTL codes which need to be filtered in the process of analyzing the coverage rate of the chip. The first code list also stores information such as functions of the hardware logic codes allowing filtering, reasons for which filtering is needed, and the like. And acquiring a second code list, wherein the second code list stores hardware logic codes which are not allowed to be filtered, namely RTL codes which cannot be filtered in the process of analyzing the coverage rate of the chip. The second code list also stores information such as functions of hardware logic codes which do not allow filtering, reasons why filtering is impossible, and the like.

The first code list and the second code list specifically comprise hardware logic codes, and the hardware logic codes can be determined according to the service condition of the chip and can be adjusted according to actual requirements.

Step S104, adjusting the target file according to the annotation information, the first code list and the second code list to obtain an adjusted target file, and adjusting the chip coverage rate analysis process according to the adjusted target file.

Specifically, in the chip verification work, coverage analysis is one of indispensable important links. The coverage rate driven verification technology is an important means for evaluating the quality of RTL codes by judging the completeness of verification functions by analyzing the function coverage rate and the code coverage rate of the RTL codes. Generally, when the coverage reaches 100%, it is explained that the verification work ends, and the functional completeness of the RTL code is good.

Screening RTL codes in the target file according to the annotation information, the first code list and the second code list, determining whether the RTL codes which are not allowed to be filtered and the RTL codes which are not filtered and allowed to be filtered exist in the target file, if so, adjusting the chip coverage analysis process by pertinently adjusting the random strategy of the verification use case or adding the directional verification use case or increasing the regression frequency, realizing the coverage of the RTL codes which are not allowed to be filtered and exist in the target file, filtering the RTL codes which are not filtered and allowed to be filtered in the target file, and finally realizing the coverage of the chip to reach 100%.

In some alternative embodiments, converting the filtered file into the target file includes:

and generating the target file according to the cache information.

Specifically, in this embodiment, the conversion from the include file to the target file is quickly implemented by using the script file in a manner of retrieving and identifying the keywords, where the target file is, for example: target Excel file.

Get script call commands, for example:

WorkPath_Info_ CovWxinclude_toCovt_dexcel. Py-d sExclude. El-r dexcel. Xlsx, wherein WorkPath_Info_ is path information with file conversion script, covExclude_toCovt_dexcel. Py is file conversion script for realizing rapid conversion of an Exclude file to a target Excel file, the Exclude file to be converted is designated by "-d", and the target Excel file is designated by "-r". ".sExclude. El" is an Exclude file and ".sExcel. Xlsx" is a target Excel file generated after converting the Exclude file. If errors occur in the execution process of the script calling command, positioning, analyzing and debugging are needed to be specifically performed until the script calling command is successfully executed, and then the target Excel file is generated.

From the above, it can be seen that the path information of the file conversion script can be determined according to the workpath_info_ of the script call command, and the file conversion script can be called according to the path information.

Keywords that are desired to be matched are defined, and preset keywords such as: assertion (Assertion), line (Line), state machine (FSM), branch (Branch), expression (Condition), toggle (Toggle), and so forth. The file conversion script reads the Exclude file and traverses the Exclude file, and in the process, the preset keywords are searched, all the keywords which can be searched in the Exclude file are identified, the searched keywords are contained in the preset keywords, namely, the searched keywords contain one or more of the preset keywords. The file conversion script performs category statistics and number statistics on the retrieved keywords to obtain a first number of keyword categories and keyword numbers of each keyword category, wherein the first number represents a plurality of keywords.

When the file conversion script identifies a certain keyword, the Exclude file is searched circularly, row information corresponding to all keywords in each keyword category is extracted sequentially and cached, whether the content corresponding to the current keyword is extracted and cached is judged according to the number of the keywords, and if the row information of all the keyword categories is extracted and cached, cache information corresponding to each keyword category is obtained. And generating the target file according to the cache information.

By performing the above steps, a target file after conversion can be obtained, for example: target Excel file, as shown in FIG. 3: fig. 3 includes 6 keyword categories, respectively: assertion (Assertion), line (Line), state machine (FSM), branch (Branch), expression (Condition), and signal flip (Toggle), the author name, file version, date, other, descriptive content, remarks, etc. are annotation information for the target file. Fig. 3 shows information under Condition category in the target Excel file, where the content of the Excel file includes 4 pieces of content of the Excel Condition, that is, RTL codes, with serial numbers of 1-4, for example: (Condition 1= =fsm_cfg_step) &, (Condition 2) | (Condition 3> =2'd 3), the RTL code is a conditional statement, (Condition 1= =fsm_cfg_step) checks if Condition1 equals fsm_cfg_step, then this Condition is true, returns 1, otherwise returns 0. Condition2 this is a negation of Condition2, and if Condition2 is 0, then this Condition is true, returning to 1, otherwise returning to 0. (Condition 3> =2'd 3) this Condition checks if Condition3 is greater than or equal to 2'd3, then this Condition is true, returns 1, otherwise returns 0. Finally, the above three conditions are combined in combination with & (sum), | (or) operators, and if (Condition 1 = fsm_cfg_step) and (-Condition 2) are true, or (Condition 3> = 2'd 3) are true, then the whole expression is true, otherwise false. Other RTL codes have similar meanings and are common conditional statements, and are not described herein.

The above process is shown in fig. 2: starting; reading an Exclude file (i.e. a. El file); presetting keywords; retrieving and identifying keywords; if the keyword is searched and identified to fail, debugging and resetting a preset keyword; if the keyword is successfully searched and identified, counting the number and the category of different keywords; circularly searching the Exclude file; traversing the Exclude file; if the traverse of the Exclude file fails, the subsequent steps are started from the reading of the Exclude file (i.e. the. El file); if the traversal of the Exclude file is successful, sequentially extracting the line information matched with the keywords and caching; respectively rewriting the cached information into Excel files; judging whether the extraction of the line information matched with the current key word is finished, if not, executing the subsequent steps from the 'loop searching the Exclude file', and if so, ending.

In some optional embodiments, extracting line information corresponding to all keywords in the keyword category from the filter file, judging whether the line information is complete according to the number of the keywords, and if the line information is complete, caching the line information to obtain cache information corresponding to each keyword category, where the method includes:

determining a target keyword category from all keyword categories;

Specifically, when the file conversion script extracts the row information corresponding to all keywords in the keyword category in the filtering file, one keyword category is determined first, the Exclude file is searched circularly, the row information matched with the keywords in the keyword category is extracted and cached in sequence, after all the row information corresponding to all the keywords in the current keyword category is extracted and cached, the next keyword category is searched and extracted continuously, and the cycle is repeated in this way until all the keyword category information is searched, extracted and cached.

The method comprises the following specific steps:

the file conversion script determines a target keyword category among all keyword categories, for example: assertions (Assertion), lines (Line), state machines (FSM), branches (Branch), expressions (Condition), and signal flip (Toggle), in the above order, are sequentially targeted keyword categories, and if no such category exists, are followed. And extracting row information corresponding to all keywords in the target keyword category from the filter file. Judging whether the number of the row information is equal to the number of the keywords in the target keyword category; if the information representing each keyword is equal, the line information is complete, and the line information is cached to obtain the cache information corresponding to the target keyword category. And re-selecting a new target keyword category from all the keyword categories, and acquiring the cache information of the new target keyword category according to the steps until the cache information corresponding to each keyword category is extracted.

In some optional embodiments, adjusting the target file according to the annotation information, the first code list and the second code list to obtain an adjusted target file includes:

Specifically, for the generated target file, for example: the target Excel file may add explanatory words, that is, annotation information, to the content of the Excel condition in the target Excel file line by line, as shown in fig. 3, where the RTL code with the sequence number 1 in the content of the Excel condition has the explanatory word 1 and the remark 1, where the explanatory word 1 is, for example: the RTL code is a conditional statement for determining whether to perform the calculation step, without affecting the implementation of function a after filtering. Remarks 1 are for example: may be filtered/unfiltered. The above is the annotation information of the RTL code of sequence number 1. And adding the annotation information into the target file to obtain a first intermediate file, wherein the first intermediate file represents the target file added with the annotation information.

Currently, in order to perform filtering, rewinding, review and other works on a target Excel file, a verification responsible person and a design responsible person need to be set, the time consumption is long, the efficiency is low, errors are easy to occur, and the workflow is shown in fig. 4: a target Excel file; verification Owner (verifying responsible person) primary filtration; design Owner (Design responsible person) secondary filtering; VO & DO Double Check (verifying responsible person and designing responsible person Double Check) to-be-filtered code; project group review; an archive file is formed and delivered. For a newly generated target Excel file, a verification responsible person can perform primary filtering on uncovered RTL codes according to experience values and understanding of the RTL codes, and the codes needing to be filtered are confirmed to be filled with descriptions and interpreted line by line. The target Excel file after the primary filtering can be forwarded to a design responsible person, and the design responsible person mainly bears the filtering work of the rest uncovered RTL codes. After the filtering, if the rows, conditions, branches, state machines or overturn of the individual RTL codes still remain uncovered, the responsible person and the design responsible person need to be verified to perform joint inspection and repeatedly push. After the process is finished, verifying that the responsible person needs to organize project group review and acceptance, and changing, archiving and delivering files passing the acceptance.

The invention utilizes the first code list and the second code list to realize the works of filtering, rewinding, reviewing and the like on the target Excel file, and avoids the problems of long time consumption, low efficiency and easy error occurrence of manual operation. The first code list and the second code list may be provided or modified by the verification responsible person and the design responsible person. In the coverage rate analysis process of the chip, the first code list stores hardware logic codes allowing filtering, that is, RTL codes needing filtering, for example: RTL codes for sequence number 1 and sequence number 2 in fig. 3. The first code list also stores information such as functions of the hardware logic code allowing filtering, reasons for which filtering is needed, and the like, for example: the RTL code of sequence number 1 is a conditional statement for determining whether to perform the calculation step, and the implementation of function a is not affected after filtering. In the second code list, hardware logic codes which are not allowed to be filtered, that is, RTL codes which cannot be filtered, in the process of analyzing the coverage rate of the chip, for example: RTL codes for sequence number 3 and sequence number 4 in fig. 3. The second code list also stores information such as functions of hardware logic codes that do not allow filtering, reasons that cannot be filtered, and the like, for example: the RTL code of sequence number 3 is a conditional statement for determining whether to execute a calculation step, which is the core step of the core function b.

Comparing the RTL codes in the first code list with the RTL codes of the first intermediate file, and if part of the RTL codes in the first code list do not exist in the first intermediate file, the part of the RTL codes are hardware logic codes which are lack in the target file and allow filtering, and the part of the RTL codes need to be filtered in the subsequent coverage rate analysis process.

Comparing the RTL codes in the second code list with the RTL codes of the first intermediate file, if a part of RTL codes in the second code list exist in the first intermediate file, the part of RTL codes are hardware logic codes which exist in the target file and are not allowed to be filtered, the RTL codes cannot be filtered in the subsequent coverage rate analysis process, and the RTL codes need to be covered.

In the first intermediate file, the hardware logic code which allows filtering and the hardware logic code which does not allow filtering are marked, so as to obtain an adjusted target file, for example: as shown in fig. 3, the target file is a target Excel file, information such as functions of hardware logic codes of RTL codes allowing filtering, reasons needing filtering and the like is obtained in a first code list, the information is written into the explanatory content of the RTL codes allowing filtering in the target Excel file, and remarks of the RTL codes allowing filtering are filled in to be filtered but not yet filtered; and acquiring information such as functions of the RTL codes which are not allowed to be filtered, reasons which cannot be filtered and the like from a second code list, writing the information into the explanatory content of the RTL codes which are not allowed to be filtered in the target Excel file, and filling the notes of the RTL codes which are not allowed to be filtered into the RTL codes which are not allowed to be filtered.

In some alternative embodiments, adjusting the chip coverage analysis process according to the adjusted target file includes:

Specifically, according to the adjusted target file, hardware logic code that allows filtering and hardware logic code that does not allow filtering are determined, for example: the target file is a target Excel file, and as shown in fig. 3, by screening remarks of each RTL code, RTL codes with remarks needing filtering but not yet filtered are screened out as hardware logic codes allowing filtering, and RTL codes with remarks not allowing filtering are screened out as hardware logic codes not allowing filtering.

The invention filters RTL codes to be covered or unreasonably found in the target file, comprising: the hardware logic code which allows filtering and the hardware logic code which does not allow filtering exist in the adjusted target file. Executing a first adjustment strategy or a second adjustment strategy, adjusting a chip coverage rate analysis process, realizing coverage of RTL codes which exist in the target file and are not allowed to be filtered, filtering the RTL codes which are not filtered in the target file and allowing to be filtered, and finally realizing that the coverage rate of the chip reaches 100%.

The first adjustment policy is used for adjusting a random policy of the verification case according to the hardware logic code which allows filtering and the hardware logic code which does not allow filtering, and the random policy is as follows: and (3) an adaptive random strategy, and according to the adaptive random strategy, the verification use case can be randomly generated. The second adjustment strategy is used for generating a new verification case according to the hardware logic code allowing filtering, adding the new verification case into the chip coverage rate analysis process, wherein the verification case is a set of documents which are formed by preconditions, test inputs, execution conditions, expected results and the like so as to complete data of a specific requirement or target test and embody a test scheme, a method, a technology and a strategy. And adjusting the random strategy of the verification case or increasing the directional verification case or increasing the regression frequency through the first adjustment strategy and the second adjustment strategy to realize the complete coverage of the RTL which does not allow filtering.

In some alternative embodiments, the coverage analysis is performed on the chip to obtain a coverage file, and a filter file is generated according to the coverage file, including:

Specifically, the embodiment is used for generating a coverage file (vdb file) first, then using a VERDI tool to load the coverage file to check the current verification case or the coverage condition of the regression of the current verification case, and obtaining a filter file (excutde file, format is · el file).

This embodiment will be described with reference to fig. 5. The coverage rate collection related command items are added in the compilation options of Makefile as coverage rate collection options, and Makefile defines a series of rules to make which files need to be compiled first, which files need to be compiled later, which files need to be recompiled, and even more complex operations are performed. The coverage collection option needs to be opened before executing the code simulator simulation command or executing the commit-back procedure. If the coverage rate collection option is in an open state, a system executing the code simulator simulation command or executing the submitting regression receives the coverage rate collection command, further executes a VCS (code simulator) compiling command according to the coverage rate collection command, compiles the command through the code simulator, controls a VCS compiling test environment (TB), and re-executes the VCS compiling command if the VCS compiling TB environment fails.

If the VCS compiles the TB environment successfully, executing a VCS simulation command or executing a submitting regression flow, and running a VCS simulation or submitting regression based on the TB environment. If the running of the VCS simulation or the submitting regression fails, after debugging the flow running the simulation or the submitting regression, re-executing the VCS simulation command or executing the submitting regression flow. If the VCS simulation is run or the commit regression is successful, the desired coverage file (in the format of the vdb file) is generated. The VCS supports a complete set of advanced debugging, defect finding, coverage, verification planning and assertion techniques, which can understand the verification methodology and provide debugging of random constraints. Submitting regression is the process of submitting a regression test, which is the process of retesting a function that has been tested before, after modifying or updating the software. Regression testing is intended to ensure that the previously tested functions still function properly after modification or updating of the software, without new problems or errors arising from new modifications or updates, the regression testing should cover the modified or updated parts and the associated functional modules, and the test coverage can measure the effectiveness of the regression testing.

Loading the coverage file with a preset tool, such as: the VERDI tool is an EDA simulation tool. If the loading of the coverage file fails, the VCS emulation command is re-executed or the commit-back procedure is performed. If the loading of the coverage file is successful, the coverage condition of the RTL code is seen, and the filtered RTL code is saved as an Exclude file (in the format of an. El file) for viewing, rewinding or review.

In some alternative embodiments, executing the code simulator to simulate the command or to execute the commit-back procedure generates the coverage file, including:

And merging the second intermediate files to obtain the coverage rate file.

Specifically, in the process of actually analyzing the coverage rate of the chip, a VCS simulation command is continuously executed or a submitting regression flow is executed, a plurality of files are generated vdb, the number of the files generated vdb is recorded as a preset number, and the preset number represents a plurality of files; to distinguish from coverage files, the multiple generated vdb file is referred to as a second intermediate file.

And performing MERGE on the multiple generated vdb files, namely the second intermediate files, to obtain the expected coverage rate file. The coverage rate file can be used for checking the coverage rate condition of the RTL codes after the MERGE.

The embodiment also provides an adjusting device for the chip coverage rate analysis process, which is used for implementing the foregoing embodiment and the preferred implementation manner, and is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

The embodiment provides an adjusting device for a chip coverage rate analysis process, as shown in fig. 6, including:

the generating module 601 is configured to perform coverage analysis on a chip to obtain a coverage file, and generate a filter file according to the coverage file, where the filter file is used to determine a hardware logic code filtered when the coverage analysis is performed on the chip;

the conversion module 602 is configured to convert the filter file into a target file, where the target file is configured to classify hardware logic codes in the filter file;

the obtaining module 603 is configured to obtain annotation information of a hardware logic code in the target file, a first code list and a second code list, where the first code list is used to determine a hardware logic code that is allowed to be filtered, and the second code list is used to determine a hardware logic code that is not allowed to be filtered;

the adjusting module 604 is configured to adjust the target file according to the annotation information, the first code list and the second code list, obtain an adjusted target file, and adjust the chip coverage analysis process according to the adjusted target file.

In some alternative embodiments, the conversion module 602 includes:

the first determining unit is used for acquiring a script calling command and determining path information of a file conversion script according to the script calling command, wherein the script calling command is also used for designating a filter file and a target file to be converted, and the file conversion script is used for converting the filter file to be converted into the target file;

The calling unit is used for calling a file conversion script according to the path information, reading a filter file based on the file conversion script, and searching a preset keyword in the filter file to obtain a searched keyword, wherein the searched keyword is contained in the preset keyword;

the first obtaining unit is used for classifying the retrieved keywords and counting the number of the keywords to obtain a first number of keyword categories and the number of the keywords of each keyword category;

the judging unit is used for extracting the row information corresponding to all the keywords in the keyword category from the filter file, judging whether the row information is complete according to the number of the keywords, and caching the row information to obtain cache information corresponding to each keyword category if the row information is complete, wherein the row information comprises hardware logic codes;

the first generation unit is used for generating the target file according to the cache information.

In some alternative embodiments, the determining unit includes:

the determining submodule is used for determining a target keyword category from all keyword categories;

the extraction sub-module is used for extracting row information corresponding to all keywords in the target keyword category from the filter file;

The judging sub-module is used for judging whether the number of the row information is equal to the number of the keywords of the target keyword category;

the caching sub-module is used for caching the line information completely if the line information is equal to the target keyword category, so as to obtain the caching information corresponding to the target keyword category;

and the circulation sub-module is used for executing subsequent steps from determining the target keyword category in all the keyword categories until the cache information corresponding to each keyword category is obtained.

In some alternative embodiments, the adjustment module 604 includes:

the second obtaining unit is used for adding the annotation information into the target file to obtain a first intermediate file;

the second determining unit is used for determining hardware logic codes which are lack in the target file and allow filtering according to the first code list and the first intermediate file;

the third determining unit is used for determining hardware logic codes which exist in the target file and are not allowed to be filtered according to the second code list and the first intermediate file;

the marking unit is used for marking the hardware logic codes which are allowed to be filtered and the hardware logic codes which are not allowed to be filtered in the first intermediate file, so as to obtain the adjusted target file.

In some alternative embodiments, the adjustment module 604 includes:

The third obtaining unit is used for obtaining the hardware logic codes which are allowed to be filtered and the hardware logic codes which are not allowed to be filtered according to the adjusted target file;

and the adjusting unit is used for executing a first adjusting strategy or a second adjusting strategy according to the hardware logic codes which are allowed to be filtered and the hardware logic codes which are not allowed to be filtered, and adjusting the chip coverage rate analysis process, wherein the first adjusting strategy is used for adjusting the random strategy of the verification case according to the hardware logic codes which are allowed to be filtered and the hardware logic codes which are not allowed to be filtered, and the second adjusting strategy is used for generating a new verification case according to the hardware logic codes which are allowed to be filtered and adding the new verification case into the chip coverage rate analysis process.

In some alternative embodiments, the generating module 601 includes:

the acquisition unit is used for acquiring the coverage rate collection command and executing the code simulator compiling command according to the coverage rate collection command;

the compiling unit is used for compiling the test environment according to the compiling command of the code simulator;

the second generation unit is used for executing the code simulator simulation command or submitting the regression flow based on the test environment to generate a coverage rate file, wherein the coverage rate file can be generated by executing the code simulator simulation command and submitting the regression flow;

And the third generation unit is used for loading the coverage rate file by using a preset tool and generating a filter file.

In some alternative embodiments, the second generating unit includes:

the generation sub-module is used for executing the simulation command of the code simulator or executing the submitting regression flow to generate a preset number of second intermediate files;

and the merging sub-module is used for merging the second intermediate files to obtain coverage rate files.

Further functional descriptions of the above respective modules and units are the same as those of the above corresponding embodiments, and are not repeated here.

The adjustment means of the chip coverage analysis procedure in this embodiment is presented in the form of functional units, here referred to as ASIC (Application Specific Integrated Circuit ) circuits, processors and memories executing one or more software or fixed programs, and/or other devices that can provide the above described functions.

The embodiment of the invention also provides computer equipment, which is provided with the adjusting device for the chip coverage rate analysis process shown in the figure 6.

Referring to fig. 7, fig. 7 is a schematic structural diagram of a computer device according to an alternative embodiment of the present invention, as shown in fig. 7, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the computer device, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display device coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple computer devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 10 is illustrated in fig. 7.

The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.

Wherein the memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform a method for implementing the embodiments described above.

The memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 20 may optionally include memory located remotely from processor 10, which may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

Memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; the memory 20 may also comprise a combination of the above types of memories.

The computer device also includes a communication interface 30 for the computer device to communicate with other devices or communication networks.

The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.

Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.

Claims

1. A method for adjusting a chip coverage analysis process, the method comprising:

the method comprises the steps of carrying out coverage rate analysis on a chip to obtain a coverage rate file, and generating a filter file according to the coverage rate file, wherein the filter file is used for determining a hardware logic code filtered out when the coverage rate analysis is carried out on the chip;

converting the filter file into a target file, wherein the target file is used for classifying the hardware logic codes in the filter file;

acquiring annotation information, a first code list and a second code list of the hardware logic codes in the target file, wherein the first code list is used for determining hardware logic codes allowing filtering, and the second code list is used for determining hardware logic codes not allowing filtering;

and adjusting the target file according to the annotation information, the first code list and the second code list to obtain an adjusted target file, and adjusting a chip coverage rate analysis process according to the adjusted target file.

2. The method of claim 1, wherein said converting said filtered file to a target file comprises:

acquiring a script calling command, and determining path information of a file conversion script according to the script calling command, wherein the script calling command is also used for designating the filter file to be converted and the target file, and the file conversion script is used for converting the filter file to be converted into the target file;

calling the file conversion script according to the path information, reading the filter file based on the file conversion script, and searching a preset keyword in the filter file to obtain a searched keyword, wherein the searched keyword is contained in the preset keyword;

classifying the retrieved keywords and counting the number of the keywords to obtain a first number of keyword categories and the number of the keywords of each keyword category;

extracting row information corresponding to all keywords in the keyword category from the filter file, judging whether the row information is complete according to the number of the keywords, and caching the row information to obtain cache information corresponding to each keyword category if the row information is complete, wherein the row information comprises the hardware logic code;

And generating the target file according to the cache information.

3. The method according to claim 2, wherein the extracting the line information corresponding to all keywords in the keyword category in the filter file, and judging whether the line information is complete according to the number of keywords, if the line information is complete, caching the line information to obtain the cache information corresponding to each keyword category, includes:

determining a target keyword category from all the keyword categories;

extracting the row information corresponding to all keywords in the target keyword category from the filter file;

if the target keyword categories are equal, the line information is complete, and the line information is cached to obtain the cache information corresponding to the target keyword categories;

and starting to execute the subsequent steps from the step of determining the target keyword category in all the keyword categories until the cache information corresponding to each keyword category is obtained.

4. The method of claim 1, wherein adjusting the target file according to the annotation information, the first code list, and the second code list to obtain the adjusted target file comprises:

Adding the annotation information into the target file to obtain a first intermediate file;

and marking the hardware logic codes which are allowed to be filtered and the hardware logic codes which are not allowed to be filtered in the first intermediate file to obtain the adjusted target file.

5. The method of claim 4, wherein adjusting the chip coverage analysis process based on the adjusted target file comprises:

obtaining the hardware logic codes allowing filtering and the hardware logic codes not allowing filtering according to the adjusted target file;

executing a first adjustment strategy or a second adjustment strategy according to the hardware logic code allowing filtering and the hardware logic code not allowing filtering, and adjusting the chip coverage rate analysis process, wherein the first adjustment strategy is used for adjusting the random strategy of the verification case according to the hardware logic code allowing filtering and the hardware logic code not allowing filtering, and the second adjustment strategy is used for generating a new verification case according to the hardware logic code allowing filtering and adding the new verification case into the chip coverage rate analysis process.

6. The method of claim 1, wherein the performing coverage analysis on the chip to obtain a coverage file, and generating a filter file according to the coverage file, comprises:

compiling a test environment according to the code simulator compiling command;

based on the test environment, executing a code simulator simulation command or a submitting regression flow to generate the coverage rate file, wherein the coverage rate file can be generated by the code simulator simulation command and the submitting regression flow;

and loading the coverage rate file by using a preset tool, and generating the filter file.

7. The method of claim 6, wherein the executing a code simulator to simulate a command or to execute a commit regression process, generating the coverage file, comprises:

executing the code simulator simulation command or executing the submitting regression flow to generate a preset number of second intermediate files;

and merging the second intermediate files to obtain the coverage rate file.

8. An apparatus for adjusting a chip coverage analysis process, the apparatus comprising:

the generating module is used for carrying out coverage rate analysis on the chip to obtain a coverage rate file, and generating a filtering file according to the coverage rate file, wherein the filtering file is used for determining a filtered hardware logic code when the coverage rate analysis is carried out on the chip;

the conversion module is used for converting the filter file into a target file, wherein the target file is used for classifying the hardware logic codes in the filter file;

the system comprises an acquisition module, a first code list and a second code list, wherein the acquisition module is used for acquiring annotation information of the hardware logic codes in the target file, the first code list is used for determining hardware logic codes which are allowed to be filtered, and the second code list is used for determining hardware logic codes which are not allowed to be filtered;

and the adjustment module is used for adjusting the target file according to the annotation information, the first code list and the second code list to obtain an adjusted target file, and adjusting a chip coverage rate analysis process according to the adjusted target file.

9. A computer device, comprising:

a memory and a processor, the memory and the processor being communicatively connected to each other, the memory having stored therein computer instructions, the processor executing the computer instructions to perform the method of adjusting the chip coverage analysis process of any one of claims 1 to 7.

10. A computer-readable storage medium having stored thereon computer instructions for causing a computer to execute the adjustment method of the chip coverage analysis process according to any one of claims 1 to 7.