CN114297961A - Chip test case processing method and related device - Google Patents
Chip test case processing method and related device Download PDFInfo
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- CN114297961A CN114297961A CN202111445180.0A CN202111445180A CN114297961A CN 114297961 A CN114297961 A CN 114297961A CN 202111445180 A CN202111445180 A CN 202111445180A CN 114297961 A CN114297961 A CN 114297961A
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Abstract
The application discloses a chip test case processing method, which comprises the following steps: performing structure verification plan generation processing based on a preset format and received test case definition data to obtain a structure verification plan file; executing management operation on the received test case data based on the structure verification plan file to obtain simulation data; and executing chip simulation operation based on the preset simulation flow and the simulation data to obtain a simulation result. On the basis, management operation is performed on the received test case data based on the structure verification plan file to obtain simulation data, the test case is not managed in a manual mode, and the efficiency and the effect of managing the chip test case are improved. The application also discloses a chip test case processing device, a server and a computer readable storage medium, which have the beneficial effects.
Description
Technical Field
The present disclosure relates to the field of chip manufacturing technologies, and in particular, to a method for processing a chip test case, a device for processing a chip test case, a server, and a computer-readable storage medium.
Background
With the continuous development of chip foundation, the chip needs to be verified in the chip design process to improve the feasibility of the chip.
In the related art, technicians generally simply adopt a script language to manage test cases, however, the complexity of chip functions is different, and the number of test cases is different. The chip with simple functions has small test case set and little influence on direct script language management. When the chip functions are increased and the scale is enlarged, the readability of directly adopting script language is poor, the flow of personnel and the change of versions can generate larger influence, and the efficiency and the effect of managing the chip test case are reduced.
Therefore, how to improve the efficiency and effect of managing the chip test cases is a key issue that those skilled in the art pay attention to.
Disclosure of Invention
The application aims to provide a chip test case processing method, a chip test case processing device, a server and a computer readable storage medium, so as to improve the efficiency and effect of managing chip test cases.
In order to solve the above technical problem, the present application provides a method for processing a chip test case, including:
performing structure verification plan generation processing based on a preset format and received test case definition data to obtain a structure verification plan file;
executing management operation on the received test case data based on the structure verification plan file to obtain simulation data; the management operation comprises use case filtering, simulation option definition, simulation option modification, regression testing and data viewing;
and executing chip simulation operation based on a preset simulation flow and the simulation data to obtain a simulation result.
Optionally, the generating of the structure verification plan is performed based on the preset format and the received test case definition data, so as to obtain a structure verification plan file, including:
using the received test case information and test case attribute information as the test case definition data;
and writing the test case definition data into an initial structure verification plan file based on the preset format to obtain the structure verification plan file.
Optionally, executing a management operation on the received test case data based on the structure verification plan file to obtain simulation data, including:
storing the test case data corresponding to the structure verification plan file according to a preset rule to obtain a test case folder;
and executing the management operation on the test case folder to obtain the simulation data.
Optionally, executing a chip simulation operation based on a preset simulation flow and the simulation data to obtain a simulation result, including:
importing the simulation data into a simulation tool;
and controlling the simulation tool to execute simulation operation based on the configuration information in the simulation data to obtain a simulation result.
Optionally, executing a chip simulation operation based on a preset simulation flow and the simulation data to obtain a simulation result, including:
receiving a test case operation instruction through a UI (user interface);
executing operation on the simulation data based on the test case operation instruction to obtain data to be simulated;
and when an execution instruction is received through the UI, executing simulation operation based on the data to be simulated corresponding to the execution instruction to obtain the simulation result.
Optionally, the presetting of the simulation process includes: environment installation operation, simulation instruction execution operation and simulation result analysis operation.
Optionally, the method further includes:
and analyzing the simulation result based on a preset retrieval instruction to obtain an analysis result.
The present application further provides a device for processing a chip test case, including:
the test data receiving module is used for generating a structure verification plan based on a preset format and the received test case definition data to obtain a structure verification plan file;
the test data management module is used for executing management operation on the received test case data based on the structure verification plan file to obtain simulation data; the management operation comprises use case filtering, simulation option definition, simulation option modification, regression testing and data viewing;
and the chip simulation module is used for executing chip simulation operation based on a preset simulation flow and the simulation data to obtain a simulation result.
The present application further provides a server, comprising:
a memory for storing a computer program;
and the processor is used for realizing the steps of the chip test case processing method when the computer program is executed.
The present application further provides a computer-readable storage medium, on which a computer program is stored, and the computer program, when executed by a processor, implements the steps of the chip test case processing method as described above.
The application provides a chip test case processing method, which comprises the following steps: performing structure verification plan generation processing based on a preset format and received test case definition data to obtain a structure verification plan file; executing management operation on the received test case data based on the structure verification plan file to obtain simulation data; the management operation comprises use case filtering, simulation option definition, simulation option modification, regression testing and data viewing; and executing chip simulation operation based on a preset simulation flow and the simulation data to obtain a simulation result.
The method comprises the steps of generating a corresponding structure verification plan file through received test case definition data, on the basis, carrying out management operation on the received test case data based on the structure verification plan file to obtain simulation data instead of manually managing the test cases, and finally carrying out chip simulation operation based on a preset simulation flow and the simulation data to obtain a simulation result, so that the efficiency and the effect of managing the chip test cases are improved.
The application also provides a chip test case processing device, a server and a computer readable storage medium, which have the beneficial effects, and are not described herein again.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of a method for processing a chip test case according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a chip test case processing apparatus according to an embodiment of the present disclosure.
Detailed Description
The core of the application is to provide a chip test case processing method, a chip test case processing device, a server and a computer readable storage medium, so as to improve the efficiency and effect of managing the chip test cases.
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
In the related art, technicians generally simply adopt a script language to manage test cases, however, the complexity of chip functions is different, and the number of test cases is different. The chip with simple functions has small test case set and little influence on direct script language management. When the chip functions are increased and the scale is enlarged, the readability of directly adopting script language is poor, the flow of personnel and the change of versions can generate larger influence, and the efficiency and the effect of managing the chip test case are reduced.
Therefore, the application provides a chip test case processing method, a corresponding structure verification plan file is generated through received test case definition data, on the basis, management operation is performed on the received test case data based on the structure verification plan file to obtain simulation data, the test case is not managed in a manual mode, and finally chip simulation operation is performed based on a preset simulation flow and the simulation data to obtain a simulation result, so that the efficiency and the effect of managing the chip test case are improved.
The following describes a method for processing a chip test case according to an embodiment.
Referring to fig. 1, fig. 1 is a flowchart of a method for processing a chip test case according to an embodiment of the present disclosure.
In this embodiment, the method may include:
s101, generating a structure verification plan based on a preset format and received test case definition data to obtain a structure verification plan file;
therefore, the step aims to perform structural verification plan generation processing based on the preset format and the received test case definition data to obtain a corresponding structural verification plan file. The structure verification plan file is used for controlling the management and use process of the test cases. That is, in the present embodiment, in order to implement automatic processing and management of the chip test case, the processing is not performed manually. Accordingly, there is a need for implementing corresponding automated operations based on a structure verification plan file.
The preset format is a certain format for constructing the structure verification plan file, so that the computer can acquire and identify the content in the file according to the preset format.
The test case definition data is corresponding data input by a technician or a user and used for defining the test cases and defining the attributes in the structure verification plan file.
Further, the step may include:
step 1, using the received test case information and test case attribute information as test case definition data;
and 2, writing the test case definition data into the initial structure verification plan file based on a preset format to obtain a structure verification plan file.
It can be seen that the present alternative scheme mainly explains how to obtain the structure verification plan file. In the alternative, the received test case information and the test case attribute information are used as test case definition data, and the test case definition data is written into the initial structure verification plan file based on a preset format to obtain the structure verification plan file.
S102, executing management operation on the received test case data based on the structure verification plan file to obtain simulation data; the management operation comprises use case filtering, simulation option definition, simulation option modification, regression testing and data viewing;
on the basis of S101, the step aims at carrying out management operation on the received test case data based on the structure verification plan file to obtain simulation data; the management operation comprises use case filtering, simulation option definition, simulation option modification, regression testing and data viewing.
Therefore, the step aims to perform corresponding configuration operation on the test case based on the configuration information of the test case in the structure verification plan file on the basis of obtaining the structure verification plan file, and obtain corresponding simulation data.
Further, the step may include:
step 1, storing test case data corresponding to a structure verification plan file according to a preset rule to obtain a test case folder;
and 2, executing management operation on the test case folder to obtain simulation data.
It can be seen that the present alternative scheme mainly explains how simulation data is acquired. In the alternative, the test case data corresponding to the structure verification plan file is stored according to a preset rule to obtain a test case folder, and management operation is performed on the test case folder to obtain simulation data.
S103, executing chip simulation operation based on a preset simulation flow and simulation data to obtain a simulation result.
On the basis of S102, the present step aims to execute a chip simulation operation based on a preset simulation flow and simulation data, and obtain a simulation result.
Therefore, in this step, the simulation operation may be executed based on the corresponding simulation tool on the basis of acquiring the corresponding simulation data, so as to obtain the simulation result. The simulation data comprises simulation commands which are controlled by corresponding simulation tools.
Further, the step may include:
step 1, importing simulation data into a simulation tool;
and 2, controlling the simulation tool to execute simulation operation based on the configuration information in the simulation data to obtain a simulation result.
It can be seen that the present alternative scheme mainly illustrates how the emulation operation is performed in the background. In the alternative, the simulation data is imported into the simulation tool, and the simulation tool is controlled to execute simulation operation based on the configuration information in the simulation data to obtain a simulation result. The simulation tool can adopt any one of the simulation tools provided by the prior art. Accordingly, selecting a corresponding simulation tool requires selecting a corresponding simulation command.
Further, the step may include:
step 1, receiving a test case operation instruction through a UI (user interface);
step 2, executing operation on the simulation data based on the test case operation instruction to obtain data to be simulated;
and 3, when the execution instruction is received through the UI, executing simulation operation based on the data to be simulated corresponding to the execution instruction to obtain a simulation result.
It can be seen that the present alternative is primarily illustrative of how simulation operations may be performed visually through a UI interface. In the alternative, the test case operation instruction is received through the UI, the simulation data is operated based on the test case operation instruction to obtain the data to be simulated, and when the execution instruction is received through the UI, the simulation operation is executed based on the data to be simulated corresponding to the execution instruction to obtain the simulation result. Wherein, the technicians can input corresponding control information or control options through the corresponding UI interfaces so as to control the simulation process and improve the effectiveness of control.
Further, the step may include:
presetting a simulation flow, comprising: environment installation operation, simulation instruction execution operation and simulation result analysis operation.
It can be seen that the present alternative scheme mainly explains what is a preset simulation flow. In this alternative, the preset simulation process includes: environment installation operation, simulation instruction execution operation and simulation result analysis operation.
Further, this embodiment may further include:
and analyzing the simulation result based on a preset retrieval instruction to obtain an analysis result.
It can be seen that the present alternative is mainly illustrative of how the analysis results are obtained. In the alternative, the simulation result is analyzed based on the preset retrieval instruction to obtain an analysis result.
In summary, in the embodiment, the corresponding structure verification plan file is generated through the received test case definition data, on this basis, the management operation is performed on the received test case data based on the structure verification plan file to obtain the simulation data, instead of performing the management on the test case in a manual manner, and finally, the chip simulation operation is performed based on the preset simulation flow and the simulation data to obtain the simulation result, so that the efficiency and the effect of managing the chip test case are improved.
The following further describes a method for processing a chip test case provided by the present application with a specific embodiment.
In this embodiment, in order to facilitate function implementation, achieve convenient operability and high efficiency of management, and improve the convergence speed, a structural verification method is used to define various attributes of a test case in a unique original input file. The user can define the required test case in the verification plan according to the verification plan, and automatically add the corresponding attribute of the case according to the requirement so as to be used for case management and simulation. The input file must meet certain format definition requirements and can be implemented in multiple languages. The format definition may be as follows:
aiming at the division of different modules in the chip during verification, the method also supports the nesting management of a plurality of input files, and the sub-files are imported into the top-level file, so that the case division management is facilitated.
Furthermore, the test cases are managed.
In order to simplify the use case management and improve the management efficiency, the embodiment defines the use case file storage hierarchy, specifies that all use cases are individually established as folders, and are uniformly placed in the tc folder under the corresponding module folders, and the structure can be automatically generated by a tool. Aiming at different problems of simulation options of different use cases, a corresponding simulation configuration file exists under each use case folder, and the simulation configuration file can be automatically generated by a tool and can be configured by a user. Similarly, for the tidiness of the working directory, the method uniformly defines the simulation path under the simulation folder, and the path management is similar to the use case path.
In addition, as chip designs scale larger and larger, randomization is employed to ensure the integrity of the excitation set. In order to adapt to the requirement, for the test case needing random, the method adopted by the patent is as follows: the source use case is unchanged, the 'random' attribute is set to the corresponding random number in the HVP (structural Verification Plan), the tool will copy the number in the database and add the corresponding suffix, and the simulation is carried out in parallel under different directories.
Further, in this embodiment, a visual operation interface may be built based on PyQt5, and the test case may be managed by importing the required HVP file in the UI interface of the tool. The principle is that all attributes of each test case, including VO, priority, owner and other related information of the case, are extracted from an HVP file through Python software, a database is generated, and corresponding function operation is performed on the imported test case in a UI (user interface).
The management functions of the present embodiment may include: the method comprises the steps of filtering and classifying test cases, defining and modifying simulation options, performing regression testing, checking simulation files, and analyzing and reporting simulation results.
To catch up with the use case status and verification progress. During regression testing, the tool saves the results, summarizes and generates a visual regression report according to the results of each regression testing, and marks coverage rate, case passing rate and the like. The verification progress can be clearly displayed, and the verification manager can conveniently control the verification progress.
In order to facilitate simulation management and realize compatibility of different simulation software and hardware co-simulation, the present embodiment defines three simulation steps: pre, run, post. In the simulation, the three steps are sequentially executed in sequence. Also, the simulation state during the simulation is specified: pending, running, post process, pass, fail, etc. to characterize the status and results of test cases in the regression process.
For the three simulation steps, the method specifies the contents of YAML (Yet Another Markup Language, Another Markup Language) file format as follows:
pre: the step is to install corresponding simulation tools, configure the environment and prepare files required by simulation. User-defined instructions may be executed.
run: this step executes the emulation commands.
post: this step performs analysis of the simulation results. User-defined commands may be executed.
The implementation modes are various, and one implementation of YAML grammar is as follows, and other languages can also be used for implementation.
Based on the three simulation steps, this embodiment specifies two cases simulation methods, including: the batch mode emulates a UI (User Interface).
And the Batch mode is to introduce all the case management files to be operated at one time without using a UI (user interface), the tool continuously simulates all the test cases defined in the files according to the steps and the configuration until all the case simulations are finished, analyzes and collects results, and finally notifies a verification manager and a related person in charge of mail. The method is suitable for scenes such as regression testing and usability checking during version alternation.
The UI simulation calls a UI interface of the tool, and the functions specified in the management method are realized in the UI interface. The method can be used for carrying out classification management, state tracking, case simulation debugging, regression testing and the like of the cases. The method is suitable for the debugging of the test case, the review of VO, the case and the coverage rate and other scenes. And the simulation result can be analyzed and stored, a visual file in the form of an excel table and the like is formed, and the simulation result is inversely marked according to the specific file.
The following steps are the steps of the use case simulation debugging function in the UI interface, which may include:
modification of simulation options: and selecting the corresponding use case, and clicking set _ tc to add and modify the simulation options of the use case and the corresponding attributes in the HVP file.
Submitting simulation: and selecting the corresponding test case, clicking the submit (optional more and counter-optional), and calling the corresponding simulation tool to simulate in the background by the tool.
And (4) stopping simulation: and selecting the corresponding test case, clicking kill, and ending the task by the tool.
And (3) displaying the state: and displaying the specified information such as the case simulation state, the time and the like in real time in the simulation process in the UI.
Besides, the functions of analyzing the log parts again (redo post), and denormalizing the result (read result) are also provided.
After the simulation operation is finished, the embodiment searches the log files and the keywords defined by the user, and judges whether the test case passes according to the search result. If the use case passes, saving the state and coverage rate file; if the use case fails, the simulation result is retained, the corresponding coverage rate file is deleted, and the coverage rate collection is not participated; and triggering the mail system to inform the corresponding responsible person of the reason of case simulation failure.
It can be seen that, in this embodiment, a corresponding structure verification plan file is generated through the received test case definition data, on this basis, a management operation is performed on the received test case data based on the structure verification plan file to obtain simulation data, instead of performing management on the test case in a manual manner, and finally, a chip simulation operation is performed based on a preset simulation flow and the simulation data to obtain a simulation result, so that the efficiency and the effect of managing the chip test case are improved.
In the following, the chip test case processing apparatus provided in the embodiment of the present application is introduced, and the chip test case processing apparatus described below and the chip test case processing method described above may be referred to correspondingly.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a chip test case processing apparatus according to an embodiment of the present disclosure.
In this embodiment, the apparatus may include:
the test data receiving module 100 is configured to perform structure verification plan generation processing based on a preset format and received test case definition data to obtain a structure verification plan file;
the test data management module 200 is configured to perform a management operation on the received test case data based on the structure verification plan file to obtain simulation data; the management operation comprises use case filtering, simulation option definition, simulation option modification, regression testing and data viewing;
the chip simulation module 300 is configured to execute a chip simulation operation based on a preset simulation flow and simulation data to obtain a simulation result.
Optionally, the test data receiving module 100 is specifically configured to use the received test case information and the test case attribute information as test case definition data; and writing the test case definition data into the initial structure verification plan file based on a preset format to obtain a structure verification plan file.
Optionally, the test data management module 200 is specifically configured to store the test case data corresponding to the structure verification plan file according to a preset rule, so as to obtain a test case folder; and executing management operation on the test case folder to obtain simulation data.
Optionally, the chip simulation module 300 is specifically configured to import simulation data into a simulation tool; and controlling the simulation tool to execute simulation operation based on the configuration information in the simulation data to obtain a simulation result.
Optionally, the chip simulation module 300 is specifically configured to receive a test case operation instruction through a UI interface; executing operation on the simulation data based on the test case operation instruction to obtain data to be simulated; and when the execution instruction is received through the UI, executing simulation operation based on the data to be simulated corresponding to the execution instruction to obtain a simulation result.
Optionally, the apparatus may further include:
and the result analysis module is used for analyzing the simulation result based on the preset retrieval instruction to obtain an analysis result.
An embodiment of the present application further provides a server, including:
a memory for storing a computer program;
and the processor is used for realizing the steps of the chip test case processing method according to the above embodiment when executing the computer program.
The embodiment of the present application further provides a computer-readable storage medium, where a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the steps of the chip test case processing method according to the above embodiment are implemented.
The embodiments are described in a progressive manner in the specification, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The above detailed description is provided for a chip test case processing method, a chip test case processing apparatus, a server, and a computer-readable storage medium. The principles and embodiments of the present application are explained herein using specific examples, which are provided only to help understand the method and the core idea of the present application. It should be noted that, for those skilled in the art, it is possible to make several improvements and modifications to the present application without departing from the principle of the present application, and such improvements and modifications also fall within the scope of the claims of the present application.
Claims (10)
1. A method for processing chip test cases is characterized by comprising the following steps:
performing structure verification plan generation processing based on a preset format and received test case definition data to obtain a structure verification plan file;
executing management operation on the received test case data based on the structure verification plan file to obtain simulation data; the management operation comprises use case filtering, simulation option definition, simulation option modification, regression testing and data viewing;
and executing chip simulation operation based on a preset simulation flow and the simulation data to obtain a simulation result.
2. The chip test case processing method according to claim 1, wherein performing structure verification plan generation processing based on a preset format and received test case definition data to obtain a structure verification plan file comprises:
using the received test case information and test case attribute information as the test case definition data;
and writing the test case definition data into an initial structure verification plan file based on the preset format to obtain the structure verification plan file.
3. The method for processing the chip test case according to claim 1, wherein the step of executing a management operation on the received test case data based on the structure verification plan file to obtain simulation data comprises:
storing the test case data corresponding to the structure verification plan file according to a preset rule to obtain a test case folder;
and executing the management operation on the test case folder to obtain the simulation data.
4. The method for processing the chip test case according to claim 1, wherein the step of executing a chip simulation operation based on a preset simulation flow and the simulation data to obtain a simulation result comprises:
importing the simulation data into a simulation tool;
and controlling the simulation tool to execute simulation operation based on the configuration information in the simulation data to obtain a simulation result.
5. The method for processing the chip test case according to claim 1, wherein the step of executing a chip simulation operation based on a preset simulation flow and the simulation data to obtain a simulation result comprises:
receiving a test case operation instruction through a UI (user interface);
executing operation on the simulation data based on the test case operation instruction to obtain data to be simulated;
and when an execution instruction is received through the UI, executing simulation operation based on the data to be simulated corresponding to the execution instruction to obtain the simulation result.
6. The method for processing the chip test case according to claim 1, wherein the presetting of the simulation flow includes: environment installation operation, simulation instruction execution operation and simulation result analysis operation.
7. The method for processing the chip test case according to claim 1, further comprising:
and analyzing the simulation result based on a preset retrieval instruction to obtain an analysis result.
8. A chip test case processing apparatus, comprising:
the test data receiving module is used for generating a structure verification plan based on a preset format and the received test case definition data to obtain a structure verification plan file;
the test data management module is used for executing management operation on the received test case data based on the structure verification plan file to obtain simulation data; the management operation comprises use case filtering, simulation option definition, simulation option modification, regression testing and data viewing;
and the chip simulation module is used for executing chip simulation operation based on a preset simulation flow and the simulation data to obtain a simulation result.
9. A server, comprising:
a memory for storing a computer program;
a processor for implementing the steps of the chip test case processing method according to any one of claims 1 to 7 when executing the computer program.
10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, carries out the steps of the chip test case processing method according to any one of claims 1 to 7.
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