CN117871921A - Single-channel multi-range automatic switching measurement circuit and load monitoring unit - Google Patents
Single-channel multi-range automatic switching measurement circuit and load monitoring unit Download PDFInfo
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Abstract
The invention discloses a single-channel multi-range automatic switching measuring circuit and a load monitoring unit. When the invention is applied, the hardware is adopted to automatically judge the range, the range is automatically switched, software control is not needed, the optimal gear is automatically matched, and the measurement precision is improved; meanwhile, the invention samples through one path of ADC, the measuring range is informed to the MCU by external hardware, the requirement of equipment on sampling ADC is greatly reduced, the cost is saved, the software writing is simplified, and the equipment is more stable.
Description
Technical Field
The invention relates to the field of automatic measurement, in particular to a single-channel multi-range automatic switching measurement circuit and a load monitoring unit.
Background
In the prior art, the multi-range measurement technology generally relies on software to control switching and uses multiple ADCs to sample, and the control mode controls switching through software, so that risks of software run-out and dead halt exist, and if the software is abnormal, the situation that errors cannot be detected or detected can occur. Meanwhile, when the measurement is performed in a software control switching mode, a plurality of measuring ranges are needed to occupy a plurality of ADC channels, and a host computer or an ADC which is required to be used needs to be matched with the measuring ranges to have a plurality of paths of ADCs, so that the cost is high.
Disclosure of Invention
The invention aims to overcome the defects that in the prior art, the multi-range measurement is in risk of software running and dead halt through software control range switching, so that detection is impossible or error is caused, a plurality of ADC channels are occupied when a plurality of ranges are measured, and the cost is high.
The aim of the invention is mainly realized by the following technical scheme:
in a first aspect, the present application provides a single-channel multi-range automatic switching measurement circuit comprising a measurement current input conversion circuit, a reference voltage generation circuit, a gear information generation circuit, a gear matching circuit, a voltage signal debugging circuit and a controller, wherein,
the gear information generating circuit comprises n comparators, n is more than or equal to 1, the non-inverting input end of each comparator inputs the voltage to be measured, the inverting input end of each comparator inputs the comparison voltage, and the output end of each comparator outputs gear information; the comparator is used for judging the gear information of an input power supply and outputting the gear information to the gear matching circuit and the controller;
The output end of the measuring current input conversion circuit is connected with the non-inverting input end of each comparator and is used for inputting a measured current, converting the measured current into a measured voltage and outputting the measured voltage to the gear information generation circuit;
the reference voltage generation circuit is used for outputting reference voltage and comparison voltage, wherein the reference voltage is divided to obtain n comparison voltages which are arranged from small to large, and the n comparison voltages are input to the inverting input ends of the n comparators in a one-to-one correspondence manner;
the gear matching circuit is connected with the measured current input conversion circuit to form a VI conversion circuit, the input end of the gear matching circuit is input with gear information, and the gear matching circuit is used for converting input measured currents of different gears into sampling voltages of the same gear according to the gear information and outputting the sampling voltages to the voltage signal debugging circuit;
the input end of the voltage signal debugging circuit is used for inputting sampling voltage, amplifying the sampling voltage and outputting the amplified sampling voltage to the controller so that the controller can sample the sampling voltage;
the controller is used for inputting gear information, identifying the input tested current gear according to the gear information, wherein the input tested current is the zeroth gear when the tested voltage is smaller than the first comparison voltage, and the input tested current is the nth gear when the tested voltage is larger than the nth comparison voltage; for inputting the amplified sampling voltage and sampling the sampling voltage.
In the process of measuring multiple ranges, the inventor finds that when the range is switched through software control, the software has risks of running and halting, if the software is abnormal, the situation that detection cannot be carried out or errors are detected can occur, meanwhile, the measurement of multiple ranges needs to be carried out by relying on multiple ADC (analog to digital converter), namely, when the measurement is carried out, a plurality of ranges need to occupy a plurality of ADC channels, and therefore a used host or ADC needs to have multiple ADC channels so as to match the multiple ranges, and the cost is high.
For this reason, based on the problems existing in the prior art described above, the inventors propose the present application to solve the problems existing in the prior art. In the application, a measuring current input conversion circuit, a reference voltage generation circuit, a gear information generation circuit, a gear matching circuit, a voltage signal debugging circuit and a controller are arranged, wherein the measuring current input conversion circuit is used for inputting measured currents, converting the measured currents into measured voltages, outputting the measured voltages to the gear information generation circuit and the gear matching circuit, the reference voltage generation circuit is used for outputting reference voltages and comparison voltages, the measured voltages output by the measuring current input conversion circuit are input into the gear information generation circuit, n comparators are arranged in the gear information generation circuit, the measured voltages are respectively input into non-inverting input ends of the n comparators, meanwhile, the reference voltage generation circuit outputs reference voltages, the reference voltages are divided to obtain n comparison voltages which are arranged from small to large, the obtained n comparison voltages are input into inverting input ends of the n comparators in a one-to-one correspondence mode, and at the moment, when the measured currents of different gears are input, the sizes of the converted measured voltages change along with the sizes of the measured currents. If the measured voltage is smaller than the minimum comparison voltage, namely the first comparison voltage, the output ends of all comparators output low level, the information is input to the controller, at the moment, the controller judges that the gear of the input measured current is the lowest gear according to the information that the output ends of all comparators output low level, namely the zeroth gear, when the measured voltage changes along with the input measured current from small to large, the measured voltage is gradually larger than all comparison voltages, the output ends of all comparators sequentially output high level, and the controller judges which gear the input measured current is in according to the comparator outputting high level. It is worth to say that, n comparison voltages with different magnitudes are n gears, and the actual measured gear is n+1 if the lowest gear is added with the zeroth gear. In the present application, the gear of the measured current is determined according to the number of comparators outputting high level, if the output ends of the comparators output low level, that is, the number of comparators outputting high level is zero, the input measured current is in the zeroth gear, if the output ends of n comparators output high level, the input measured current is in the nth gear, for example, the input measured current is in the third gear, at this time, the input value of the non-inverting input end of three comparators is greater than the input value of the inverting input end thereof, that is, the measured voltage is greater than the comparison voltage of the third gear, then three comparators output high level, and at this time, the input measured current is determined to be the third gear.
Besides judging the gear of the input tested current through hardware, the input tested current of different gears can be converted into the sampling voltage of the same gear, so that the tested current of a plurality of measuring ranges is sampled through one path of ADC, and the cost is saved. In the application, a gear matching circuit is further arranged and connected with the measuring current input conversion circuit, so that a VI conversion circuit is formed, and the input measured currents of different gears are converted into measured voltages of the same gear. In the application, the input end of the gear matching circuit is connected with the output end of the gear information generating circuit, namely the input end of the gear matching circuit is connected with the output ends of n comparators, when the tested currents of different gears are input, the gear information generating circuit generates different gear information and inputs the different gear information into the gear matching circuit, at the moment, the VI converting circuit formed by the gear matching circuit and the measured current input converting circuit converts the tested currents of different gears into sampling voltages of the same gear according to the different gear information, the sampling voltages are input to the voltage signal debugging circuit, and the voltage signal debugging circuit amplifies the sampling voltages and outputs the amplified sampling voltages to the controller. In the present application, since the shift information of the measured current is notified to the controller by the shift information generating circuit, even if the measured currents of different shift positions are converted into the sampling voltages of the same shift position to be sampled by the controller, it is possible to know from the shift information generated by the shift information generating circuit which shift position the final sampling voltage is converted from the measured current of which shift position, and to calculate the magnitude of the measured current according to the conversion process thereof.
Further, the measuring current input conversion circuit comprises a VI conversion resistor, and the two ends of the VI conversion resistor are input with the measured current, so that the input measured current is converted into the measured voltage, and the measured voltage is output to the gear information generation circuit.
Further, the gear matching circuit comprises n NMOS tubes and n sampling resistors; the S poles of the NMOS tubes are connected with a sampling resistor to form a series circuit, n NMOS tubes and n sampling resistors form n series circuits, n series circuits are connected in parallel to form a gear matching circuit, wherein the g poles of the n NMOS tubes are connected with the output ends of n comparators in a one-to-one correspondence manner, the d poles of the n NMOS tubes are connected with each other, the other ends of the n sampling resistors connected with the n NMOS tubes are grounded, and the gear matching circuit and the VI conversion resistor are connected in parallel to form a VI conversion circuit.
Further, the measuring current input conversion circuit further comprises a resistance compensation circuit, wherein the resistance compensation circuit is connected with the VI conversion circuit in series and is used for carrying out resistance compensation on the VI conversion circuit, so that the total resistance value of a series circuit formed by the resistance compensation circuit and the VI conversion circuit is always equal to the resistance value of the VI conversion resistor.
Further, the resistance compensation circuit comprises n selection switches which are connected in sequence, wherein a compensation resistor is connected between two adjacent selection switches, and the output end of the nth selection switch is connected with a compensation resistor; the selection switch comprises a first optical coupler, a diode, a second optical coupler and a triode; the first pin of the first optical coupler is connected with an external power supply through a first current limiting resistor, the second pin of the first optical coupler is connected with the ground through a diode, and the fourth pin of the first optical coupler is connected with a VI conversion resistor; the first pin of the second optical coupler is connected with the first pin of the first optical coupler, the second pin is connected with the collector electrode of the triode, and the fourth pin is connected with the compensation resistor; the base electrode of the triode is connected with the output end of the comparator through a second current limiting resistor and is grounded through a pull-down resistor, and the emitter electrode of the triode is grounded; the third pins of the first optocoupler and the second optocoupler of the first selector switch are respectively input with a current to be measured; the third pin of the first optical coupler is connected with the third pin of the second optical coupler, and is connected with the fourth pin of the second optical coupler of the last selection switch through a compensation resistor; and the fourth pin of the second optocoupler of the nth selection switch is connected with the VI conversion resistor through the compensation resistor.
Furthermore, the measured current input conversion circuit further comprises a TVS tube, wherein the TVS tube is connected with the VI conversion resistor in parallel and is used for protecting a later-stage circuit when the input measured current exceeds the maximum value of measurement.
Further, the reference voltage generating circuit comprises a reference voltage chip and a voltage dividing circuit, wherein the reference voltage chip is used for generating a reference voltage and inputting the reference voltage to the voltage dividing circuit; the voltage dividing circuit comprises n+1 voltage dividing resistors which are connected in series, wherein one end of the series circuit formed by connecting the n+1 voltage dividing resistors in series is input with reference voltage, the other end of the series circuit is grounded, and any two adjacent voltage dividing resistors are connected with the inverting input end of one comparator and used for inputting comparison voltages with different magnitudes to the comparator.
Further, in the gear information generating circuit, the output end of any comparator is externally connected with a pull-up resistor and a third current limiting resistor, and the other end of the pull-up resistor connected with the comparator is connected with an external power supply; the other end of the third current limiting resistor is connected with the controller.
Further, the voltage signal debugging circuit comprises an inverting amplifier and a differential amplifier, wherein the inverting input end of the inverting amplifier inputs sampling voltage, and the output end of the inverting amplifier is connected with the inverting input end of the differential amplifier; the non-inverting input end of the differential amplifier inputs the superposition voltage, the output end of the differential amplifier is connected with a filter circuit, and the output end of the differential amplifier is connected with a controller through the filter circuit and is used for providing the amplified sampling voltage for the controller; the superimposed voltage is one half of the reference voltage, so that the signal zero point of the sampling voltage finally input to the controller is in the middle of the effective range of the ADC sampling voltage.
In a second aspect, the present application further provides a load monitoring unit, including a single-channel multi-range automatic switching measurement circuit as described above.
In summary, compared with the prior art, the invention has the following beneficial effects: according to the invention, the hardware is adopted to automatically judge the range, the range is automatically switched, software control is not needed, the optimal gear is automatically matched, and the measurement precision is improved; according to the invention, sampling is carried out through one path of ADC, the measuring range is informed to the MCU by external hardware, so that the requirement of equipment on the sampling ADC is greatly reduced, the cost is saved, the software writing is simplified, and the equipment is more stable.
Drawings
The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and are incorporated in and constitute a part of this application, illustrate embodiments of the invention. In the drawings:
FIG. 1 is a schematic circuit diagram of a measurement current input conversion circuit according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a reference voltage chip and an external circuit thereof according to an embodiment of the present invention;
FIG. 3 is a schematic circuit diagram of a voltage divider circuit according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a portion of a gear information generating circuit according to an embodiment of the present invention;
FIG. 5 is a schematic circuit diagram of the rest of the shift information generating circuit according to an embodiment of the present invention;
FIG. 6 is a schematic circuit diagram of a gear matching circuit according to an embodiment of the present invention;
FIG. 7 is a schematic circuit diagram of a resistance compensation circuit according to an embodiment of the present invention;
fig. 8 is a schematic circuit diagram of a voltage signal debug circuit according to an embodiment of the present invention.
Detailed Description
For the purpose of making apparent the objects, technical solutions and advantages of the present invention, the present invention will be further described in detail with reference to the following examples and the accompanying drawings, wherein the exemplary embodiments of the present invention and the descriptions thereof are for illustrating the present invention only and are not to be construed as limiting the present invention.
Examples:
in a first aspect, the present embodiment provides a single-channel multi-range automatic switching measurement circuit, comprising a measurement current input conversion circuit, a reference voltage generation circuit, a gear information generation circuit, a gear matching circuit, a voltage signal debugging circuit and a controller, wherein,
the gear information generating circuit comprises n comparators, n is more than or equal to 1, the non-inverting input end of each comparator inputs the voltage to be measured, the inverting input end of each comparator inputs the comparison voltage, and the output end of each comparator outputs gear information; the comparator is used for judging the gear information of an input power supply and outputting the gear information to the gear matching circuit and the controller;
The output end of the measuring current input conversion circuit is connected with the non-inverting input end of each comparator and is used for inputting a measured current, converting the measured current into a measured voltage and outputting the measured voltage to the gear information generation circuit and the gear matching circuit;
the reference voltage generation circuit is used for outputting reference voltage and comparison voltage, wherein the reference voltage is divided to obtain n comparison voltages which are arranged from small to large, and the n comparison voltages are input to the inverting input ends of the n comparators in a one-to-one correspondence manner;
the gear matching circuit is connected with the measured current input conversion circuit to form a VI conversion circuit, the input end of the gear matching circuit is input with gear information, and the gear matching circuit is used for converting input measured currents of different gears into sampling voltages of the same gear according to the gear information and outputting the sampling voltages to the voltage signal debugging circuit;
the input end of the voltage signal debugging circuit is used for inputting sampling voltage, amplifying the sampling voltage and outputting the amplified sampling voltage to the controller so that the controller can sample the sampling voltage;
the controller is used for inputting gear information, identifying the input tested current gear according to the gear information, wherein the input tested current is the zeroth gear when the tested voltage is smaller than the first comparison voltage, and the input tested current is the nth gear when the tested voltage is larger than the nth comparison voltage; for inputting the amplified sampling voltage and sampling the sampling voltage.
In the process of measuring multiple ranges, the inventor finds that when the range is switched through software control, the software has risks of running and halting, if the software is abnormal, the situation that detection cannot be carried out or errors are detected can occur, meanwhile, the measurement of multiple ranges needs to be carried out by relying on multiple ADC (analog to digital converter), namely, when the measurement is carried out, a plurality of ranges need to occupy a plurality of ADC channels, and therefore a used host or ADC needs to have multiple ADC channels so as to match the multiple ranges, and the cost is high.
For this reason, based on the problems existing in the prior art described above, the inventors propose the present embodiment to solve the problems existing in the prior art. In this embodiment, a measurement current input conversion circuit, a reference voltage generation circuit, a gear information generation circuit, a gear matching circuit, a voltage signal debugging circuit and a controller are provided, wherein the measurement current input conversion circuit is used for inputting a measured current, converting the measured current into a measured voltage, and outputting the measured voltage to the gear information generation circuit and the gear matching circuit, the reference voltage generation circuit is used for outputting a reference voltage and a comparison voltage, the measured voltage output by the measurement current input conversion circuit is input into the gear information generation circuit, n comparators are provided in the gear information generation circuit, the measured voltage is respectively input into the non-inverting input ends of the n comparators, meanwhile, the reference voltage generation circuit outputs a reference voltage, the reference voltage is divided into n comparison voltages arranged from small to large, the obtained n comparison voltages are input into the inverting input ends of the n comparators one by one, and at this time, when the magnitude of the measured current is input, namely, when the measured currents of different gears are input, the magnitude of the converted measured voltage changes along with the magnitude of the measured current. If the measured voltage is smaller than the minimum comparison voltage, namely the first comparison voltage, the output ends of all comparators output low level, the information is input to the controller, at the moment, the controller judges that the gear of the input measured current is the lowest gear according to the information that the output ends of all comparators output low level, namely the zeroth gear, when the measured voltage changes along with the input measured current from small to large, the measured voltage is gradually larger than all comparison voltages, the output ends of all comparators sequentially output high level, and the controller judges which gear the input measured current is in according to the comparator outputting high level. It is worth to say that, n comparison voltages with different magnitudes are n gears, and the actual measured gear is n+1 if the lowest gear is added with the zeroth gear. In this embodiment, the gear of the measured current is determined according to the number of comparators outputting high levels, if the output terminals of each comparator output low levels, that is, the number of comparators outputting high levels is zero, the input measured current is in the zeroth gear, if the output terminals of n comparators output high levels, the input measured current is in the nth gear, for example, the input measured current is in the third gear, at this time, the input value of the non-inverting input terminal of three comparators is greater than the input value of the inverting input terminal thereof, that is, the measured voltage is greater than the comparison voltage of the third gear, and then three comparators output high levels, that is, the input measured current is determined to be in the third gear.
In the embodiment, besides judging the gear of the input tested current through hardware, the input tested current of different gears can be converted into the sampling voltage of the same gear, so that the tested current of a plurality of measuring ranges is sampled through one path of ADC, and the cost is saved. In this embodiment, a gear matching circuit is further provided, and the gear matching circuit is connected with the measured current input conversion circuit, so as to form a VI conversion circuit, so as to convert the input measured currents of different gears into the measured voltages of the same gear. In this embodiment, an input end of the gear matching circuit is connected to an output end of the gear information generating circuit, that is, an input end of the gear matching circuit is connected to output ends of n comparators, when measured currents of different gears are input, the gear information generating circuit generates different gear information and inputs the different gear information into the gear matching circuit, and at this time, a VI converting circuit formed by the gear matching circuit and the measured current input converting circuit converts the measured currents of different gears into sampling voltages of the same gear according to the different gear information, and inputs the sampling voltages to the voltage signal debugging circuit, and the voltage signal debugging circuit amplifies the sampling voltages and outputs the amplified sampling voltages to the controller. In this embodiment, since the shift information of the measured current is notified to the controller by the shift information generating circuit, even if the measured currents of different shift positions are converted into the sampling voltages of the same shift position to be sampled by the controller, it is possible to know from the shift information generated by the shift information generating circuit which shift position the finally sampled sampling voltage is converted from the measured current of which shift position, and to calculate the magnitude of the measured current from the conversion process thereof.
In one possible implementation manner, the measurement current input conversion circuit includes a VI conversion resistor, and the two ends of the VI conversion resistor are input with a measured current, so as to convert the input measured current into a measured voltage, and output the measured voltage to the gear information generation circuit.
In one possible implementation manner, the gear matching circuit comprises n NMOS tubes and n sampling resistors; the S poles of the NMOS tubes are connected with a sampling resistor to form a series circuit, n NMOS tubes and n sampling resistors form n series circuits, n series circuits are connected in parallel to form a gear matching circuit, wherein the g poles of the n NMOS tubes are connected with the output ends of n comparators in a one-to-one correspondence manner, the d poles of the n NMOS tubes are connected with each other, the other ends of the n sampling resistors connected with the n NMOS tubes are grounded, and the gear matching circuit and the VI conversion resistor are connected in parallel to form a VI conversion circuit.
Further, in order to prevent the VI conversion circuit formed by the parallel connection of the gear matching circuit and the VI conversion resistor from having different resistance values in different gears, so that the output measured voltage changes in the same gear, and further the gear information is disordered, the measurement current input conversion circuit further comprises a resistance compensation circuit, and the resistance compensation circuit is connected in series with the VI conversion circuit and is used for performing resistance compensation on the VI conversion circuit, so that the total resistance value of the series circuit formed by the resistance compensation circuit and the VI conversion circuit is always equal to the resistance value of the VI conversion resistor.
In one possible implementation manner, the resistance compensation circuit comprises n selection switches connected in sequence, wherein a compensation resistor is connected between two adjacent selection switches, and the output end of the nth selection switch is connected with a compensation resistor; the selection switch comprises a first optical coupler, a diode, a second optical coupler and a triode; the first pin of the first optical coupler is connected with an external power supply through a first current limiting resistor, the second pin of the first optical coupler is connected with the ground through a diode, and the fourth pin of the first optical coupler is connected with a VI conversion resistor; the first pin of the second optical coupler is connected with the first pin of the first optical coupler, the second pin is connected with the collector electrode of the triode, and the fourth pin is connected with the compensation resistor; the base electrode of the triode is connected with the output end of the comparator through a second current limiting resistor and is grounded through a pull-down resistor, and the emitter electrode of the triode is grounded; the third pins of the first optocoupler and the second optocoupler of the first selector switch are respectively input with a current to be measured; the third pin of the first optical coupler is connected with the third pin of the second optical coupler, and is connected with the fourth pin of the second optical coupler of the last selection switch through a compensation resistor; and the fourth pin of the second optocoupler of the nth selection switch is connected with the VI conversion resistor through the compensation resistor. In this embodiment, the diode functions as a matching potential, so that when the output terminal of the comparator outputs a high level, the base of the triode inputs a high level, the second optocoupler is turned on, and the first optocoupler is turned off.
In one possible implementation, the measured current input conversion circuit further includes a TVS tube connected in parallel with the VI conversion resistor for protecting the subsequent stage circuit when the input measured current exceeds the measured maximum value.
In one possible implementation manner, the reference voltage generating circuit includes a reference voltage chip and a voltage dividing circuit, where the reference voltage chip is used to generate a reference voltage and input the reference voltage to the voltage dividing circuit; the voltage dividing circuit comprises n+1 voltage dividing resistors which are connected in series, wherein one end of the series circuit formed by connecting the n+1 voltage dividing resistors in series is input with reference voltage, the other end of the series circuit is grounded, and any two adjacent voltage dividing resistors are connected with the inverting input end of one comparator and used for inputting comparison voltages with different magnitudes to the comparator.
In one possible implementation manner, in the gear information generating circuit, the output end of any comparator is externally connected with a pull-up resistor and a third current limiting resistor, and the other end of the pull-up resistor connected with the comparator is connected with an external power supply; the other end of the third current limiting resistor is connected with the controller.
In one possible implementation manner, the voltage signal debugging circuit comprises an inverting amplifier and a differential amplifier, wherein the inverting input end of the inverting amplifier inputs a sampling voltage, and the output end of the inverting amplifier is connected with the inverting input end of the differential amplifier; the non-inverting input end of the differential amplifier inputs the superposition voltage, the output end of the differential amplifier is connected with a filter circuit, and the output end of the differential amplifier is connected with a controller through the filter circuit and is used for providing the amplified sampling voltage for the controller; the superimposed voltage is one half of the reference voltage, so that the signal zero point of the sampling voltage finally input to the controller is in the middle of the effective range of the ADC sampling voltage.
In a second aspect, the present embodiment further provides a load monitoring unit, including a single-channel multi-range automatic switching measurement circuit as described above.
In order to better understand and describe a single-channel multi-range automatic switching circuit in the present solution, the present solution is further described below with reference to specific embodiments.
The embodiment is a single-channel five-range automatic switching measurement circuit, as shown in fig. 1-8, which is a schematic circuit diagram of the embodiment, wherein fig. 1 shows a schematic circuit diagram of a current input conversion circuit of the embodiment, in fig. 1, the current input conversion circuit includes a pin H1, a TVS tube D1 and a VI conversion resistor R14, wherein the TVS tube D1 and the VI conversion resistor R14 are connected in parallel to form a parallel circuit, and two pins of the pin H1 are respectively connected with two ends of the parallel circuit to input external measured current IA to the parallel circuit, and the VI conversion resistor R14 converts the measured current IA into measured voltage VIN1 and outputs the measured voltage VIN1 to the outside. Specifically, the first pin and the second pin of the pin H1 are respectively connected to two ends of the TVS tube D1 and the VI switching resistor R14, and the first pin of the pin H1 is grounded. Preferably, the pin H1 in this embodiment is of the type PZ254V-11-02P.
Fig. 2 is a schematic diagram of a reference voltage chip U1 and an external circuit thereof according to the present embodiment, in fig. 2, a first pin of the reference voltage chip U1 outputs a reference voltage VBIAS, and a fifth pin outputs a reference voltage VREF, wherein the first pin is connected with a filter capacitor C5, the other end of the filter capacitor C5 connected with the first pin is grounded, the fifth pin is connected with a filter capacitor C1, and the other end of the filter capacitor C1 connected with the fifth pin is grounded; the second pin of the reference voltage chip U1 is grounded; the third pin and the fourth pin of the reference voltage chip are communicated and connected with an external power supply VCC, wherein two capacitors C3 and C2 which are connected in parallel are connected when the external power supply VCC is connected to the reference voltage chip U1, and the other ends of the capacitors C3 and C2 connected with the external power supply VCC are grounded. In the present embodiment, the reference voltage chip U1 is used to externally provide the reference voltage VREF and the reference voltage VBIAS. In this embodiment, the reference voltage chip is REF2025AIDDCR, and the handbook of the chip indicates that the reference voltage VBIAS is one half of the reference voltage VREF, and the output reference voltage vref=2.5v.
Fig. 3 is a schematic circuit diagram of a voltage divider circuit in this embodiment, in fig. 3, the voltage dividing resistors R1 to R5 are equal in resistance and connected in series, and the other end of each of the voltage dividing resistors R1 to R2 is connected to a fifth pin of the reference voltage chip U1, and the other end of each of the voltage dividing resistors R5 to R4 is grounded. In the voltage dividing circuit, a reference voltage VREF is divided by five voltage dividing resistors R1-R5 connected in series to obtain four comparison voltages of 0.2VREF, 0.4VREF, 0.6VREF and 0.8VREF respectively.
Fig. 4 is a schematic diagram of a partial circuit of the gear information generating circuit of the present embodiment, including four comparators and four pull-up resistors, wherein the non-inverting input ends of the four comparators are all connected with the output end of the measuring current input converting circuit, namely connected in parallel with R14, and input the measured voltage VIN1, wherein the inverting input end of the comparator U2 is connected in parallel between R1 and R2, and input a 0.8VREF comparison voltage, the output end of the comparator U2 outputs the gear information KC4, and the output end of the comparator U2 is connected to the external power VCC through the pull-up resistor R6; the reverse input end of the comparator U3 is connected in parallel between R2 and R3, a 0.6VREF comparison voltage is input, the output end of the comparator U3 outputs gear information KC3, and the output end of the comparator U3 is connected with an external power supply VCC through a pull-up resistor R7; the reverse input end of the comparator U4 is connected in parallel between R3 and R4, a 0.4VREF comparison voltage is input, the output end of the comparator U4 outputs gear information KC2, and the output end of the comparator U4 is connected with an external power supply VCC through a pull-up resistor R8; the reverse input end of the comparator U5 is connected in parallel between R4 and R5, a 0.2VREF comparison voltage is input, the output end of the comparator U5 outputs gear information KC1, and the output end of the comparator U5 is connected with an external power supply VCC through a pull-up resistor R9. In this embodiment, fig. 5 includes four third current limiting resistors, where one ends of the four third current limiting resistors are respectively connected to the output ends of the four comparators, and the other ends of the four third current limiting resistors are respectively connected to the controller, so that the purpose of informing the controller of the gear information through the third current limiting resistors is to facilitate calculation and input. In this embodiment, there are 5 ranges of input, when the input measured current IA is in the first range, the measured voltage VIN1 obtained by conversion is greater than 0.2VREF, at this time, the output of the comparator U5 is high, the output of the remaining three comparators is low, the gear information KC1 is output, and the third current limiting resistor R22 informs the controller of the gear information KC1, so that the controller determines that the input measured current IA is in the first range; when the input measured current IA is in the second gear, the measured voltage VIN1 obtained through conversion is larger than 0.4VREF, the comparator U5 and the comparator U4 output high levels, the other two comparators output low levels, gear information KC1 and KC2 are output, and the third current limiting resistors R22 and R23 inform the controller of the gear information KC1 and KC2, so that the controller judges that the input measured current IA is in the second gear; when the input measured current IA is in the third gear, the measured voltage VIN1 obtained through conversion is larger than 0.6VREF, the comparator U5, the comparator U4 and the comparator U3 output high levels, the comparator U2 outputs low levels, gear information KC1, KC2 and KC3 are output, and the third current limiting resistors R22, R23 and R24 inform the controller of the gear information KC1, KC2 and KC3, so that the controller judges that the input measured current IA is in the third gear; when the input measured current IA is in the fourth gear, the measured voltage VIN1 obtained through conversion is larger than 0.8VREF, at the moment, the output of the four comparators is high level, gear information KC1, KC2, KC3 and KC4 are output, and the third current limiting resistors R22, R23, R24 and R25 inform the controller of the gear information KC1, KC2, KC3 and KC4, so that the controller judges that the input measured current IA is in the fourth gear; besides the four gears, the device also comprises a zeroth gear, when the input measured current IA is very small, namely the measured voltage VIN1 obtained through conversion is smaller than 0.2VREF, the output ends of the four comparators output low level and no gear information is output, so that the controller judges that the measured current IA is in the zeroth gear according to the low level output by the four comparators; when the input measured current IA suddenly changes to cause the input measured current IA to exceed the measuring range, the TVS tube D1 in the current input conversion circuit is started at the moment to protect the subsequent circuit, so that equipment damage is prevented. In this embodiment, the power supplies of the four comparators are all external power VCC. Preferably, in the embodiment, the comparators U2-U5 are all of the type AP331AWG-7.
Fig. 6 is a schematic circuit diagram of a gear matching circuit in this embodiment, in fig. 6, the gear matching circuit includes four NMOS tubes and four sampling resistors, d poles of the four NMOS tubes are connected to each other, wherein g pole of an NMOS tube Q1 is connected to an output end of a comparator U5, s pole is connected to a sampling resistor R13, and the other end of the sampling resistor R13 connected to an NMOS tube Q1 is grounded; the g pole of the NMOS tube Q2 is connected with the output end of the comparator U4, the s pole is connected with the sampling resistor R15, and the other end of the sampling resistor R15 connected with the NMOS tube Q2 is grounded; the g pole of the NMOS tube Q3 is connected with the output end of the comparator U3, the s pole is connected with the sampling resistor R19, and the other end of the sampling resistor R19 connected with the NMOS tube Q3 is grounded; the g pole of the NMOS tube Q4 is connected with the output end of the comparator U2, the s pole is connected with the sampling resistor R21, and the other end of the sampling resistor R21 connected with the NMOS tube Q4 is grounded. In this embodiment, the d-pole of the NMOS transistor Q4 is connected to the output end of the measurement current input conversion circuit, that is, to the VI conversion resistor R14, so that R14 is connected in parallel with the gear matching circuit to form the VI conversion circuit, and the converted sampling voltage VIN is output from the d-pole of Q1. In this embodiment, when the input measured current IA is small, the measured voltage VIN1 obtained by the conversion of the measured current input conversion circuit is smaller than 0.2VREF, the outputs of the four comparators are all low level, and the four NMOS transistors are all not opened, so that the output measured voltage VIN1 directly enters the voltage signal debugging circuit, the measured voltage VIN1 entering the voltage signal debugging circuit is in the zeroth gear, and the input measured current IA is in the zeroth gear; when the input measured current IA changes from small to large, the measured voltage VIN1 obtained by conversion of the measured current input conversion circuit changes from small to large, the four comparators sequentially output high levels, so that the four NMOS tubes are sequentially opened, the four sampling resistors are connected with the VI conversion resistor R14 in parallel along with the opening of the four NMOS tubes, the input measured current IA is subjected to VI conversion, the obtained sampling voltage VIN is output from the d pole of the NMOS tube Q1, at the moment, the resistance values of the VI conversion resistor R14 and the four sampling resistors are properly designed, so that the sampling voltage VIN finally obtained by conversion of the measured current IA is input into the same gear in each gear, namely, the zero gear, and the final sampling can be completed only by one ADC.
Specifically, in the present embodiment, the reference voltage vref=2.5v, the vi conversion resistor R14 resistance is set to 2.5Ω, the sampling resistor R13 resistance is set to 2.5Ω, the sampling resistor R15 resistance is set to 2.5Ω, the sampling resistor R19 resistance is set to 2.5Ω, the sampling resistor R21 resistance is set to 2.5Ω, and the input measured current IA is divided into five ranges, that is, five gear steps: zero gear 0-200mA, first gear 200-400mA, second gear 400-600mA, third gear 600-800mA, fourth gear 800-1000mA, at this time, the maximum sampling voltage VIN of output that each gear conversion got is: zero th gear: vin=r14×ia=0.5v; first gear: vin=r14// r13×ia=0.5V; second gear: vin=r14// r13// r15xia=0.5v; third gear: vin=r14// r13// r15// r19xia=0.5V; fourth gear: vin=r14// r13// r15// r19// r21×ia=0.5V. And the output maximum sampling voltage VIN finally converted by each gear is 0.5V, so that the input measured current IA of each gear is converted into the sampling voltage VIN of the zeroth gear, and the sampling can be finished by only one path of ADC. It should be noted that, in the embodiment, when the input measured current IA is in the zeroth gear, the gear matching circuit does not work, and the output measured voltage VIN1 is equal to the sampling voltage VIN of the input voltage signal debugging circuit, that is, the measured voltage VIN1 is the sampling voltage VIN.
In the above embodiment, when the measured current IA is not in the zeroth gear, due to the opening of the NMOS tube, the resistance of the VI conversion resistor R14 is restored to be equal to the resistance of the VI conversion resistor R14, so that the resistance of the VI conversion circuit formed by the VI conversion resistor R14 and the gear matching circuit is reduced, the measured voltage VIN1 output by the measured current input conversion circuit is reduced, the measured voltage VIN1 may be lower than the comparison voltage of the current gear, the NMOS tube is closed, the sampling voltage VIN at this time is increased, the sampling voltage VIN of the current gear may be greater than the sampling voltage VIN of the zeroth gear, and due to the closing of the NMOS tube, the resistance of the VI conversion circuit is restored to be equal to the resistance of the VI conversion resistor R14, so that the NMOS tube is opened, the resistance of the VI conversion circuit is reduced, and the NMOS tube is closed, so that the NMOS tube is closed, and the service life of the NMOS tube is affected. Taking third gear 600-800mA as an example, when the input measured current IA is 700mA, the output measured voltage VIN1 is 1.75V and is larger than the comparison voltage 0.6VREF, the comparators U3, U4 and U5 all output high level, U2 outputs low level, the gear information KC1, KC2 and KC3 are output, the gear information received by the controller is the third gear, the NMOS transistors Q1, Q2 and Q3 are all opened, the sampling voltage VIN is 0.4375V, and the resistance value of the VI conversion circuit is R14// R13// R15// R19=0.625 omega at the moment, the measured voltage VIN1 will generate voltage drop, the output measured voltage VIN1 will become 0.4375V, therefore, the output measured voltage VIN1 is smaller than 0.2VREF, the comparators U2-U5 all output low level, at this time, the gear information received by the controller is zero gear, the NMOS transistors Q1, Q2 and Q3 are all closed, the sampling voltage VIN becomes 1.75V and cannot be acquired, the output measured voltage VIN1 becomes 1.75V because the NMOS transistors Q1, Q2 and Q3 are all closed, the comparators U3, U4 and U5 are all output high level again, the U2 outputs low level, the gear information KC1, KC2 and KC3 are output, at this time, the gear information received by the controller is third gear, the NMOS transistors Q1, Q2 and Q3 are all opened, and the sampling voltage VIN is 0.4375V. Due to the continuous switching of the NMOS transistors Q1, Q2 and Q3, the output measured voltage VIN1 and the sampling voltage VIN continuously jump, and the gear information received by the controller also continuously changes between the third gear and the zeroth gear, so that the acquisition of the gear information and the sampling voltage VIN is affected. For this reason, in this embodiment, the measurement current input conversion circuit further includes a resistance compensation circuit, so that the total resistance of the series circuit formed by the resistance compensation circuit and the VI conversion circuit is always equal to the resistance of the VI conversion resistor.
As shown in fig. 7, a resistance compensation circuit is connected in series with the VI switching resistor R14 in fig. 1. The resistance compensation circuit comprises eight optocouplers, four diodes and four triodes, wherein a first pin of the optocoupler U11 is connected with an external power supply VCC through a first current limiting resistor R35, a second pin is grounded through a diode D2, a third pin is connected with a second pin of the pin H1 and used for inputting a tested current IA, and a fourth pin is grounded through a VI conversion resistor R14; the first pin of the optocoupler U12 is connected with the first pin of the optocoupler U11, the second pin is connected with the collector electrode of the triode Q5, the third pin is connected with the third pin of the optocoupler U11, and the fourth pin is connected with the compensation resistor R31; the base electrode of the triode Q5 is connected with the output end of the comparator U5 through a second current limiting resistor R39, and is grounded through a pull-down resistor R40, and the emitter electrode of the triode Q5 is grounded; the first pin of the optocoupler U13 is connected with an external power supply VCC through a first current limiting resistor R36, the second pin is grounded through a diode D3, the third pin is connected with the fourth pin of the optocoupler U12 through a compensation resistor R31, and the fourth pin is connected with the fourth pin of the optocoupler U11; the first pin of the optocoupler U14 is connected with the first pin of the optocoupler U13, the second pin is connected with the collector electrode of the triode Q6, the third pin is connected with the third pin of the optocoupler U13, and the fourth pin is connected with the compensation resistor R32; the base electrode of the triode Q6 is connected with the output end of the comparator U4 through a second current limiting resistor R41, and is grounded through a pull-down resistor R42, and the emitter electrode of the triode Q6 is grounded; the first pin of the optocoupler U15 is connected with an external power supply VCC through a first current limiting resistor R37, the second pin is grounded through a diode D4, the third pin is connected with the fourth pin of the optocoupler U14 through a compensation resistor R32, and the fourth pin is connected with the fourth pin of the optocoupler U11; the first pin of the optocoupler U16 is connected with the first pin of the optocoupler U15, the second pin is connected with the collector electrode of the triode Q7, the third pin is connected with the third pin of the optocoupler U15, and the fourth pin is connected with the compensation resistor R33; the base electrode of the triode Q7 is connected with the output end of the comparator U3 through a second current limiting resistor R43 and is grounded through a pull-down resistor R44, and the emitter electrode of the triode Q7 is grounded; the first pin of the optocoupler U17 is connected with an external power supply VCC through a first current limiting resistor R38, the second pin is grounded through a diode D5, the third pin is connected with the fourth pin of the optocoupler U16 through a compensation resistor R33, and the fourth pin is connected with the fourth pin of the optocoupler U11; the first pin of the optocoupler U18 is connected with the first pin of the optocoupler U17, the second pin is connected with the collector electrode of the triode Q8, the third pin is connected with the third pin of the optocoupler U17, and the fourth pin is connected with the compensation resistor R34; the base electrode of the triode Q8 is connected with the output end of the comparator U2 through a second current limiting resistor R45 and is grounded through a pull-down resistor R46, and the emitter electrode of the triode Q8 is grounded; the compensation resistor R34 is connected to the fourth pin of the optocoupler U11 at the other end opposite to the connection optocoupler U18.
In the present embodiment, the resistance values of the compensation resistors R31, R32, R33, R34 are set to 1.25Ω, 0.42Ω, 0.205 Ω, 0.125Ω, respectively. When the first-gear measured current IA is input, the output end of the optocoupler U11 is conducted, the input measured current IA is converted into a measured voltage VIN1 through a VI converting resistor R14, and is input into comparators U2-U5 for comparison with comparison voltage, at the moment, the comparators U5 output high level, the comparators U2, U3 and U4 output low level, gear information KC1 is output, at the moment, an NMOS tube Q1 is conducted, NMOS tubes Q2-Q4 are closed, a triode Q5 is conducted, optocouplers U12 and U13 are conducted, other optocouplers are closed, at the moment, the measured current IA flows through the optocoupler U12, a compensating resistor R31, the optocoupler U13, a VI converting resistor R14, an NMOS tube Q1 and a sampling resistor R13, at the moment, the measured current IA is converted into the measured voltage 1, the total resistance value of the circuit is R31+R14// R13=2.5Ω=R14, and the maximum value of the sampling voltage VIN is=R14// R11xIA=0.5V; when the detected current IA of the second gear is input, the output end of the optocoupler U11 is conducted, the input detected current IA is converted into the detected voltage VIN1 through the VI converting resistor R14, and is input into the comparators U2-U5 to be compared with the comparison voltage, the comparators U5 and U4 output high level at the moment, the comparators U2 and U3 output low level at the moment, the gear information KC1 and KC2 are output, the NMOS tubes Q1 and Q2 are conducted at the moment, the NMOS tubes Q3 and Q4 are closed, the triodes Q5 and Q6 are conducted, the optocouplers U12, U14 and U15 are conducted, the other optocouplers are closed, the measured current IA flows through the optocoupler U12, the compensation resistor R31, the optocoupler U14, the compensation resistor R32, the optocoupler U15, the VI converting resistor R14, the NMOS transistors Q1 and Q2 and the sampling resistors R13 and R15, the measured current IA is converted into the measured voltage VIN1, the total resistance value of the circuit is R31+R32+R14// R13// R15=2.5Ω=R14, and the maximum value of the sampling voltage VIN is VIN=R14// R13// R15×IA=0.5V; when the third-gear measured current IA is input, the output end of the optocoupler U11 is conducted, the input measured current IA is converted into the measured voltage VIN1 through the VI conversion resistor R14, and is input into the comparators U2-U5 for comparison with the comparison voltage, at this time, the comparators U3-U5 output high levels, the comparators U2 output low levels, the gear information KC1, KC2 and KC3 are output, at this time, the NMOS transistors Q1-Q3 are conducted, the NMOS transistor Q4 is closed, the audion Q5-Q7 is conducted, the optocouplers U12, U14, U16 and U17 are conducted, the rest of the optocouplers are closed, at this time, the measured current IA flows through the optocoupler U12, the compensation resistor R31, the optocoupler U14, the compensation resistor R32, the optocoupler U16, the compensation resistor R33, the optocoupler U17, the VI conversion resistor R14, the NMOS transistors Q1-Q3, the sampling resistors R13, R15 and R19, at this time, the measured current is converted into the measured voltage 1, the NMOS transistors Q1-Q3, the NMOS transistors Q4 are closed, the audion 5-Q7 is conducted, the total resistance value of the circuit is R31+r32+r14/v14=r14/v14=v15/v1=v14.v14=v15/v15=r15/v1=r15=r15/v1; when the fourth-gear measured current IA is input, the output end of the optocoupler U11 is conducted, the input measured current IA is converted into the measured voltage VIN1 through the VI conversion resistor R14, and is input to the comparators U2-U5 for comparison with the comparison voltage, at this time, the comparators U2-U5 all output high levels, the output gear information KC1, KC2, KC3 and KC4 are conducted, at this time, the NMOS transistors Q1-Q4 are conducted, the triodes Q5-Q8 are conducted, the optocouplers U12, U14, U16 and U18 are conducted, the rest of the optocouplers are closed, at this time, the measured current IA flows through the optocoupler U12, the compensation resistor R31, the optocoupler U14, the compensation resistor R32, the optocoupler U16, the compensation resistor R33, the optocoupler U18, the compensation resistor R34, the VI conversion resistor R14, the NMOS transistors Q1-Q4, the sampling resistors R13, R15, R19 and R21 are converted into the measured voltage 1, at this time, the total resistance value of the circuit is R31 +r32+r33+r19/VIN/R14/i14/i2=r14/i2+r14/i14// i2=r14/i2/i2+r14/i2=r14/i2/R4.
Fig. 8 is a schematic circuit diagram of the voltage signal debug circuit of the present embodiment, and in fig. 8, an inverting amplifier and a differential amplifier are included. As shown in fig. 8, one end of the resistor R11 is grounded, and the other end thereof is connected to the non-inverting input terminal of the operational amplifier U6; one end of the resistor R10 is connected with the output end of the gear matching circuit, namely connected with the d pole of the NMOS tube, and the other end of the resistor R is connected with the inverting input end of the operational amplifier U6; and a feedback resistor R12 is connected between the inverting input end and the output end of the operational amplifier U6, so that the inverting amplifier is formed. One end of the resistor R16 is connected with the output end of the operational amplifier U6, and the other end of the resistor R is connected with the inverting input end of the operational amplifier U7; one end of the resistor R26 is connected with the reference voltage VBIAS, and the other end of the resistor R is connected with the non-inverting input end of the operational amplifier U7; one end of the resistor R27 is grounded, and the other end of the resistor R is connected with the non-inverting input end of the operational amplifier U7; and a feedback resistor R18 is connected between the inverting input end and the non-inverting input end of the operational amplifier U7, so that a differential amplifier is formed. The output end of the operational amplifier U7 is connected with an RC filter circuit, and the RC filter circuit is connected with a controller so as to perform ADC sampling, wherein the RC filter circuit comprises a resistor R20 and a capacitor C4, and two ends of the resistor R20 are respectively connected with the output end of the operational amplifier U7 and the controller; one end of the capacitor C4 is connected to the resistor R20, and the other end is grounded. In this embodiment, the input sampling voltage VIN is amplified by an inverting amplifier, and then the amplified sampling voltage VIN is superimposed with the reference voltage VBIAS by a differential amplifier, so that the output voltage signal zero is in the middle of the ADC sampling range, so that positive and negative signals can be conveniently sampled, and the sampled voltage Vadc1 is finally output after filtering by a filter circuit composed of a capacitor C4 and a resistor R20. Specifically, in the present embodiment, the input sampling voltage VIN is amplified 30 times. In this embodiment, the power supplies of the two operational amplifiers are both the reference voltage VREF provided by the reference voltage chip U1. Preferably, in the present embodiment, the model numbers of the operational amplifiers U6 and U7 are TLV333IDBVR.
The foregoing description of the embodiments has been provided for the purpose of illustrating the general principles of the invention, and is not meant to limit the scope of the invention, but to limit the invention to the particular embodiments, and any modifications, equivalents, improvements, etc. that fall within the spirit and principles of the invention are intended to be included within the scope of the invention.
Claims (10)
1. A single-channel multi-range automatic switching measuring circuit is characterized by comprising a measuring current input conversion circuit, a reference voltage generating circuit, a gear information generating circuit, a gear matching circuit, a voltage signal debugging circuit and a controller, wherein,
the gear information generating circuit comprises n comparators, n is more than or equal to 1, the non-inverting input end of each comparator inputs the voltage to be measured, the inverting input end of each comparator inputs the comparison voltage, and the output end of each comparator outputs gear information; the comparator is used for judging the gear information of an input power supply and outputting the gear information to the gear matching circuit and the controller;
the output end of the measuring current input conversion circuit is connected with the non-inverting input end of each comparator and is used for inputting a measured current, converting the measured current into a measured voltage and outputting the measured voltage to the gear information generation circuit;
The reference voltage generation circuit is used for outputting reference voltage and comparison voltage, wherein the reference voltage is divided to obtain n comparison voltages which are arranged from small to large, and the n comparison voltages are input to the inverting input ends of the n comparators in a one-to-one correspondence manner;
the gear matching circuit is connected with the measured current input conversion circuit to form a VI conversion circuit, the input end of the gear matching circuit is input with gear information, and the gear matching circuit is used for converting input measured currents of different gears into sampling voltages of the same gear according to the gear information and outputting the sampling voltages to the voltage signal debugging circuit;
the input end of the voltage signal debugging circuit is used for inputting sampling voltage, amplifying the sampling voltage and outputting the amplified sampling voltage to the controller so that the controller can sample the sampling voltage;
the controller is used for inputting gear information, identifying the input tested current gear according to the gear information, wherein the input tested current is the zeroth gear when the tested voltage is smaller than the first comparison voltage, and the input tested current is the nth gear when the tested voltage is larger than the nth comparison voltage; for inputting the amplified sampling voltage and sampling the sampling voltage.
2. The single-channel multi-range automatic switching measurement circuit according to claim 1, wherein the measurement current input conversion circuit comprises a VI conversion resistor, and the two ends of the VI conversion resistor are used for inputting a measured current, converting the inputted measured current into a measured voltage, and outputting the measured voltage to the gear information generation circuit.
3. The single-channel multi-range automatic switching measurement circuit according to claim 2, wherein the gear matching circuit comprises n NMOS tubes and n sampling resistors; the S poles of the NMOS tubes are connected with a sampling resistor to form a series circuit, n NMOS tubes and n sampling resistors form n series circuits, n series circuits are connected in parallel to form a gear matching circuit, wherein the g poles of the n NMOS tubes are connected with the output ends of n comparators in a one-to-one correspondence manner, the d poles of the n NMOS tubes are connected with each other, the other ends of the n sampling resistors connected with the n NMOS tubes are grounded, and the gear matching circuit and the VI conversion resistor are connected in parallel to form a VI conversion circuit.
4. A single-channel multi-range automatic switching measurement circuit according to claim 3, wherein the measurement current input conversion circuit further comprises a resistance compensation circuit, the resistance compensation circuit is connected in series with the VI conversion circuit, and is used for performing resistance compensation on the VI conversion circuit, so that the total resistance of a series circuit formed by the resistance compensation circuit and the VI conversion circuit is always equal to the resistance of the VI conversion resistor.
5. The single-channel multi-range automatic switching measurement circuit according to claim 4, wherein the resistance compensation circuit comprises n selection switches connected in sequence, wherein a compensation resistor is connected between two adjacent selection switches, and the output end of the nth selection switch is connected with a compensation resistor; the selection switch comprises a first optical coupler, a diode, a second optical coupler and a triode; the first pin of the first optical coupler is connected with an external power supply through a first current limiting resistor, the second pin of the first optical coupler is connected with the ground through a diode, and the fourth pin of the first optical coupler is connected with a VI conversion resistor; the first pin of the second optical coupler is connected with the first pin of the first optical coupler, the second pin is connected with the collector electrode of the triode, and the fourth pin is connected with the compensation resistor; the base electrode of the triode is connected with the output end of the comparator through a second current limiting resistor and is grounded through a pull-down resistor, and the emitter electrode of the triode is grounded; the third pins of the first optocoupler and the second optocoupler of the first selector switch are respectively input with a current to be measured; the third pin of the first optical coupler is connected with the third pin of the second optical coupler, and is connected with the fourth pin of the second optical coupler of the last selection switch through a compensation resistor; and the fourth pin of the second optocoupler of the nth selection switch is connected with the VI conversion resistor through the compensation resistor.
6. The single-channel multi-range automatic switching measurement circuit according to claim 2, wherein the measurement current input conversion circuit further comprises a TVS tube connected in parallel with the VI conversion resistor for protecting the latter stage circuit when the input measured current exceeds the measurement maximum value.
7. The single-channel multi-range automatic switching measurement circuit according to claim 1, wherein the reference voltage generation circuit comprises a reference voltage chip and a voltage division circuit, the reference voltage chip is used for generating a reference voltage, and the reference voltage is input to the voltage division circuit; the voltage dividing circuit comprises n+1 voltage dividing resistors which are connected in series, wherein one end of the series circuit formed by connecting the n+1 voltage dividing resistors in series is input with reference voltage, the other end of the series circuit is grounded, and any two adjacent voltage dividing resistors are connected with the inverting input end of one comparator and used for inputting comparison voltages with different magnitudes to the comparator.
8. The single-channel multi-range automatic switching measurement circuit according to claim 1, wherein in the gear information generation circuit, the output end of any comparator is externally connected with a pull-up resistor and a third current limiting resistor, and the other end of the pull-up resistor connected with the comparator is connected with an external power supply; the other end of the third current limiting resistor is connected with the controller.
9. The single-channel multi-range automatic switching measurement circuit according to claim 1, wherein the voltage signal debugging circuit comprises an inverting amplifier and a differential amplifier, wherein the inverting input end of the inverting amplifier inputs sampling voltage, and the output end of the inverting amplifier is connected with the inverting input end of the differential amplifier; the non-inverting input end of the differential amplifier inputs the superposition voltage, the output end of the differential amplifier is connected with a filter circuit, and the output end of the differential amplifier is connected with a controller through the filter circuit and is used for providing the amplified sampling voltage for the controller; the superimposed voltage is one half of the reference voltage, so that the signal zero point of the sampling voltage finally input to the controller is in the middle of the effective range of the ADC sampling voltage.
10. Load monitoring unit, characterized by comprising a single-channel multi-range automatic switching measurement circuit according to any of claims 1 to 9.
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