CN117856587A - SiC MOSFET driving circuit, control chip and switching power supply - Google Patents

Abstract

The invention relates to the technical field of SiC MOSFET driving, and discloses a SiC MOSFET driving circuit, a control chip and a switching power supply, wherein the SiC MOSFET driving circuit comprises an upper switching unit, a lower switching unit, a negative-pressure charge pump, a clamping unit, a level conversion unit and a signal processing unit; when the high-level signal is required to be output in actual use, the voltage at the output end of the upper switch unit can be clamped to the target voltage through the clamping unit; when a low-level signal is required to be output, negative pressure is provided by the negative pressure charge pump, and the output end of the upper switch unit is set to be negative pressure by the level conversion unit and the signal processing unit, so that the SiC MOSFET is prevented from being turned on by mistake due to grid crosstalk during the turn-off period.

Description

SiC MOSFET driving circuit, control chip and switching power supply

Technical Field

The invention relates to the technical field of SiC MOSFET driving, in particular to a SiC MOSFET driving circuit, a control chip and a switching power supply.

Background

The PWM driving technology is an important electronic control technology which is widely applied to various fields such as motor control, power management, illumination control and the like, and the main principle is that a reference signal is compared with a sawtooth wave signal through a comparator so as to generate a pulse signal with adjustable width, and the controlled object is controlled by adjusting the pulse width of the square wave signal, wherein the controlled object is mostly based on a silicon-based MOSFET, and the output voltage is controlled by controlling the on-off of the silicon-based MOSFET.

In the conventional PWM-driven circuit architecture, it is almost always used for driving a silicon-based MOSFET (hereinafter, referred to as a silicon-based MOSFET), and is not suitable for driving a SiC-based MOSFET (hereinafter, referred to as a SiC MOSFET). Compared with silicon-based MOSFETs, siC MOSFETs have the advantages of low on-resistance, low energy loss, high current density, high-frequency switching and the like. However, in practical use, since the SiC MOSFET is fast in switching speed and fast in voltage change speed, gate crosstalk is easily caused, and once the gate crosstalk voltage Δvgs exceeds the threshold voltage Vth of the SiC MOSFET, the SiC MOSFET is at risk of being turned on by mistake, and in this case, the SiC MOSFET is easily damaged.

Disclosure of Invention

In view of the shortcomings of the background technology, the invention provides a SiC MOSFET driving circuit, a control chip and a switching power supply, and aims to solve the technical problem that the existing SiC MOSFET is easy to damage due to the situation that the grid crosstalk is wrongly started when PWM control is performed.

In order to solve the technical problems, in a first aspect, the present invention provides the following technical solutions: a SiC MOSFET driving circuit comprises an upper switch unit, a lower switch unit, a negative voltage charge pump, a clamping unit, a level conversion unit and a signal processing unit;

the input end of the upper switch unit is used for inputting power supply voltage, the output end of the upper switch unit is electrically connected with the output end of the lower switch unit, and the input end of the lower switch unit is electrically connected with the negative pressure output end of the negative pressure charge pump;

the level conversion unit is electrically connected with the negative pressure output end of the negative pressure charge pump, negative pressure and power supply voltage output by the negative pressure charge pump are switched and output based on an input control signal, the voltage output end of the level conversion unit is electrically connected with the control end of the lower switch unit and the input end of the signal processing unit respectively, the signal processing unit is used for inverting the input signal, and the output end of the signal processing unit is electrically connected with the control ends of the clamping unit and the upper switch unit respectively.

In a certain implementation manner of the first aspect, the upper switch unit includes a triode Q1 and a triode Q2, where a collector of the triode Q1 is electrically connected with a collector of the triode Q2, and is an input end of the upper switch unit, a base of the triode Q1 is a control end of the upper switch unit, an emitter of the triode Q1 is electrically connected with a base of the triode Q2, and an emitter of the triode Q2 is an output end of the upper switch unit.

In a certain implementation manner of the first aspect, the lower switch unit includes a MOS transistor M1, a drain electrode of the MOS transistor M1 is an output end of the lower switch unit, a gate electrode of the MOS transistor M1 is a control end of the lower switch unit, and a source electrode of the MOS transistor M1 is an input end of the lower switch unit.

In a certain implementation manner of the first aspect, the clamping unit includes a clamping diode, and the voltage output end of the level conversion unit is electrically connected with a negative electrode of the clamping diode, and a positive electrode of the clamping diode is grounded.

In a certain implementation manner of the first aspect, the signal processing unit includes an inverter, an input terminal of the inverter is an input terminal of the signal processing unit, and an output terminal of the inverter is an output terminal of the signal processing unit.

In a certain implementation manner of the first aspect, the level conversion unit includes an inverter INV1, a MOS transistor P2, a MOS transistor N1, and a MOS transistor N2;

the source electrode of the MOS tube P1 is electrically connected with the source electrode of the MOS tube P2 and is used for being connected with a power supply, the grid electrode of the MOS tube P1 is electrically connected with the output end of the inverter INV1, and the input end of the inverter INV1 is used for inputting the control signal and is electrically connected with the grid electrode of the MOS tube P2; the drain electrode of the MOS tube P1 is respectively and electrically connected with the drain electrode of the MOS tube N1 and the grid electrode of the MOS tube N2, the drain electrode of the MOS tube P2 is a voltage output end of the level conversion unit and is respectively and electrically connected with the drain electrode of the MOS tube N2 and the grid electrode of the MOS tube N1, and the source electrode of the MOS tube N1 and the source electrode of the MOS tube N2 are electrically connected with the negative pressure output end of the negative pressure charge pump.

In a certain implementation manner of the first aspect, the negative-pressure charge pump includes a MOS transistor P3, a MOS transistor P4, a MOS transistor N3, and a MOS transistor N4;

the source electrode of the MOS tube P3 is used for accessing the working voltage, the drain electrode of the MOS tube P3 is electrically connected with the drain electrode of the MOS tube N3, the source electrode of the MOS tube N3 is used for grounding, the drain electrode of the MOS tube P4 is used for grounding, and the source electrode of the MOS tube P4 is electrically connected with the source electrode of the MOS tube N4;

the drain electrode of the MOS tube P3 and the source electrode of the MOS tube P4 are electrically connected with two ends of the capacitor C5; the source electrode of the MOS tube N3 and the drain electrode of the MOS tube N4 are electrically connected with two ends of the capacitor C6, and the source electrode of the MOS tube N3 is the negative pressure output end; the grid electrode of the MOS tube P3, the grid electrode of the MOS tube P4, the grid electrode of the MOS tube N3 and the grid electrode of the MOS tube N4 are respectively input with control clock signals.

In a second aspect, the invention provides a control chip, wherein the control chip is provided with the SiC MOSFET driving circuit, and the control chip is also provided with a VCC pin, an OUT pin, a VEE pin, a C+ pin, a C-pin and a GND pin;

the input end of the upper switch unit is electrically connected with the VCC pin, the output end of the upper switch unit is electrically connected with the OUT pin, the input end of the lower switch unit is electrically connected with the VEE pin, the drain electrode of the MOS tube P3 is electrically connected with the C+ pin, and the drain electrode of the MOS tube P4 is electrically connected with the C-pin.

In a certain implementation manner of the second aspect, the control chip is further provided with an LDO unit, an oscillator, a maximum duty ratio setting unit, a logic unit, an overcurrent protection unit, a PWM output unit, a ramp voltage generating unit, an RS trigger, a comparator, a resistor R1, a resistor R2, a resistor R3, a voltage drop unit, a resistor R4 and a MOS transistor M2;

the control chip is also provided with a VIN pin, a CS pin, a RT pin, a COMP pin and a FB pin;

the LDO unit is electrically connected with the VIN pin and generates a power supply voltage and a reference voltage based on an external voltage input by the VIN pin; the oscillator is electrically connected with the RT pin and is respectively used for providing clock signals for the slope voltage generating unit, the maximum duty ratio setting unit and the S end of the RS trigger, the voltage output end of the slope voltage generating unit is respectively electrically connected with the positive input end of the PWM output unit, the overcurrent protection unit and one end of the resistor R4, the other end of the resistor R4 is respectively electrically connected with the CS pin and the drain electrode of the MOS tube M2, and the source electrode of the MOS tube M2 is electrically connected with the GND pin; the negative input end of the PWM output unit is respectively and electrically connected with one end of a resistor R2 and one end of a resistor R3, the other end of the resistor R3 is grounded, the other end of the resistor R2 is electrically connected with the output end of the voltage drop unit, the input end of the voltage drop unit is respectively and electrically connected with one end of a resistor R1, a COMP pin and the output end of a comparator, the other end of the resistor R1 is used for inputting 5V voltage, the positive input end of the comparator is used for inputting 1.25V voltage, and the negative input end of the comparator is electrically connected with the FB pin; the maximum duty ratio setting unit, the output end of the PWM output unit and the output end of the overcurrent protection unit are electrically connected with the logic unit, the logic unit is electrically connected with the R end of the RS trigger, and the Q end of the RS trigger is used for inputting control signals to the level conversion unit.

In a third aspect, the invention provides a switching power supply, which comprises the control chip, and further comprises a capacitor C1, a capacitor C2, an inductor L1, a capacitor C3, a capacitor C4, a diode D1, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a capacitor C5, a capacitor C6 and a SiC MOSFET M3;

the VIN pin is respectively and electrically connected with one end of a capacitor C1 and one end of an inductor L1, the other end of the capacitor C1 is grounded, the other end of the inductor L1 is respectively and electrically connected with the anode of a diode D1 and the drain electrode of a SiC MOSFET tube M3, the grid electrode of the SiC MOSFET tube M3 is electrically connected with an OUT pin, the source electrode of the SiC MOSFET tube M3 is grounded through a resistor R6, the cathode of the diode D1 is respectively and electrically connected with one end of a capacitor C4 and one end of a resistor R7, the other end of the capacitor C4 is grounded, the other end of the resistor R7 is respectively and electrically connected with one end of a resistor R8, the FB pin and one end of a capacitor C2, the other end of the capacitor C2 is electrically connected with the COMP pin, and the other end of the resistor R8 is grounded; the RT pin is grounded through a resistor R5, the C+ pin is electrically connected with the C-pin through a capacitor C5, and the VEE pin is grounded through a capacitor C6.

Compared with the prior art, the invention has the following beneficial effects: when the high-level signal is required to be output in actual use, the voltage at the output end of the upper switch unit can be clamped to the target voltage through the clamping unit; when a low-level signal is required to be output, negative pressure is provided by the negative pressure charge pump, and the output end of the upper switch unit is set to be negative pressure by the level conversion unit and the signal processing unit, so that the SiC MOSFE is prevented from being opened by mistake due to grid crosstalk during the turn-off period.

Drawings

FIG. 1 is a circuit diagram of a SiC MOSFET drive circuit in an embodiment;

FIG. 2 is a circuit diagram of a negative voltage charge pump in an embodiment;

FIG. 3 is a circuit diagram of a level shift unit in an embodiment;

FIG. 4 is a block diagram of a control chip in an embodiment;

fig. 5 is a structural diagram of a switching power supply in the embodiment.

Detailed Description

The invention will now be described in further detail with reference to the accompanying drawings. The drawings are simplified schematic representations which merely illustrate the basic structure of the invention and therefore show only the structures which are relevant to the invention.

Example 1

As shown in fig. 1, a SiC MOSFET driving circuit includes an upper switching unit 1, a lower switching unit 2, a negative-pressure charge pump 5, a clamping unit 3, a level converting unit 4, and a signal processing unit 15;

the input end of the upper switch unit 1 is used for inputting power supply voltage, the output end of the upper switch unit 1 is electrically connected with the output end of the lower switch unit 2, and the input end of the lower switch unit 2 is electrically connected with the negative pressure output end of the negative pressure charge pump 5;

the level conversion unit 4 is electrically connected with a negative pressure output end of the negative pressure charge pump 5, the negative pressure and the power supply voltage output by the negative pressure charge pump 5 are switched and output based on an input control signal, the voltage output end of the level conversion unit 4 is respectively electrically connected with a control end of the lower switch unit 2 and an input end of the signal processing unit 15, the signal processing unit 15 is used for inverting the input signal, and the output end of the signal processing unit is respectively electrically connected with control ends of the clamping unit 3 and the upper switch unit 1.

In actual use, when a high-level signal needs to be output, the voltage at the output end of the upper switch unit 1 can be clamped to a target voltage through the clamping unit 3; when a low-level signal needs to be output, negative pressure is provided by the negative pressure charge pump 5, and the output end of the upper switch unit 1 is set to be negative pressure by the level conversion unit 4 and the signal processing unit 15, so that the SiC MOSFET is ensured not to be turned on by mistake due to gate crosstalk during the turn-off period.

Specifically, in this embodiment, the upper switch unit 1 includes a triode Q1 and a triode Q2, where the collector of the triode Q1 is electrically connected to the collector of the triode Q2, and is an input end of the upper switch unit 1, the base of the triode Q1 is a control end of the upper switch unit 1, the emitter of the triode Q1 is electrically connected to the base of the triode Q2, and the emitter of the triode Q2 is an output end of the upper switch unit 1;

the voltage clamping unit 3 further includes a voltage clamping diode Vz, and an output terminal of the signal processing unit 15 is electrically connected to a negative electrode of the voltage clamping diode Vz, and a positive electrode of the voltage clamping diode Vz is grounded.

In actual use, the triode Q1 and the triode Q2 form a Bipolar driving structure, and in order to enhance the driving capability of the circuit, the triode Q1 and the triode Q2 can adopt a Darlington structure; in addition, the base voltage of the triode Q1 can be clamped by the clamping diode Vz, and the breakdown voltage of the clamping diode Vz can be set to about 20V, so that the voltage of the output end of the upper switch unit 1 is about 20V when the upper switch unit is turned on, and the SiC MOSFET can be ensured to have smaller on-resistance when the SiC MOSFET is driven, and the system efficiency is improved.

Specifically, in this embodiment, the lower switch unit 2 includes a MOS transistor M1, a drain electrode of the MOS transistor M1 is an output end of the lower switch unit 2, a gate electrode of the MOS transistor M1 is a control end of the lower switch unit 2, and a source electrode of the MOS transistor M1 is an input end of the lower switch unit 2. In actual use, the MOS transistor M1 may be a DMOS transistor.

Specifically, in this embodiment, the signal processing unit 15 includes an inverter, an input end of the inverter is an input end of the signal processing unit 15, and an output end of the inverter is an output end of the signal processing unit 15.

Referring to fig. 2, in the present embodiment, the negative-pressure charge pump 5 includes a MOS transistor P3, a MOS transistor P4, a MOS transistor N3, and a MOS transistor N4;

the source electrode of the MOS tube P3 is used for being connected with a working voltage, wherein the working voltage is 5V, the drain electrode of the MOS tube P3 is electrically connected with the drain electrode of the MOS tube N3, the source electrode of the MOS tube N3 is used for being grounded, the drain electrode of the MOS tube P4 is used for being grounded, and the source electrode of the MOS tube P4 is electrically connected with the source electrode of the MOS tube N4;

the drain electrode of the MOS tube P3 and the source electrode of the MOS tube P4 are electrically connected with two ends of the capacitor C5; the source electrode of the MOS tube N3 and the drain electrode of the MOS tube N4 are electrically connected with two ends of the capacitor C6, and the source electrode of the MOS tube N3 is a negative pressure output end; the gate of the MOS transistor P3, the gate of the MOS transistor P4, the gate of the MOS transistor N3 and the gate of the MOS transistor N4 are respectively input with a control clock signal highfreg_clk, wherein the control clock signal highfreg_clk can be generated by a high-frequency oscillator.

When the control clock signal highfreg_clk is in a low level in actual use, the MOS transistor P3 and the MOS transistor P4 are turned on, the MOS transistor N3 and the MOS transistor N4 are turned off, and at the moment, the working voltage passes through the MOS transistor P3, the capacitor C5 and the MOS transistor P4 to the ground, so that the voltage at two ends of the capacitor C5 is 5V; when the control clock signal highfreg_clk is at a high level, the two MOS transistors N3 and N4 are turned on, the MOS transistor P3 and P4 are turned off, and the voltage at two ends of the capacitor can not be suddenly changed because the voltage at two ends of the capacitor can not be suddenly changed from the MOS transistor N3, the capacitor C5 and the MOS transistor N4 to the VEE terminal, and the capacitor C6 is arranged between the VEE and the GND for energy storage, so that the VEE voltage can be ensured to be stabilized at-5V.

Specifically, in the present embodiment, referring to fig. 3, the level conversion unit 4 includes an inverter INV1, a MOS transistor P2, a MOS transistor N1, and a MOS transistor N2;

the source electrode of the MOS tube P1 is electrically connected with the source electrode of the MOS tube P2 and is used for being connected with a power supply, the grid electrode of the MOS tube P1 is electrically connected with the output end of the inverter INV1, and the input end of the inverter INV1 is used for inputting a control signal IN and is electrically connected with the grid electrode of the MOS tube P2; the drain electrode of the MOS tube P1 is respectively and electrically connected with the drain electrode of the MOS tube N1 and the grid electrode of the MOS tube N2, the drain electrode of the MOS tube P2 is a voltage output end of the level conversion unit 4 and is respectively and electrically connected with the drain electrode of the MOS tube N2 and the grid electrode of the MOS tube N1, and the source electrode of the MOS tube N1 and the source electrode of the MOS tube N2 are electrically connected with a negative pressure output end of the negative pressure charge pump 5.

When the control core number IN is high, the MOS transistor P1 and the MOS transistor N2 are conducted, the MOS transistor P2 and the MOS transistor N1 are disconnected, and at the moment, the drain electrode of the MOS transistor P2 outputs a low-level signal (as VEE voltage); when the control signal IN is at a low level, the MOS transistor P1 and the MOS transistor N2 are turned off, and the MOS transistor P2 and the MOS transistor N1 are turned on, and at the moment, the drain electrode of the MOS transistor P2 outputs a high-level signal (VCC voltage), so that voltage switching control is realized, and when the SiC MOSFET to be controlled is turned off, the drain electrode of the MOS transistor P2 outputs a VEE voltage, so that the situation that the SiC MOSFET is not turned on by mistake due to grid crosstalk during the turn-off period can be avoided.

Example two

The embodiment provides a control chip, referring to fig. 4, a driving circuit of a SiC MOSFET in the first embodiment is provided on the control chip, and VCC pins, OUT pins, VEE pins, c+ pins, C-pins and GND pins are further provided on the control chip;

the input end of the upper switch unit 1 is electrically connected with the VCC pin, the output end of the upper switch unit 1 is electrically connected with the OUT pin, the input end of the lower switch unit 2 is electrically connected with the VEE pin, the drain electrode of the MOS tube P3 is electrically connected with the C+ pin, and the drain electrode of the MOS tube P4 is electrically connected with the C-pin.

In fig. 4, the control chip is further provided with an LDO unit 8, an oscillator 9, a maximum duty ratio setting unit 7, a logic unit 6, an overcurrent protection unit 12, a PWM output unit 11, a ramp voltage generating unit 10, an RS flip-flop, a comparator 14, a resistor R1, a resistor R2, a resistor R3, a voltage drop unit 13, a resistor R4, and a MOS transistor M2;

the control chip is also provided with a VIN pin, a CS pin, an RT pin, a COMP pin and a FB pin;

the LDO unit 8 is electrically connected with the VIN pin and generates a power supply voltage and a reference voltage based on an external voltage input by the VIN pin; the oscillator 9 is electrically connected with the RT pin and is respectively used for providing clock signals for the slope voltage generating unit 10, the maximum duty ratio setting unit 7 and the S end of the RS trigger, the voltage output end of the slope voltage generating unit 10 is respectively electrically connected with the positive input end of the PWM output unit 11, the overcurrent protection unit 12 and one end of the resistor R4, the other end of the resistor R4 is respectively electrically connected with the CS pin and the drain electrode of the MOS tube M2, and the source electrode of the MOS tube M2 is electrically connected with the GND pin; the negative input end of the PWM output unit 11 is respectively and electrically connected with one end of a resistor R2 and one end of a resistor R3, the other end of the resistor R3 is grounded, the other end of the resistor R2 is electrically connected with the output end of a voltage drop unit 13, the input end of the voltage drop unit 13 is respectively and electrically connected with one end of a resistor R1, a COMP pin and the output end of a comparator 14, the other end of the resistor R1 is used for inputting 5V voltage, the positive input end of the comparator 14 is used for inputting 1.25V voltage, and the negative input end of the comparator 14 is electrically connected with the FB pin; the maximum duty ratio setting unit 7, the output end of the PWM output unit 11 and the output end of the overcurrent protection unit 12 are electrically connected with the logic unit 6, the logic unit 6 is electrically connected with the R end of the RS flip-flop, and the Q end of the RS flip-flop is used for inputting a control signal to the level conversion unit 4.

Specifically, the reference voltages generated by the LDO unit 8 have a reference voltage of 5V, a reference voltage of 1.25V, and a reference voltage of 0.5V; the voltage drop unit 13 is configured to generate a fixed voltage drop for the input voltage, and the voltage drop of the exemplary voltage drop unit 13 is 1.4V.

In this embodiment, the control manner commonly used in the PWM feedback control field is performed through the LDO unit 8, the oscillator 9, the maximum duty ratio setting unit 7, the logic unit 6, the over-current protection unit 12, the PWM output unit 11, the ramp voltage generating unit 10, and the RS flip-flop, and the control principle and control procedure thereof are not discussed here.

The control chip in the embodiment integrates the driving circuit of the SiC MOSFET and the PWM control part circuit, so that the driving volume and cost of the SiC MOSFET can be reduced.

Example III

As shown in fig. 5, the embodiment provides a switching power supply, which includes the control chip, and further includes a capacitor C1, a capacitor C2, an inductor L1, a capacitor C3, a capacitor C4, a diode D1, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a capacitor C5, a capacitor C6, and a SiC MOSFET M3;

the VIN pin is respectively and electrically connected with one end of a capacitor C1 and one end of an inductor L1, the other end of the capacitor C1 is grounded, the other end of the inductor L1 is respectively and electrically connected with the anode of a diode D1 and the drain electrode of a SiC MOSFET tube M3, the grid electrode of the SiC MOSFET tube M3 is electrically connected with an OUT pin, the source electrode of the SiC MOSFET tube M3 is grounded through a resistor R6, the cathode of the diode D1 is respectively and electrically connected with one end of a capacitor C4 and one end of a resistor R7, the other end of the capacitor C4 is grounded, the other end of the resistor R7 is respectively and electrically connected with one end of a resistor R8, the FB pin and one end of a capacitor C2, the other end of the capacitor C2 is electrically connected with the COMP pin, and the other end of the resistor R8 is grounded; the RT pin is grounded through a resistor R5, the C+ pin is electrically connected with the C-pin through a capacitor C5, and the VEE pin is grounded through a capacitor C6.

The present invention has been made in view of the above-described circumstances, and it is an object of the present invention to provide a portable electronic device capable of performing various changes and modifications without departing from the scope of the technical spirit of the present invention. The technical scope of the present invention is not limited to the description, but must be determined according to the scope of claims.

Claims (10)

1. The SiC MOSFET driving circuit is characterized by comprising an upper switch unit, a lower switch unit, a negative voltage charge pump, a clamping unit, a level conversion unit and a signal processing unit;

the input end of the upper switch unit is used for inputting power supply voltage, the output end of the upper switch unit is electrically connected with the output end of the lower switch unit, and the input end of the lower switch unit is electrically connected with the negative pressure output end of the negative pressure charge pump;

the level conversion unit is electrically connected with the negative pressure output end of the negative pressure charge pump, negative pressure and power supply voltage output by the negative pressure charge pump are switched and output based on an input control signal, the voltage output end of the level conversion unit is electrically connected with the control end of the lower switch unit and the input end of the signal processing unit respectively, the signal processing unit is used for inverting the input signal, and the output end of the signal processing unit is electrically connected with the control ends of the clamping unit and the upper switch unit respectively.

2. The SiC MOSFET driving circuit of claim 1, wherein the upper switching unit includes a transistor Q1 and a transistor Q2, a collector of the transistor Q1 is electrically connected to a collector of the transistor Q2, and is an input terminal of the upper switching unit, a base of the transistor Q1 is a control terminal of the upper switching unit, an emitter of the transistor Q1 is electrically connected to a base of the transistor Q2, and an emitter of the transistor Q2 is an output terminal of the upper switching unit.

3. The SiC MOSFET driving circuit of claim 1, wherein the lower switching unit includes a MOS transistor M1, a drain of the MOS transistor M1 is an output terminal of the lower switching unit, a gate of the MOS transistor M1 is a control terminal of the lower switching unit, and a source of the MOS transistor M1 is an input terminal of the lower switching unit.

4. The SiC MOSFET driving circuit according to claim 1, wherein the clamping unit comprises a clamping diode, a voltage output terminal of the level conversion unit is electrically connected to a negative electrode of the clamping diode, and a positive electrode of the clamping diode is grounded.

5. The SiC MOSFET driving circuit of claim 1, wherein the signal processing unit includes an inverter, an input of the inverter being an input of the signal processing unit, and an output of the inverter being an output of the signal processing unit.

6. The SiC MOSFET driving circuit according to any one of claims 1 to 5, wherein the level shift unit includes an inverter INV1, a MOS transistor P2, a MOS transistor N1, and a MOS transistor N2;

the source electrode of the MOS tube P1 is electrically connected with the source electrode of the MOS tube P2 and is used for being connected with a power supply, the grid electrode of the MOS tube P1 is electrically connected with the output end of the inverter INV1, and the input end of the inverter INV1 is used for inputting the control signal and is electrically connected with the grid electrode of the MOS tube P2; the drain electrode of the MOS tube P1 is respectively and electrically connected with the drain electrode of the MOS tube N1 and the grid electrode of the MOS tube N2, the drain electrode of the MOS tube P2 is a voltage output end of the level conversion unit and is respectively and electrically connected with the drain electrode of the MOS tube N2 and the grid electrode of the MOS tube N1, and the source electrode of the MOS tube N1 and the source electrode of the MOS tube N2 are electrically connected with the negative pressure output end of the negative pressure charge pump.

7. The SiC MOSFET driving circuit of claim 6, wherein the negative-pressure charge pump comprises a MOS transistor P3, a MOS transistor P4, a MOS transistor N3, and a MOS transistor N4;

the source electrode of the MOS tube P3 is used for accessing the working voltage, the drain electrode of the MOS tube P3 is electrically connected with the drain electrode of the MOS tube N3, the source electrode of the MOS tube N3 is used for grounding, the drain electrode of the MOS tube P4 is used for grounding, and the source electrode of the MOS tube P4 is electrically connected with the source electrode of the MOS tube N4;

the drain electrode of the MOS tube P3 and the source electrode of the MOS tube P4 are electrically connected with two ends of the capacitor C5; the source electrode of the MOS tube N3 and the drain electrode of the MOS tube N4 are electrically connected with two ends of the capacitor C6, and the source electrode of the MOS tube N3 is the negative pressure output end; the grid electrode of the MOS tube P3, the grid electrode of the MOS tube P4, the grid electrode of the MOS tube N3 and the grid electrode of the MOS tube N4 are respectively input with control clock signals.

8. A control chip, characterized in that the control chip is provided with the SiC MOSFET driving circuit as claimed in claim 7, and the control chip is also provided with a VCC pin, an OUT pin, a VEE pin, a C+ pin, a C-pin and a GND pin;

the input end of the upper switch unit is electrically connected with the VCC pin, the output end of the upper switch unit is electrically connected with the OUT pin, the input end of the lower switch unit is electrically connected with the VEE pin, the drain electrode of the MOS tube P3 is electrically connected with the C+ pin, and the drain electrode of the MOS tube P4 is electrically connected with the C-pin.

9. The control chip according to claim 8, wherein the control chip is further provided with an LDO unit, an oscillator, a maximum duty ratio setting unit, a logic unit, an overcurrent protection unit, a PWM output unit, a ramp voltage generating unit, an RS trigger, a comparator, a resistor R1, a resistor R2, a resistor R3, a voltage drop unit, a resistor R4, and a MOS transistor M2;

the control chip is also provided with a VIN pin, a CS pin, a RT pin, a COMP pin and a FB pin;

the LDO unit is electrically connected with the VIN pin and generates a power supply voltage and a reference voltage based on an external voltage input by the VIN pin; the oscillator is electrically connected with the RT pin and is respectively used for providing clock signals for the slope voltage generating unit, the maximum duty ratio setting unit and the S end of the RS trigger, the voltage output end of the slope voltage generating unit is respectively electrically connected with the positive input end of the PWM output unit, the overcurrent protection unit and one end of the resistor R4, the other end of the resistor R4 is respectively electrically connected with the CS pin and the drain electrode of the MOS tube M2, and the source electrode of the MOS tube M2 is electrically connected with the GND pin; the negative input end of the PWM output unit is respectively and electrically connected with one end of a resistor R2 and one end of a resistor R3, the other end of the resistor R3 is grounded, the other end of the resistor R2 is electrically connected with the output end of the voltage drop unit, the input end of the voltage drop unit is respectively and electrically connected with one end of a resistor R1, a COMP pin and the output end of a comparator, the other end of the resistor R1 is used for inputting 5V voltage, the positive input end of the comparator is used for inputting 1.25V voltage, and the negative input end of the comparator is electrically connected with the FB pin; the maximum duty ratio setting unit, the output end of the PWM output unit and the output end of the overcurrent protection unit are electrically connected with the logic unit, the logic unit is electrically connected with the R end of the RS trigger, and the Q end of the RS trigger is used for inputting control signals to the level conversion unit.

10. A switching power supply, comprising the control chip of claim 9, further comprising a capacitor C1, a capacitor C2, an inductor L1, a capacitor C3, a capacitor C4, a diode D1, a resistor R5, a resistor R6, a resistor R7, a resistor R8, a capacitor C5, a capacitor C6, and a SiC MOSFET M3;

the VIN pin is respectively and electrically connected with one end of a capacitor C1 and one end of an inductor L1, the other end of the capacitor C1 is grounded, the other end of the inductor L1 is respectively and electrically connected with the anode of a diode D1 and the drain electrode of a SiC MOSFET tube M3, the grid electrode of the SiC MOSFET tube M3 is electrically connected with an OUT pin, the source electrode of the SiC MOSFET tube M3 is grounded through a resistor R6, the cathode of the diode D1 is respectively and electrically connected with one end of a capacitor C4 and one end of a resistor R7, the other end of the capacitor C4 is grounded, the other end of the resistor R7 is respectively and electrically connected with one end of a resistor R8, the FB pin and one end of a capacitor C2, the other end of the capacitor C2 is electrically connected with the COMP pin, and the other end of the resistor R8 is grounded; the RT pin is grounded through a resistor R5, the C+ pin is electrically connected with the C-pin through a capacitor C5, and the VEE pin is grounded through a capacitor C6.