CN117856584A

CN117856584A - DC-DC converter device and corresponding control method

Info

Publication number: CN117856584A
Application number: CN202311281238.1A
Authority: CN
Inventors: A·贝托里尼; A·加斯帕里尼; P·梅利洛; S·勒万蒂诺; M·吉奥尼
Original assignee: STMicroelectronics SRL
Current assignee: STMicroelectronics SRL
Priority date: 2022-10-06
Filing date: 2023-10-07
Publication date: 2024-04-09

Abstract

A boost DC-DC converter includes a switching network coupled to an inductor, controlled by a PWM drive signal. The control loop receives the voltage output and provides a PWM drive signal. The control loop generates an error signal based on a difference between the output voltage and a reference voltage, wherein the PWM drive signal is generated based on the error signal. A low pass filter circuit within the control loop receives the PWM drive signal and provides at least one filtered signal. The adder node of the control loop receives at least one filtered signal from the low pass filter circuit for addition with the at least one filtered signal. The PWM drive signal is generated from the sum of the filtered signal and the error signal.

Description

DC-DC converter device and corresponding control method

Priority claim

The present application claims the benefit of priority from italian patent application No. 102022000020607 filed at 10/6 of 2022, the contents of which are incorporated herein by reference in their entirety to the maximum extent allowed by law.

Technical Field

For example, the present description relates to Power Management Integrated Circuits (PMICs), such as DC-DC converter devices that include a time-based control loop.

One or more embodiments may be applied to, for example, an Organic Light Emitting Diode (OLED) display panel.

Background

Switching DC-DC converters are used in various electronic systems. For example, a DC-DC converter may be used to provide a supply voltage level to the AMOLED display unit, thereby converting the battery-powered voltage level to a regulated (positive) output voltage level.

For example, various types of electronic converters are conventionally used, such as "buck" or "boost" converters. These types of converters are well known to those skilled in the art, for example as demonstrated by the published application notes AN513/00393"Topologies for Switched Mode Power Supplies" (incorporated herein by reference) of the legal semiconductor in 1999 by l.wuidart.

DC-DC converters, such as boost converters, may be used in a variety of applications.

Conventional implementations of converter circuits (currently referred to as "time-based") include: a (voltage or current) controlled oscillator for performing integration in the phase domain; and a delay line providing a proportional/differential effect.

Depending on the application, to provide sufficient efficiency and performance levels, the time-based DC-DC converter circuit should desirably operate in different modes (e.g., continuous Conduction Mode (CCM), discontinuous Conduction Mode (DCM), asynchronous mode, synchronous mode, etc.) and be able to operate reliably in different scenarios.

In DC-DC converters using switching pairs or transistor networks driven by Pulse Width Modulation (PWM) signals, time-based methods use the occurrence of rising edges of binary signals as variables within the control loop. The advantage of this approach is that it occupies a lower area and consumes less power than the voltage-based approach. The performance gap between the two approaches increases further as the reference frequency of the converter increases.

Time-based methods take advantage of the natural technological shrink of CMOS processes, thereby using digital rather than analog signals within the control loop. Moreover, fully integrated DC-DC converters utilize lower filter inductance and capacitance values.

In order to maintain the same output voltage ripple, the reference frequency of the converter must be increased to several tens of MHz. While this variation does not introduce any problem in the time-based control loop size setting, it directly affects the voltage-based control loop as the error amplifier (e a) bandwidth increases (resulting in increased power consumption). For example, the effectiveness of this approach has been verified in the framework of high frequency CMOS buck converters.

Ideally, a time-based architecture could also be used in the control loop of the boost converter, achieving the same advantages. However, due to its non-minimum phase nature, the maximum achievable bandwidth of a boost converter is typically subject to 1/τ _z The limitation of the presence of the bottom Right Half Plane (RHP) zero, which is inherently present in the control of the output transfer function.

Representing the (transfer) function T of the control loop of a boost converter _{control-to-out} (s) can be written as:

wherein: τ _LHPz Is the left half plane zero point, corresponding to the zero point of the parasitic element of the capacitive element; τ _RHPz Is the right half plane zero point; v (V) _in An indication input voltage signal; d indicates the duty cycle; q-indicating filter qualityA quantity factor; and is also provided withIs the filter natural frequency.

The term τ at the molecule _RHPz Is the Right Half Plane (RHP) zero point 1/tau _z The value of which depends on the inductance L of the converter and the load R _load And a duty cycle D, as indicated below:

equation (2) also indicates that the time constant τ of such zero point _z The value of (2) becomes larger as the converter load increases. Such an additional term only exists when the converter is operating in PWM mode.

The maximum bandwidth of the system satisfies two inequalities, which can be expressed as:

BW _max ＜＜f _sw (3b)

wherein BW is _max Indicates the maximum achievable bandwidth, and f _sw Indicating the PWM switching frequency. In LED display applications, the required current capability is such that the first term is always limited with respect to the second term. Consider a standard PID compensation network with transfer function:

wherein τ _zl And τ _zh Time constant, τ, indicative of two zeros _p1 And τ _p2 Time constant indicating high frequency pole and K _PID Indicating PID DC gain. To meet the requirement in equation (3 a), the design of the PID network will involve the time constant τ of the zero point _zh And τ _zl Is a high value of (2).

To take full advantage of the time-based implementation, overcoming the bandwidth limitation introduced by the RHP zero in equation (3 a) has a certain correlation.

The presence of a Right Half Plane (RHP) zero in the transfer function of the open loop control to the output of the (e.g. non-minimum phase) DC-DC converter results in limiting the bandwidth of such devices.

For example, in known non-minimum phase converters, the bandwidth of the control system is kept below the RHP zero in order to keep the loop stable under each operating condition.

Discussion of literature lists for existing methods include, for example:

(1) SW Lee, published in the application report in 2014, "Practical feedback loop analysis for voltage-mode boost converter," discusses a type III compensator for designing a loop of a voltage mode boost converter operating in Continuous Conduction Mode (CCM), wherein the Right Half Plane (RHP) zero has additional constraints on the design of loop compensation and crossover frequency;

(2) "a novel tri-state boost converter with fast dynamics (a novel tri-state boost converter with fast dynamics)" published by viswanathan, r.oruganti, and d.srinivasan at page 677 through 683 of IEEE power electronics journal 17, 5, 2002 discusses the design of boost converters operating in continuous conduction mode, the problem of which is caused by dynamic shifting of the small signal control of the converter to the Right Half Plane (RHP) zero in the output transfer function;

(3) "Input/Output Current Ripple Cancellation and RHP Zero Elimination in a Boost Converter using an Integrated Magnetic Technique" published by y.gu, d.zhang, and z.zhao at 2015, IEEE power electronics journal 30, phase 2, pages 747 to 756 discusses a digital Current Mode Control (CMC) tuning method in an NIBB converter for fast voltage transition from buck mode to boost mode and return to Dynamic Voltage Scaling (DVS), LED driving, and envelope tracking;

(4) S-U.shin et al, "A95.2%efficiency dual-path DC-DC step-up converter with continuous output current delivery and low voltage ripple", published on IEEE International Solid State Circuit Conference (ISSCC) pages 430-432 in 2018.

(5) "Mitigation of Positive Zero Effect on Nonminimum Phase Boost DC-DC Converters in CCM", published on pages 4125-4134 of IEEE industrial electronic journal, volume 65, 5, v.v. paduvali, r.j.taylor, l.r.hunt, and p.t. balsar, 5, 2018, discusses control loop stability in boost converters operating in continuous conduction mode and a method of mitigating the effect of a zero on a control loop of a boost converter by shifting the location of the zero to the left half plane to thereby improve the stability of the control loop of the boost converter; and

(6) The "An 800-mA Time-Based Boost Converter in 0.18.18 μm BCD with RightHalf-Plane Zero Elimination and% Power Efficiency" published by leonii, a. Bertoli, a. Gaspani, s. Levantino and m. Ghion at pages 223-226 of escscirc 2021-IEEE 47 solid state conference on escscirc, et al, 2021, discusses a novel boost converter with Time-based control for LED display applications that eliminates CCM control to the right half-plane zero of the output transfer function to improve dynamic performance without the need for additional off-chip components or Power switches when inductor current is used.

Each of the foregoing documents is incorporated herein by reference.

The existing methods suffer from one or more of the following disadvantages: the area occupation is increased due to dedicated pads and external components, and the power consumption is higher due to the presence of additional components (load sensor, inductor current sensor).

Accordingly, there is a need in the art to make a contribution in one or more aspects of the advancement.

Disclosure of Invention

One or more embodiments include a converter device.

A boost DC-DC converter arrangement may be an example of such a converter arrangement.

One or more embodiments facilitate expanding loop bandwidth, such as increasing the speed of a control system.

For example, the controller may be reduced to a relatively simple Proportional Integral (PI) controller.

For example, eliminating the possibility of using additional sensors helps to reduce system complexity.

In one or more embodiments, the reduced system complexity helps to reduce area occupation and power/current consumption, resulting in better overall system efficiency.

Drawings

One or more embodiments will now be described, by way of non-limiting example only, with reference to the accompanying drawings, in which:

figure 1 is an exemplary diagram of a boost DC-DC converter,

Figure 1A is an example diagram of the temporal evolution of signals in the converter illustrated in figure 1,

figures 2 and 3 are exemplary diagrams of the basic principles of one or more embodiments,

figures 4A and 4B are bode diagrams indicating the basic principles of one or more embodiments,

figures 5 and 6 are exemplary diagrams of the basic principles of one or more embodiments,

figures 7 and 8 are exemplary diagrams of time-based DC-DC converter circuits according to the present disclosure,

figure 9 is an exemplary diagram of the basic principle of operating the time-based DC-DC converter circuit illustrated in figures 7 and 8,

figure 10 is an example plot of signal evolution over time in one or more embodiments,

figure 11 is an example diagram of a variant embodiment of a time-based DC-DC converter circuit according to the present disclosure,

figure 12 is an exemplary diagram of the basic principle of operating the time-based DC-DC converter circuit illustrated in figure 11,

fig. 13 is an example diagram of signal evolution over time in accordance with one or more embodiments of the present disclosure.

Detailed Description

In the following description, one or more specific details are set forth in order to provide a thorough understanding of examples of the described embodiments. These embodiments may be obtained without one or more of the specific details, or with other methods, components, materials, etc.

In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

References in the framework of the present description to "an embodiment" or "one embodiment" are intended to indicate that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, phrases such as "in an embodiment" or "in one embodiment" that may be present in one or more points of the present description do not necessarily refer to one and the same embodiment.

Furthermore, the particular structures, or characteristics may be combined in any suitable manner in one or more embodiments.

The references used herein are provided for convenience only and thus do not limit the scope of protection or the scope of the embodiments.

Corresponding numerals and symbols in the various drawings generally refer to corresponding parts, unless otherwise indicated.

The drawings are drawn to clearly illustrate the relevant aspects of the embodiments and are not necessarily drawn to scale.

The edges of features depicted in the drawings do not necessarily indicate the termination of the feature's range.

As illustrated in fig. 1, the boost converter 10 includes: power supply node V _IN Is configured to be coupled to a power supply V _IN To receive a supply voltage V therefrom _IN . Switching transistor S ₁ 、S ₂ Comprises a first switch S with a common switching node SW in between ₁ And a second switch S ₂ First switch S ₁ Includes a first control signal DRV configured to be received ₁ And has a first control node, a second switch S, which has a current path passing between the switching node SW and the ground GND ₂ Includes a receiver configured to receive a second control signal DRV ₂ And has a switching node SW and an output node V _OUT A second control node of the current path passing therethrough. Through a first switch S ₁ And a second switch S ₂ Is configured to respond to a corresponding first control signal DRV having a first value ₁ Second control signal DRV ₂ And is turned on in response to the corresponding first control signal DRV having the second value ₁ Second control signal DRV ₂ But not conductive. An inductive circuit element L (e.g. an inductor coil) is coupled to the half-bridge arrangement S ₁ 、S ₂ Is connected with the power supply node V of (1) _IN And a switching node SW. A capacitive element C (e.g. a capacitor with a corresponding capacitance C) referenced to ground GND is coupled to the output node V _OUT . Output node V _OUT Is configured to be coupled to an electrical load Z _L (e.g., resistors). The controller 12 is configured to provide a first S to the converter circuit 10 ₁ Switch and second S ₂ The switch provides a control signal DRV ₁ 、DRV ₂ 。

As illustrated in fig. 1A, in a continuous conduction mode of operation (CCM): at "on" time interval T _ON During which the inductor current i _L At the first switch S ₁ In which the flow is caused to pass through a first switch S ₁ Is turned on (i.e., the first switch S ₁ On), through a second switch S ₂ Is not conductive (i.e. while the second switch S ₂ Disconnection); and during the "off" time interval T _OFF During which the first switch S is passed through ₁ Is not conductive (i.e. the first switch S ₁ Open), through a second switch S ₂ Is turned on (i.e. second switch S ₂ On). At the off time interval T _OFF During which the inductor current i _L To capacitive element C and electrical load Z _L 。

In other words, in this configuration, energy is first stored in the inductive element L during the on-time interval and then transferred to the output load Z during the off-time interval _L 。

As illustrated in fig. 1A, the boost converter 10 is designed to pass the output current i _O To a given load Z _L Power is delivered, the output current i _O Is in the second switch S ₂ Flat of medium flowing currentMean value of<i _S2 >Is a function of (2).

When operating in CCM, e.g. in control signal DRV ₁ 、DRV ₂ During duty cycle variation of (a), average inductor current i _L Is limited by the available voltage. In the case of a control function (e.g., in the laplace plane), this corresponds to the presence of a Right Half Plane (RHP) zero, which introduces a 90 ° phase shift, limiting the maximum achievable control loop bandwidth.

As illustrated in fig. 2, the control circuit 20 (e.g., implemented in the controller 12) for controlling the operation of the boost converter 10 includes a feedback branch fb coupled to the output node V _OUT And is configured to receive a reference voltage V _REF Reference node V of (2) _REF (e.g. via being configured to be dependent on a reference voltage V _REF And output voltage V _OUT An adder 21 for generating an error signal epsilon from the difference between them). The control transfer function block 22 is coupled to the adder 21 to receive the error signal epsilon, wherein the control transfer function block 22 has a control transfer function H (S) and is configured to generate the control voltage V based on the error signal epsilon _C . The PWM controller 24 is coupled to the control transfer function block 22, wherein the PWM controller 24 is configured to switch S to the boost converter 10 ₁ 、S ₂ Providing a control signal DRV ₁ 、DRV ₂ . An output gain block 26 is coupled to the PWM controller 24, wherein the output gain block 26 has a gain function G _od (s). A filter block 27 (e.g. comprising a capacitor circuit element C coupled to _LPF Resistance circuit element R of (2) _LPF A passive RC filter of (a) is coupled to the control transfer function block 22 to receive the control voltage V _C And filtering is applied thereto. The filter block 27 has a filter transfer function FF(s). The load transfer function block 28 is configured to be dependent on the output current i _o The product of the electric load Z generates an output voltage V _OUT The load transfer function block 28 has a load transfer function Z ₀ (s). The power transfer function block 29 is configured to output a voltage V _OUT And supply voltage V _IN Providing a power transfer function G therebetween _ol (s) the power transfer function block 29 has a power transfer function G _ol (s). Second adder30 are coupled to the output gain block 26, the load transfer function block 28 and the power supply transfer function block 29, wherein the second adder 30 is configured to provide an output voltage V _OUT As a superposition of the signals received from these blocks 28, 29. A third adder 31 is coupled to the filter block 27 and to the output node V _OUT To provide it with a filtered control voltage V _C 。

The PWM signal V generated by the PWM circuit block 24 due to the presence of the filter circuit block 27 _PWM Transfer function G between error signal epsilon _do,FF (s) can be expressed as:

wherein: omega _0z Is the angular frequency of the zero dipole generated by, for example, the combination of paths including PWM circuit block 24, output gain block 26 and filter circuit block 27; the angular frequency may be a real or complex conjugate, depending for example on the gain and cut-off frequency of the filter circuit block; q (Q) _z Is the quality factor of the zero dipole; omega ₀ Is, for example, the angular frequency of the polar dipole of the reactive element L, C of the converter circuit 10; q is the quality factor of the LC filter in the converter 10; and omega _FF Is the cut-off frequency of the filter circuit block 27.

As illustrated in fig. 3, the elements of the control circuit 20 may be rearranged into an equivalent control circuit 20A, comprising a loop filter circuit block LF coupled to the first adder 31 to receive the error signal epsilon, wherein the loop filter circuit block LF comprises: a proportional-integral (PI) control circuit block 220 having a PI transfer function PI(s), the PI control circuit block 220 being configured to provide a control voltage V _C . The filter block 27 is coupled to the output of the PI transfer function PI(s) 220. The third adder 31 is coupled to the filter block 27, the integrator 220 and the first adder 21, wherein the third adder 31 is configured to add the filtered control voltage provided by the filter block 27 to the error signal epsilon.

As illustrated in fig. 3, a load transfer function block 28, a power supply transfer function block 29, an output gain block 26, and a second additionThe frenquency meter 30 is interposed between the PWM circuit block 24 and the output node V _OUT A part of the power stage block PS in between.

FIG. 4A is a graph showing the transfer function G as a function of frequency _do,FF (s) and transfer function G without filter circuit block 27 _do (s) a bode plot of the amplitude of(s).

FIG. 4B is a graph showing the transfer function G as a function of frequency _do,FF (s) and transfer function G without filter circuit block 27 _do A bode plot of the phase of(s).

Such as by transfer function G _do,FF (s)、G _do Visual comparison of the amplitude and phase of(s) shows that the presence of the filter circuit block 27 helps to compensate for the right hand plane (RHZ) zero because of the transfer function G _do,FF (s) has a transfer function G with respect to the absence of the filter circuit _do (s) decreasing with a reduced slope relative to the transfer function G without filter circuit _do (s) a trend of phase rise exceeding 90 degrees.

Due to the presence of the filter circuit block 27, the output voltage V _OUT Can be expressed as:

V _REF -V _C ·K _FF ＝V _OUT

wherein: k (K) _FF Is the gain introduced by the filter block 27 and V _C Is the control voltage.

Rearranging the terms in the above expression, reference voltage V _REF Can be expressed as:

wherein: d is the duty cycle, and G _PWM Is the gain of the PWM circuit block.

Thus, the output voltage V _OUT And reference voltage V _REF The relationship between these may depend on the offset factor D/G _PWM 。

For example, the duty cycle D may be estimated by an input/output voltage relationship, and may be expressed as:

Such a shift factor D/G _PWM The arrangement illustrated in fig. 5 may be used for further control.

As illustrated in fig. 5, the further improved control circuit 20B comprises an additional Offset calibration block (Offset) 50, which is coupled to the filter circuit 27 in the loop filter block LF, for example via a fourth adder 51, with respect to the control circuit 20A illustrated in fig. 3.

For example, the arrangement 20B illustrated in FIG. 5 facilitates removal of DC offset D/G without affecting the frequency response of the system _PWM 。

As illustrated in fig. 6, the offset calibration block 50 includes a multiplier stage 54, the multiplier stage 54 being coupled to a supply node V _IN To receive the power supply voltage V _IN Wherein the first multiplier stage 54 is configured to provide a supply voltage V _IN Multiplied by reference voltage V _REF Proportional to the reciprocal of (2), e.g. V _IN /V _REF . A pole circuit block 56 comprising a monopole (e.g. an integrator with a transfer function of 1/s) is coupled to the input of the filter block 27 and is configured to provide the product of the difference between the control and the (coarse) estimate multiplied by the pole of 1/s. The fifth adder 52 is coupled to the multiplier stage 54, to the pole circuit block 56 and is configured to perform a summation thereof and to provide it to the filter circuit block 27, e.g. via the fourth adder 51, for performing finer offset compensation.

As illustrated in fig. 6, the offset calibration block 50 calculates the ratio between the power supply voltage and the reference voltage (known voltage), and calculates the ratio from the control voltage V _C Subtracting this value.

As illustrated in fig. 6, due to non-idealities (i.e., efficiency) of the converter<1) The presence of pole circuit block 1/s counteracts the additional offset. Such an integration loop facilitates adjustment of the ratio V from which the supply voltage is subtracted to the reference voltage _IN /V _REF Is set to a level of (2). For example, this can be expressed as:

where η is the efficiency of the DC-DC converter 10.

For example, in the case where the integration path is slow enough (e.g., to satisfy expression G _int ＜＜BW _loop The condition of (2) that the difference retains frequency information without affecting the overall response of the system.

As illustrated in fig. 7, a time-based implementation of the controller includes: a time-based control function 22, known per se, is coupled to the output node V _OUT And reference node V _REF . The time-based control function 22 includes a first transconductance amplifier 220 and a second transconductance amplifier 221 configured to perform an output voltage V _OUT And reference voltage V _REF And thereby provides at least one error signal epsilon as a current signal. The time-based control function 22 further comprises Current Controlled Oscillators (CCO) 222, 224 providing integral control and Current Controlled Delay Lines (CCDL) 223, 225 implementing proportional control (in a manner known per se). A phase detector 24 coupled to the time-based control function 22 is configured to perform a comparison of the phases of the signals output by the CCDLs 223, 225 to generate a duty cycle signal V _PWM And is also configured to drive (e.g., gate) driver 120 to produce a signal for switching transistor S ₁ 、S ₂ Control signal DRV of (a) ₁ 、DRV ₂ . The filter block 27 is coupled to a time-based controller and a phase detector via an adder 31. Optionally, the offset calibration circuit block 50 is coupled to the filter circuit block 27 via an adder 31.

As illustrated in fig. 7, the output voltage V _OUT Is fed to a first transconductance block 220, the first transconductance block 220 also receiving a reference voltage V _REF And multiplying their difference by transconductance G _mP Outputting differential proportional current I on two corresponding feedback and reference output branches _P The two corresponding feedback and reference output branches are fed to a set of Current Controlled Delay Lines (CCDL) 223, 225 to generate a ratioGain. The output of the transconductance block 220 is differential across the two branches. The two differential branches are then fed as control signals for the two respective feedback current control delay lines 223 and reference current control delay lines 225 of the CCDL sets 223, 225.

As illustrated in fig. 7, the output voltage V _OUT Is fed to a second transconductance block 221, the second transconductance block 221 also receiving a reference voltage V _REF And multiplying their difference by transconductance G _mI Also outputting differential integrated current I on two corresponding feedback and reference output branches _I These two respective feedback and reference output branches are fed to a set of Current Controlled Oscillators (CCO) 222, 224 to generate an integral gain. The free running frequency of the Current Controlled Oscillators (CCO) 222, 224 sets the switching frequency f of the drive signal _sw The frequency value preferably corresponds to or depends on the frequency of the signal at the output of the Current Controlled Oscillator (CCO) 222, 224, in particular the switching frequency f _sw . Specifically, the switching frequency f _sw Corresponding to frequencies of CCOs 222 and 224 during start-up or steady state. The output of the transconductance block 221 is also differential across the two branches. The signals on the two differential branches are then fed as control signals for two respective feedback and reference current controlled oscillators 222 and 224 in the CCO sets 222, 224, which output the feedback frequencies ω, respectively _F Signal and reference frequency omega of (2) _R Is a signal of (a).

The outputs of the two current controlled oscillators 222 and 224 (i.e., the feedback frequency ω _F Signal and reference frequency omega of (2) _R Is fed to the inputs of the corresponding current controlled delay lines 223 and 225, respectively.

The outputs of the current controlled delay lines 223 and 225 are fed to a phase detector 24, which phase detector 24 supplies a PWM drive signal DRV via the driver 120 ₁ 、DRV ₂ . The phase detector 24 is configured to generate a voltage waveform V having a duty cycle _PWM The duty cycle is proportional to the phase difference between the two signals provided by CCDL 223, 225.

For example, the phase detector 24 may be implemented, for example, simply by having a pulse generation at its inputThe SR (set-reset) latch of the register. The pulse generator generates a narrow pulse on each positive edge transition of its input, resulting in SR flip-flop behavior of the phase detector 24. Pulse width modulation signal V _PWM Is set at a reference or control phase phi _R At each positive edge of (1), and at a feedback phase Φ _F Is reset at each positive edge of (c). Thus, the signal (e.g. V _PWM Waveform) is proportional to the phase difference between the two square waves.

As illustrated in fig. 7, the filter circuit block 27 includes an RC network R _LPF ，C _LPF Comprising a resistive element (e.g. resistor) R _LPF It is coupled to a capacitive element (e.g. capacitor) C _LPF The capacitor element C _LPF Referred to as a reference voltage, such as ground. The RC network is configured to apply low-pass filtering to the voltage provided by adder circuit 31, preferably at a frequency f much lower than (e.g., gate) driver 120 applying switching to switching transistor S ₁ 、S ₂ Is a switching frequency f of (2) _SW . A pair of transconductance amplifiers 270, 272 are coupled to the RC network R _LPF 、C _LPF To receive a filtered voltage signal therefrom. The pair of transconductance amplifiers 270, 272 are also coupled to the output nodes of the first transconductance amplifier 220 and the second transconductance amplifier 221 of the time-based control function 22, providing filtered current signals thereto.

As illustrated in fig. 7, the filter circuit block 27 provides a filtered value of the PWM output (in particular its duty cycle) to the proportional-integrator function of the time-based control function 22, injecting a steady-state current on CCO/CCDL proportional to the average value of the duty cycle square wave.

As illustrated in fig. 8, to preserve the frequency response of the loop, offset calibration circuitry 50 may be used to remove the offset prior to FF filter circuit block 27, which offset calibration circuitry 50 may include a power supply node V coupled to DC-DC converter 10 _IN Is connected to the first resistor branch R _IN And via switch S _A 、S _B Coupled to reference node V _REF Is connected to the second resistor branch R _REF . For example, it may be at reference node V _REF Reception (e.g. programmable) Reference voltage set point, and a second resistance branch R _REF Resistance R of (2) _REF Or may be programmable and have a value set by the same control logic that sets the reference voltage set point. It is noted that although shown in fig. 8 as covering a plurality of three resistive elements, the second resistive branch R _REF Theoretically any number of resistive elements can be included, e.g. based on a reference node V _REF A number of programmable values of the reference voltage set point received thereat. First resistor branch R _IN And a second resistor branch R _REF Is coupled at a common intermediate node P providing an indication of the supply voltage V _IN And reference voltage V _REF Is a ratio of the voltage of the ratio (a). Transconductance amplifier 500 has a first (e.g., inverting) input node coupled to a common intermediate node P to receive a voltage ratio, coupled to a reference ground C _INT A second (e.g., non-inverting) input node of the capacitive element and an output node configured to provide a current at its first input node proportional to the voltage ratio. A second input node of the transconductance amplifier 500 is coupled to a filter circuit block 27 and a coupling circuit block (known per se) comprising a phase frequency detector and a charge pump (abbreviated PFDCP). An offset calibration current controlled delay line (OC-CCDL) 502 is coupled to the output node of the transconductance amplifier 500.

Delay lines with programmable delay as a function of voltage or current signals are well known in the art. For example, in this context, reference may be made to U.S. patent nos. 5,650,739A or 7,696,799B2 (both of which are incorporated herein by reference).

As illustrated in fig. 8, the offset correction circuit 50 is configured to remove steady state offset (e.g., D/G) by driving OC-CCDL 502 _PWM ) So that its delay is aligned with the transconductance G of the transconductance amplifier 500 of the offset calibration circuit block 50 _mD In proportion to the capacitor C, the offset calibration circuit block 50 generates _int The value of the sum and the input voltage of the converter (in terms of a ratio of to V _in /V _ref Scaled by a proportional factor) the difference between the currents. For example, such a current indicates an ideal value of the duty cycle, as it can be expressed as：

Wherein:is duty cycle d=1-V _IN /V _REF The voltage across the capacitive element Cint with reference to ground.

As illustrated in fig. 8, the transconductance G of transconductance amplifier 500 is tuned _mD And the gain of OC-CCDL line 502, the output signal τ of OC-CCDL line 502 _OC The output of the CCDL 225 delayed by the estimated DC value of the duty cycle may be indicated. For example, this can be expressed as:

as illustrated in fig. 8, the output of OC-CCDL 500 is provided to a Coupling Circuit (CC) block 25, which CC block 25 provides a signal indicative of the "actual" duty cycle from the regulation loop and an estimated τ _OC The difference between them. For example, the PFD of the coupling circuit 25 is configured to act on the charge pump of the coupling circuit 25 to drive it to inject current into the feedforward filter 27 and the capacitive element C of the offset calibration circuit block 50 _int 。

As shown in fig. 9 and 10, in response to a change in the effective duty cycle (e.g., a slow change in BW < f from cycle to cycle _SW ) Estimated value τ of OC delay line 502 _OC But also by intervention of fast feed forward.

For example, based on the effective duty cycle D and the estimated one τ _OC The offset may be removed from the difference between (detected via coupling circuitry 25).

For example, may be present at the output voltage V _OUT Is slowly cancelled by the intervention of the loop OCP that adjusts the positive input voltage of the transconductance amplifier 500 to provide a current that sets OC-CCDL 502 to match the effective duty cycle D.

The solutions illustrated in fig. 8 to 10 help to remove additional disturbances that may be injected in the loop.

FIG. 10 is an example timing diagram of behavior of signals over time in one or more embodiments.

As illustrated in fig. 10, the error epsilon decreases over time due to the loop OCP operation discussed above.

As illustrated in fig. 11, in an alternative offset compensation circuit 50A, OC-CCDL 502 may be replaced by an arrangement of transistors and current generators, as discussed above.

As illustrated in fig. 11, the variable offset correction circuit 50A includes a first current generator 510 coupled to a first switch (e.g., MOSFET) M10 via a first chopper switch Sc configured to provide a PWM signal V via the phase detector 24 _PWM Driven to conduct or not conduct. The second current generator 511 via a second chopper switch S _D Is coupled to a second switch (e.g. MOSFET) M11, the second chopper switch S _D PWM signal V configured to be provided via phase detector 24 _PWM The node in between the second switch M11 and the second chopper switch Sd is coupled to the filter circuit block 27, driven to be conductive or nonconductive. The third switch M12 is coupled to the output of the transconductance amplifier 500 and the second switch M11.

As illustrated in fig. 11, the arrangement of the switches Sc, sd and the respective current generators 510, 511 may be referred to as a "current chopper" because of the reference current I provided by these generators _ref Through switch S _C 、S _D Is "chopped" by alternating opening and closing of (a) such that the average current I injected _ave Can be expressed as

I _ave ＝D _eff ·I _REF

Wherein: d (D) _eff Is a PWM signal V driving a DC-DC converter _PWM An effective duty cycle of (e.g., also considering circuit efficiency), and I _REF Is the reference current provided by the current generators 510, 511.

Chopper, as will be appreciated by those skilled in the artA circuit is an electronic switching circuit that directly converts a "fixed" DC input to a variable DC output voltage. In other words, the chopper is an electronic switch (e.g. Sc, sd) which is used in the presence of another signal (e.g. PWM signal V _PWM ) Under control of a signal (e.g. current I supplied by current generators 510, 511) _REF )。

As illustrated in fig. 11 and 12, to the ratio of the power supply voltage and the reference voltage (e.g., V _in /V _REF ) The scaled input voltage drives the transconductance amplifier 500 whose output current is mirrored and subtracted via the current choppers 511, M11. For example, the mirror current is a continuous current, which can be expressed as:

as illustrated in fig. 11 and 12, since the estimated duty cycle does not take into account the converter efficiency, the RC network R in the filter block 27 _LPF 、C _LPF Upper injection of residual average current I _ave Resulting in regulation of the output voltage V _OUT Residual offset on the substrate.

As illustrated in fig. 11 and 12, the residual offset may be cancelled due to the intervention of the integrating loop OCP, thereby adjusting the positive input of the transconductance amplifier 500 until the average current Iave across the injection capacitive element Cint reaches zero.

For example, to obtain sufficient cancellation of the residual offset, the current choppers 511, sd and 512, sc may have the same gain.

For example, during transients, when the effective duty cycle is slowly changing from cycle to cycle, the estimated value of the mirror current is determined by the voltage from the supply voltage V _in Is changed (e.g., instantaneously) by intervention of the fast feed-forward FFP.

For example, one or more embodiments facilitate preserving frequency information in a difference between an effective duty cycle and an estimated duty cycle while removing an offset.

As illustrated in fig. 12 and 13, generator I _REF The reference current provided and the effective duty up provided by the main loopSpace ratio D _eff The product of (a) produces a waveform with a varying average value (e.g., square).

As illustrated in fig. 12 and 13, the output current I generated by the transconductance amplifier 500 _OTA And estimated duty cycle D _EST The product of (2) indicates the correction provided by the integrating loop to correct the offset.

As illustrated in fig. 12 and 13, the error signal epsilon may be expressed as the difference of the above signals, for example:

ε＝(D _EFF I-D _EST I)

for example, under static conditions, the error signal ε= (D _EFF I-D _EST I) Is a square wave with an average value of zero.

As illustrated herein, a boost DC-DC converter device operating in PWM mode includes a DC-DC boost converter architecture including a boost inductor L, an output capacitor C, and a switching network S ₁ 、S ₂ Boost inductor L and supply voltage generator V for supplying a supply voltage to said boost inductor _IN Arranged in series, an output capacitor C and an output load Z _L Coupled in parallel to output node V _OUT In the switching network S ₁ 、S ₂ Is configured to drive the signal V at PWM _PWM Selectively coupling the output of the boost inductor to the output node under control of (a). The boost DC-DC converter device includes: a control loop 22, 24, 26 coupled to the voltage output and providing the PWM drive signal at its output, the control loop being configured to respond to the output voltage and a reference voltage V _REF The difference therebetween generates an error signal epsilon and is configured to provide the PWM drive signal based on the error signal; and a low pass filter circuit block 27 coupled to the control loop to receive the PWM signal therefrom, the low pass filter circuit block 27 configured to apply low pass filtering to the PWM signal to thereby provide at least one filtered signal to the control loop. The control loop comprises at least one adder node 51, 31 configured to receive at least one filtered signal from the low pass filter circuit block and to add the filtered signal to the error signal, said PWM being provided according to the sum of the filtered signal and the error signalA driving signal.

As illustrated herein, the control loop comprises a time-based control loop that includes integral control branches 221, 222, 224 and proportional branches 220, 223, 225. The integrating control branches 221, 222, 224 are configured to convert the error signal into an integrating control current signal I _i Which is used to obtain the control signal of at least one current-controlled oscillator 222, 224, supplying the switching frequency f of the PWM drive signal _sw Depending on (in particular corresponding to) the first signal, the integrated control current signal is dependent on the first phase Φ _R And (3) operating. The proportional branches 220, 223, 225 are configured to convert the error signal into a proportional control current signal I _p It is used to obtain a control signal of at least one delay line 223, 225, receiving at its input said first signal operating with a first phase configured to be dependent on said proportional control current signal at said first signal Φ _R 、Φ _F In order to sum the second phases to obtain at least one time signal phi _R 、Φ _F . At least one time signal is supplied to a phase detector 24, the phase detector 24 being configured to output a switching voltage V _PWM The switching voltage V _PWM The duty cycle D of at least one time signal, which in turn is supplied to a driver circuit to control the generation of a driving PWM signal driving the switching network of the DC-DC boost converter architecture.

As illustrated herein, the low-pass filter circuit block 27 includes: RC network R _LPF 、C _LPF Configured to apply a low pass filter to the PWM signal; and at least one transconductance amplifier 270, 272 configured to apply transconductance amplification to the filtered PWM signal to provide at least one filtered current signal to the time-based control loop. The at least one adder node of the control loop is configured to add the at least one filtered current signal with the integrated control current signal and the proportional control current signal. The sum of the at least one filtered current signal and the proportional control current signal is used to obtain the control signal for the at least one delay line 223, 225. At least one filtered electricity The sum of the flow signal and the integrated control current signal is used to obtain the control signal for at least one current controlled oscillator 222, 224.

As illustrated herein, the boost DC-DC converter includes an offset compensation circuit block 50 coupled to a low pass filter circuit block; 50A configured to apply an offset compensation process to the PWM signal, providing an offset compensated PWM signal to the low pass filter circuit block.

As illustrated herein, the offset compensation circuit block includes: a first resistive branch R coupled to a supply voltage _IN The method comprises the steps of carrying out a first treatment on the surface of the Via a switch set S _A 、S _B A second resistive branch R coupled to the setpoint reference node _REF The setpoint reference node is configured to receive a setpoint reference voltage V _REF . The first and second resistive branches are coupled at a common intermediate node P that provides a voltage indicative of a voltage ratio of the supply voltage and the reference voltage. Transconductance amplifier 500 has a first input node coupled to a common intermediate node to receive a voltage ratio, a capacitive element C coupled to a reference ground _INT And an output node configured to provide a current proportional to the voltage ratio at its first input node, wherein the second input node of the transconductance amplifier is coupled to a filter circuit block and a coupling circuit block comprising a phase frequency detector and a charge pump PFDCP circuit block 25. An offset calibration current control delay line OC-CCDL 502 is coupled to the output node of the transconductance amplifier.

As illustrated herein, the offset compensation circuit block 50A includes: a first current generator 510, via a first chopper switch S _C Coupled to the first switch M10, configured to be driven to be conductive or non-conductive via the PWM signal provided by the phase detector; and a second current generator 511 via a second chopper switch S _D Is coupled to a second switch M11, a second chopper switch S _D A PWM signal configured to be provided via a phase detector (24) is driven to be conductive or non-conductive. The third switch M12 is coupled to the output of the transconductance amplifier and to the second switch. First 510 current generatorThe second 511 current generator is configured to provide a reference current I _REF Wherein the second switch and the second chopper switch have a common intermediate node coupled to the filter circuit block.

As exemplified herein: the low-pass filter circuit block has a cut-off angular frequency omega _FF And the PWM driving signal is based on the output voltage V _OUT With reference voltage V _REF Transfer function G between error signals resulting from the difference between them _do,FF (s) is expressed as:

wherein: omega _0z Is the angular frequency of the zero dipole generated by the combination of the two paths Gdo(s) and FF(s); q (Q) _z Is the quality factor of the zero dipole; omega ₀ Is the angular frequency of the pole dipole of the LC filter of the boost DC-DC converter device; q is the quality factor of the polar dipole of the LC filter of the boost DC-DC converter device; and omega _FF Is the angular frequency of the filter circuit block (27).

It is to be understood that the various individual implementation options illustrated throughout the drawings of the present description are not necessarily intended to be employed in the same combination illustrated in the drawings. Thus, one or more embodiments may employ these (otherwise non-mandatory) options individually and/or in different combinations relative to the combinations illustrated in the figures.

The claims are an integral part of the technical teaching provided herein with reference to the examples.

Without prejudice to the underlying principles, the details and the embodiments may vary, even significantly, with respect to what has been described by way of example only, without departing from the scope of the protection. The protection scope is defined by the attached claims.

Claims

1. A boost DC-DC converter device comprising:

a boost inductor arranged in series with a supply voltage generator that provides a supply voltage to the boost inductor;

an output capacitor coupled to the output node in parallel with the output load;

a switching network configured to selectively couple an output of the boost inductor to the output node under control of a PWM drive signal;

A control loop having an input and an output, the input of the control loop coupled to receive an output voltage, the output of the control loop providing the PWM drive signal, the control loop configured to generate an error signal from a difference between the output voltage and a reference voltage, and to generate the PWM drive signal based on the error signal;

a low pass filter circuit coupled to the control loop and configured to receive the PWM drive signal, the low pass filter circuit configured to apply low pass filtering to the PWM drive signal and generate at least one filtered signal;

wherein the control loop comprises at least one adder node configured to receive the at least one filtered signal from the low pass filter circuit and to add the filtered signal to the error signal;

wherein the PWM drive signal is generated from a signal output from the at least one adder node.

2. The boost DC-DC converter device of claim 1, wherein the control loop is a time-based control loop comprising:

An integration control branch configured to convert the error signal into an integration control current signal from which a control signal is generated to control at least one current controlled oscillator to supply a first signal from which a switching frequency of the PWM drive signal depends, the first signal having a first phase that depends on the integration control current signal; and

a proportional branch configured to convert the error signal to a proportional control current signal, a control signal generated from the proportional control current signal to control at least one delay line configured to delay the first signal by a second phase to generate at least one time signal, the second phase being dependent on the proportional control current signal;

a phase detector configured to receive the at least one time signal and output a switching voltage having a duty cycle that is a function of the phase of the at least one time signal; and

a driver circuit configured to receive the switching voltage and control generation of the PWM drive signal.

3. The boost DC-DC converter device of claim 2, wherein the low pass filter circuit comprises:

An RC network configured to apply low pass filtering to the PWM drive signal; and

at least one transconductance amplifier configured to apply transconductance amplification to the low-pass filtered PWM drive signal to generate at least one filtered current signal reaching the time-based control loop;

wherein the at least one adder node of the time-based control loop is configured to add the at least one filtered current signal to the integrated control current signal and to the proportional control current signal;

wherein the sum of the at least one filtered current signal and the proportional control current signal is used to obtain the control signal for at least one delay line; and is also provided with

Wherein the sum of the at least one filtered current signal and the integrated control current signal is used to obtain the control signal of at least one current controlled oscillator.

4. The boost DC-DC converter device of claim 1, further comprising an offset compensation circuit coupled to the low pass filter circuit, the offset compensation circuit configured to apply an offset compensation process to the PWM signal to provide an offset compensated PWM signal to the low pass filter circuit.

5. The boost DC-DC converter device of claim 4, wherein the offset compensation circuit comprises:

a first resistive branch coupled to the supply voltage;

a second resistive branch coupled to a set point reference node via a set of switches, the set point reference node configured to receive a set point reference voltage;

wherein the first and second resistive branches are coupled at a common intermediate node to provide a voltage indicative of a voltage ratio of the supply voltage to the reference voltage;

a transconductance amplifier having a first input node coupled to the common intermediate node to receive the voltage ratio, a second input node coupled to a capacitive element that is referenced to ground, and an output node configured to provide a current at the first input node that is proportional to the voltage ratio, wherein the second input node of the transconductance amplifier is coupled to the filter circuit and a coupling circuit that includes a phase frequency detector and a charge pump circuit; and

an offset calibration current controlled delay line is coupled to the output node of the transconductance amplifier.

6. The boost DC-DC converter device of claim 4, wherein the offset compensation circuit comprises:

a first current generator coupled to a first switch via a first chopper switch, the first chopper switch being driven to be conductive or non-conductive via the PWM signal provided by the phase detector;

a second current generator coupled to a second switch via a second chopper switch, the second chopper switch being driven to be conductive or non-conductive via the PWM signal provided by the phase detector;

a third switch coupled to the output of the transconductance amplifier and the second switch;

wherein the first current generator and the second current generator are configured to provide a reference current; and is also provided with

Wherein the second switch and the second chopper switch have a common intermediate node coupled to the filter circuit.

7. The boost DC-DC converter device of claim 1, wherein:

the low pass filter circuit has a cut-off angular frequency omega _FF The method comprises the steps of carrying out a first treatment on the surface of the And is also provided with

A transfer function G between the PWM drive signal and the error signal generated from the difference between the output voltage and the reference voltage _do,FF (s) is expressed as:

wherein: omega _0z Is the angular frequency of the zero dipole generated by the combination of the two paths Gdo(s) and FF(s); q (Q) _z Is a quality factor of the zero dipole; omega ₀ Is the angular frequency of the polar dipole of the LC filter of the boost DC-DC converter device; q is a quality factor of the pole dipole of the LC filter of the boost DC-DC converter device; and omega _FF Is the angular frequency of the filter circuit.

8. A boost DC-DC converter device comprising:

a switching network configured to selectively couple the output of the boost inductor to the output node under control of a PWM drive signal;

a control loop having an input and an output, the input of the control loop coupled to a voltage output, the output of the control loop providing the PWM drive signal;

the control loop includes:

a first adder circuit configured to generate an error signal from a difference between the output voltage and a reference voltage;

A second adder circuit configured to generate a first signal from a sum of the error signal and a second signal;

a proportional-integral circuit having an input and an output, the input of the proportional-integral circuit configured to receive the first signal, the output of the proportional-integral circuit configured to generate a PWM control voltage signal;

a low pass filter circuit configured to filter the PWM control voltage signal and generate the second signal; and

a PWM circuit having an input and an output, the input of the PWM circuit configured to receive the PWM control voltage signal, the output of the PWM circuit configured to generate the PWM drive signal.

9. The boost DC-DC converter device of claim 8, wherein the control loop further comprises a third adder circuit configured to add an offset to the PWM control voltage signal for input to the low pass filter circuit.

10. The boost DC-DC converter device of claim 9, further comprising an offset compensation circuit configured to generate the offset, the offset compensation circuit comprising:

a first resistive branch coupled to a supply voltage;

a transconductance amplifier having a first input node coupled to the common intermediate node to receive the voltage ratio, a second input node coupled to a capacitive element that is referenced to ground, and an output node configured to provide a current at the first input node of the transconductance amplifier that is proportional to the voltage ratio, wherein the second input node of the transconductance amplifier is coupled to the filter circuit and a coupling circuit that includes a phase frequency detector and a charge pump circuit; and

11. The boost DC-DC converter device of claim 9, further comprising an offset compensation circuit configured to generate the offset, the offset compensation circuit comprising:

A first current generator coupled to a first switch via a first chopper switch, the first chopper switch configured to be driven to be conductive or non-conductive via the PWM drive signal;

a second current generator coupled to a second switch via a second chopper switch, the second chopper switch configured to be driven to be conductive or non-conductive via the PWM drive signal;

12. The boost DC-DC converter device of claim 8, wherein the control loop further comprises:

a third adder circuit configured to add a third signal to the PWM control voltage signal to input to the low-pass filter circuit;

a fourth adder circuit configured to add a fourth signal and a fifth signal to generate the third signal;

a pole blocking circuit having an input coupled to the output of the third adder circuit and configured to generate the fourth signal; and

A multiplier circuit configured to scale a supply voltage to generate the fifth signal.

13. The boost DC-DC converter device of claim 12, wherein the pole blocking circuit is an integrator circuit.

14. The boost DC-DC converter device of claim 8, wherein the proportional-integral circuit comprises:

an integration control branch configured to convert the first signal into an integration control current signal from which a control signal is generated to control at least one current controlled oscillator to supply a first oscillation signal, the switching frequency of the PWM drive signal being dependent on the first oscillation signal, the first oscillation signal having a first phase, the first phase being dependent on the integration control current signal; and

a proportional branch configured to convert the first signal into a proportional control current signal, a control signal being generated from the proportional control current signal to control at least one delay line configured to delay the first oscillating signal by a second phase to generate at least one time signal, the second phase being dependent on the proportional control current signal.

15. The boost DC-DC converter device of claim 14, wherein the PWM circuit comprises:

16. The boost DC-DC converter device of claim 8, wherein the low pass filter circuit comprises:

an RC network configured to apply low pass filtering to the PWM control voltage signal; and

at least one transconductance amplifier configured to apply transconductance amplification to the low-pass filtered PWM control voltage signal to generate the second signal.