WO2014204408A1

WO2014204408A1 - Method and network for providing fixed frequency for dc-dc hysteretic control buck converter

Info

Publication number: WO2014204408A1
Application number: PCT/SG2014/000294
Authority: WO
Inventors: Zhuochao SUN; Liter Siek; Ravinder Pal Singh; Minkyu Je
Original assignee: Agency For Science, Technology And Research; Nanyang Technological University
Priority date: 2013-06-21
Filing date: 2014-06-20
Publication date: 2014-12-24

Abstract

A method, circuits and networks have been provided for improved stable dynamic voltage regulation. The circuits include a tunable hysteretic window module, a buck converter and a voltage regulation module. The tunable hysteretic window module, the buck converter and the voltage regulation module are coupled such that a fixed switching frequency can be achieved. The tunable hysteretic window module includes a tuning module and a hysteretic window comparator module and a feedback network is formed connecting the voltage regulation module and the hysteretic window comparator module to achieve improved voltage regulation.

Description

METHOD AND NETWORK FOR PROVIDING FIXED FREQUENCY FOR DC-DC HYSTERETIC CONTROL BUCK CONVERTER

PRIORITY CLAIM

[0001] The present application claims priority of Singapore Patent Application No. 201304873-1 , filed on 21 June 2013.

TECHNICAL FIELD

[0002] The present invention relates to a method and network configuration for providing fixed frequency for hysteretic controlled voltage regulator modules, more specifically, for current mode DC-DC hysteretic control buck converters.

BACKGROUND

[0003] Voltage regulator modules (VRMs) for modern high performance microprocessors are expected to be capable of providing a large output current (approaching 150A) with a fast current transient (up to 50A/ps) while performing dynamic voltage scaling (DVS). When the dynamic range (for both current and voltage) increases, the VRM design becomes more challenging as it requires a high speed controller to maintain or shorten the transient time. Otherwise, extra output capacitors are needed, which increase the cost and the size of the motherboard of an electronic device.

[0004] For stability reasons, a VRM operated according to a linear control theory (e.g., pulse width modulation (PWM)) normally has to limit its bandwidth to 20%~30% of the switching frequency. Thus, for VRMs targeting fast responding speeds, an extremely high switching frequency is required. However, although an extremely high switching frequency will help to reduce inductor and capacitor sizes, it results in low efficiency due to associated extra switching loss.

[0005] However, if a VRM operates in accordance with a nonlinear control method (e.g. hysteretic control), the transient response is no longer limited by its switching frequency. Instead of responding to a load transient after a few switching cycles in a PWM controlled VRM, the hysteretic controlled VRM can achieve a nearly instantaneous response. Therefore, the switching frequency can be reduced while maintaining a fast transient speed. However, conventional hysteretic controlled VRMs do not operate at a fixed frequency, which introduces potential electro-magnetic interference (EMI) failure for noise-sensitive systems (e.g., RF transceivers) and phase interleaving difficulties for high current multiphase designs. Therefore, a fixed-frequency hysteretic control becomes more attractive.

[0006] Thus, what is needed is a robust method and networks that overcome the drawbacks of conventional ones and enable provision of fixed frequency hysteretic controlled VRMs for, for example, DC-DC hysteretic control buck converters.

SUMMARY

[0007] According to a first aspect of the present invention, there is provided a method for providing a fixed switching frequency for a hysteretic buck converter. The method includes using a tunable hysteretic window module to fix the fixed switching frequency

[0008] According to a second aspect of the present invention, there is provided a current mode hysteretic buck converter. The current mode hysteretic buck converter includes a tunable hysteretic window module, a buck converter and a voltage regulation module. The tunable hysteretic window module, the buck converter and the voltage regulation module are coupled such that fixed switching frequency can be achieved.

BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The accompanying figures, where like reference numerals refer to identical or functionally similar elements throughout the separate views and which together with the detailed description below are incorporated in and form part of the specification, serve to illustrate various embodiments and to explain various principles and advantages in accordance with a present embodiment.

[0010] Fig.lA depicts a conventional voltage-mode hysteretic control (VMHC) structure hysteretic buck converter. Fig.l B depicts a conventional current-mode hysteretic control (CMHC) structure hysteretic buck converter.

[0011] Fig. 2 depicts a first known frequency-locking technique, i.e. a fixed-frequency hysteretic buck converter with adaptive-on/off-time.

[0012] Fig. 3 illustrates waveforms of the first known frequency-locking technique working in a continuous-conduction mode (CCM) with adaptive-on/off-time.

[0013] Fig. 4 illustrates waveforms of the first known frequency-locking technique working in a discontinuous-conduction mode (DCM) with adaptive-on-time.

[0014] Fig. 5 depicts a second known frequency-locking technique, i.e. a fixed-frequency hysteretic buck converter with an adjustable delay.

[0015] Fig. 6 illustrates voltage waveforms of the hysteretic comparator of the second known frequency-locking technique with an adjustable delay of Fig. 5. [0016] Fig. 7A depicts a third known frequency-locking technique, i.e. a fixed-frequency hysteretic buck converter with an adjustable hysteretic window. Fig. 7B depicts an implementation of the window adjustable hysteretic comparator of the third known frequency- locking technique.

[0017] Fig. 8A depicts a fourth known frequency-locking technique, i.e. a fixed-frequency hysteretic buck converter with a periodic synchronized current signal injection at V_REF. Fig. 8B depicts the fourth known frequency-locking technique with a periodic synchronized voltage signal injection at V_REF.

[0018] Fig. 9A depicts a flowchart of a method for providing fixed frequency for hysteretic control buck converter in accordance with a present embodiment. FIG. 9B depicts a network for providing the fixed frequency for hysteretic control buck converter in accordance with the present embodiment.

[0019] Fig. 10A depicts a fixed-frequency hysteretic buck converter with tunable hysteretic window and simplified feedback voltage regulation module in accordance with the present embodiment. Fig. 10B depicts an implementation of the hysteretic comparator in accordance with the present embodiment. Fig. 10C depicts operating waveforms of the present embodiment, showing a 1 MHz fixed switching frequency. Fig. 10D depicts a measurement of the hysteretic window when the frequency is locked at 1 MHz.

[0020] Fig. 11A depicts a fixed-frequency hysteretic buck converter with another tunable hysteretic window and simplified feedback voltage regulation module in accordance with an alternate embodiment. Fig. 11B depicts generation of the synchronization current that is configured to tune the hysteretic window in accordance with the alternate embodiment. Figs. 1 C-D are simulation results showing a frequency tuning process and steady state operation waveforms, respectively, in accordance with the alternate embodiment. [0021] Fig. 12 depicts an illustration of the present embodiments deployed for a multiphase buck converter.

[0022] Skilled artisans will appreciate that elements in the figures are illustrated for simplicity and clarity and have not necessarily been depicted to scale. For example, the dimensions of some of the elements in the block diagrams or flowcharts may be exaggerated in respect to other elements to help to improve understanding of the present embodiments.

DETAILED DESCRIPTION

[0023] The following detailed description is merely exemplary in nature and is not intended to limit the invention or the application and uses of the invention. Furthermore, there is no intention to be bound by any theory presented in the preceding background of the invention or the following detailed description. It is the intent of the present embodiments to present two new approaches for fixed-frequency hysteretic control methods. These two approaches achieve frequency adjustment by tuning a hysteretic window comparator module so as to achieve improved voltage regulation and an extended frequency tuning range. In addition, current-mode control is adopted in the present embodiment thus making the provided embodiments suitable for multiphase applications that require equal current sharing. A simple current/voltage feedback network is also presented, which comprises passive components and provides significant improvement on output voltage regulation.

[0024] Based on feedback signal types, conventional hysteretic controls can be classified into voltage-mode hysteretic control (VMHC) and current-mode hysteretic control (GMHC). Referring to Fig. 1A, a conventional VMHC buck converter network 100 is depicted. The conventional VMHC buck converter network 100 includes a hysteretic window comparator 102, a buck converter 104, and a load resistor R 106. For the VMHC buck converter network 100, the duty signal ν_¾ 112, is generated according to an output voltage ripple, which implies that, a sufficiently large ripple will be required at the output 114. As such, the ripple feedback signal of the conventional VMHC is noise sensitive, which increases the difficulty for board design of VMHC buck converters.

[0025] Traditionally, the VMHC buck converter network 100 is often designed such that the output filtering capacitor C 108 has a large equivalent series resistor (ESR) r_c 110. The corresponding on/off duty time t₀t/toFF, cycle period T, switching frequency f_w and duty ratio D of the conventional VMHC network 100 can be expressed as the following Equations (1) to (4):

L - V H„

^ON

ft IN - V OUT j

(1)

LV H,

lOFF

VouT^rc

T = t_ON + t_OFF = - — ( )

r ouT ' ^y om )^rc

D = ^t<3N = ^V°^UT (4)

¹ T V ' IN

[0026] Referring to Fig. 1 B, a conventional current-mode hysteretic control (CMHC) buck converter network 150 is shown. The CMHC buck converter network 150 comprises a hysteretic window comparator 152, a buck converter 154, and a load resistor R 156. A reference voltage V_REF 160 is fed into the hysteretic window comparator 152 to be compared with the duty signal V_¾ 162. The conventional CMHC network 150 operates with a simple current sensing network 158 which comprises a resistor R«, 164 and a capacitor C_ft 66. As illustrated in Fig. 1B, instead of the output voltage ripple, it is the inductor current ripple that is used to generate the duty signal V_ft 162. Thus, sensitivity issues relating to switching noise are reduced. Due to the current sensing network 158, CMHC is widely adopted as it can easily implement over current protection and current sharing for single phase and multiphase buck converter designs. The CMHC buck converter's on/off duty time t_ON/t_0FF , cycle period T, switching frequency f_SM, and duty ratio D have relations in accordance with the following Equations (5) to (8):

T V IN V IN

[0027] Based on Equations (3) and (7), however, the switching frequency under hysteretic control is a variable depending on both converter operating conditions and circuit component values. The varying switching frequency causes EMI problems and multiphase interleaving difficulties so that conventional VMHC and CMHC buck converters both need to be improved. Several known frequency-locking techniques are attempted to suppress the drawbacks caused by the varying switching frequency. These known frequency-locking techniques are introduced in the following figure descriptions, where the first known method is based on the VMHC mode and the remaining three known methods are based on the CMHC mode. [0028] Referring to Fig. 2, a first known frequency locking buck converter network 200 is depicted. The frequency locking buck converter network 200 comprises a hysteretic window comparator 202, a buck converter 204, and a load resistor R 206. The frequency locking buck converter network 200 further comprises a frequency control loop 212 that is added to lock the switching frequency by adjusting the on/off duty period via an adaptive on-time or off-time module 214.

[0029] The first known frequency locking buck converter network 200 is typically implemented for voltage-mode constant on-time or constant off-time hysteretic DC-DC converters.

[0030] If r_c 210 is large, this first known frequency locking buck converter network 200 is suitable for continuous-conduction mode (CCM) applications. Referring to Fig. 3A, a graph 300 depicts the continuous inductor current i_L, where time (t) is plotted along the x-axis 302 and the inductor current i_L waveform when the first known frequency locking buck converter network 200 works in the continuous-conduction mode (CCM) is plotted along the y-axis 304. It can be seen from the graph 300 that the output current 306, the inductor current upward slope ST 308 and downward slope -S₂ 310 are also plotted.

[0031] Referring to Fig. 3B, a graph 320 depicts the continuous output voltage V_out, where time (t) is plotted along the x-axis 322 and the output voltage V_out waveform of the first known frequency locking buck converter network 200 working on duty in the continuous-conduction mode (CCM) is plotted along the y-axis 324. It can be seen from the graph 320 that the reference voltage 326, the output voltage upward slope Sir_c 328 and downward slope -S₂rc 330 are shown. The buck converter's on duty time t₀w334 and the delay time τ_0Ν 332 and T_OFF 336 are also shown.

[0032] Referring to Fig. 3C, a graph 340 depicts the continuous output voltage V_out) where time (t) is plotted along the x-axis 342 and the output voltage V_out waveform of the first known frequency locking buck converter network 200 working off duty in the continuous-conduction mode (CCM) is plotted along the y-axis 344. It can be seen from the graph 340 that the reference voltage 346, the output voltage upward slope S^c 348 and downward slope -S₂r_c 35 are also plotted. The buck converter's off duty time ί₀ρρ354, the delay time τ_0Ν 352 and r_OFF 356, and the switching period 358 are also shown.

[0033] By controlling the duty time t₀w 334 or ί₀ρρ354, the switching frequency f_sw of the first known frequency locking buck converter network 200 can be predicted by the following Equations (9) to (11 ).

^Sl^rc VON ⁺ F ) -_C _ „.

'^■ON ^— -; if controlling t_0N

(10)

^S2^rc VOFF ⁺ N ) -r _t ir

VR ^{+ S}i^rc ¹— -; if controlling t_OFF

where (11 )

Note that, (v_out } is the actual average output voltage, and V₀ur is the designed value.

[0034] On the other hand, if r_c is small, this first known frequency locking buck converter network 200 could be suitable for discontinuous-conduction mode (DCM) applications. Referring to Fig. 4A, a graph 400 depicts the discontinuous inductor current of the first known frequency locking buck converter network 200 working in the DCM mode, where time (t) is plotted along the x-axis 402 and the discontinuous inductor current i_L waveform is plotted along the y-axis 404. It can be seen from the graph 300 that the output current \₀υτ 406, the inductor peak current k(peak) 412, the inductor current upward slope Si 408 and downward slope -S₂ 410 are also plotted. It can also be seen from the graph 400 that when the output current Ι₀υτ is much smaller than the inductor peak current i_L(_peak) 412, negligible areas A-, 414 and A₂ 416 will be formed.

[0035] Referring to Fig. 4B, a graph 450 depicts the output voltage waveform V_out of the first known frequency locking buck converter network 200 working in the DCM mode, where time (t) is plotted along the x-axis 452 and the discontinuous output voltage V_ou, waveform is plotted along the y-axis 454. It can be seen from Fig. 4B that the switching period 460 is longer than the switching period 358 of Fig. 3C.

[0036] As the switching period is typically much longer in DCM as compared to that in CCM, the delay time r_0N and T_OFF can be ignored. In light of Figs. 4A and 4B, if one of the following two conditions is fulfilled: a) the output current l₀ur 406 is much smaller than inductor peak current k(peak) 412 (resulting in negligible areas A^ 414 and A₂ 416_. ), or b) the inductor current slopes Si~s₂ (resulting in Λ_? 414 ~A₂ 416); then the switching frequency and average output voltage (V_OUT ) can be derived in accordance with the following Equations (12) to (13):

1 2LVOUT²

T Rt_0N v_IN [y_IN -v_our)

[0037] In accordance with Equations (9) and (12), the frequency of the first known frequency locking buck converter network 200 can be locked by adjusting the on/off duty time W oFF- During this adjusting process, however, the output regulation is affected, as indicated in Equations (10) and (13). Furthermore, as the output voltage ripple is frequency dependent, the first known frequency locking buck converter network 200 of Fig. 2 is only practical to tune the frequency in a narrow range before resulting in a too large output ripple.

[0038] Referring to Fig. 5, a second known frequency locking buck converter network 500 is depicted. The second known frequency locking buck converter network 500 comprises a hysteretic window comparator 502, a buck converter 504, a load resistor R 506, a feedback network R_ft- Cft, 508 and a hysteretic control loop 510.

[0039] The second known frequency locking buck converter network 500 further comprises an adjustable delay module 512 added into the hysteretic control loop 510 so that the switching frequency can be tuned by varying this delay. The adjustable delay 512 can be injected only during the turning-on transition or turning-off transition.

[0040] Referring to Fig. 6, a graph 600 depicts voltage waveforms V of the hysteretic control loop 510 that comprises a hysteretic comparator 502 with an adjustable delay 512, where time (t) is plotted along the x-axis 602, and the comparator supply voltage V_DD 606, the reference voltage V_REF 612, the feedback voltage 614, the minimum 618 and the maximum value 608 of the feedback voltage V_ft and the minimum 616 and the maximum value 610 of the hysteretic voltage V_H are plotted along the y-axis 604.

[0041] It can be seen from the graph 600 that the delay times r_D, 620, 622 and 624 are also shown, and that the delay time r_D is controlled. Hence, the steady state switching frequency fsw and converter average output voltage (V_OUT ) can be expressed by the following Equations (14) - (16).

^Rfb^Cfl>^VIN^VH

V {ΥΐΝ V

^{A = V}REF _p ' - „ '„ ⁺ ry ^T£W - + £ (^) (^{1 6})

[0042] According to Equation (16), Δ is the sum of the frequency-independent output voltage drop, with an ideal value equal to zero. Its first component is the effective DC offset of the hysteretic comparator 502, the second component is due to the undesired delay, and the last component is due to the inductor ESR voltage drop.

[0043] This second known frequency-locking buck converter network 500 utilizes a very simple architecture. By changing the adjustable delay 512, the frequency can be locked within a wide range and the limitation normally lies with the highest achievable locking frequency (as a negative delay time T_D is impossible). However, in a similar manner to the first known frequency-locking, when the frequency control variable (in this case T_D ) is adjusted to lock the frequency, output regulation is sacrificed.

[0044] Referring to Fig. 7A, a third known frequency-locking buck converter network 700 is depicted. The third known frequency locking buck converter network 700 comprises a hysteretic window comparator 702, a buck converter 704, a load resistor R 706, a frequency regulation loop 708, a current sensing loop 710 and a voltage regulation loop 712.

[0045] The hysteretic window of the comparator 702 in FIG. 7A is adjustable so as to change the switching frequency f_siv. Referring to Fig. 7B, an implementation network 750 of the adjustable hysteretic window comparator 702 is illustrated. It can been seen from Fig. 7B that network 750 uses resistors R_† 752, R₂ 754, R₃ 756 and R₄ 758 to adjust the hysteretic window of the hysteretic comparator 702 wherein R₄ 758 is realized by a discrete voltage controlled resistor (VCR).

[0046] For the third known frequency-locking buck converter network 700 that uses an adjustable hysteretic window comparator 702, the switching frequency f^, the comparator hysteretic window V_H and the comparator effective DC offset are derived in accordance with the following Equations (17) to (19):

V„ = (18)

(R_{1 +} R₂ )(R_{3 +} R₄ ) + R₃R₄

REF (19)

{R_{l +} R₂ )(R₃ + R₄ ) + R₃R₄ where K_c is the current sensing gain.

[0047] The third known frequency locking technique as depicted in Figs. 7A and 7B can be implemented through discrete components. However, its frequency-tuning range is small, as limited by R₄ range, R₄ being utilized in Equation (18). Also, it utilizes a complicated current sensing circuit. In addition, due to the large comparator effective DC offset expressed in Equation (19) which is affected by the frequency-tuning operation, an extra op-amp based voltage loop compensation (e.g. voltage regulation loop 712 illustrated in FIG. 7A) is compulsory, thereby increasing design complexity, silicon area and power consumption.

[0048] Referring to Fig. 8A, a fourth known frequency locking buck converter network 800 is depicted. The fourth known frequency locking buck converter network 800 comprises a hysteretic window comparator 802, a buck converter 804, a load resistor R 806, a resistor R, 816, a feedback network R_ft- C_¾ 808 and a periodic synchronization signal l_sync 810 at V_REF. Referring to Fig. 8B, another fourth known frequency locking buck converter network 850 is depicted. The fourth known frequency locking buck converter network 850 comprises a hysteretic window comparator 852, a buck converter 854, a load resistor R 856, a synchronization resistor R_sync 866, a synchronization capacitor C_sync 868, a feedback network R_ft- C_fc 858 and a periodic synchronization signal PWM_ref 860 at V_REF.

[0049] As shown in^" Figs, 8A and 8B, the reference clock signals CLK_REF 812, 862 are modulated into a periodic signal and injected as a synchronization signal into V_REF. The synchronization signal can be either a current, e.g., the periodic l_sync 810 in Fig. 8A, or a voltage, e.g. the periodic PWM_ref 860 in FIG. 8B. The synchronization signal adds a ripple into V_REF which will appear on the hysteretic window so that the feedback signals V_ft 814, 864 will follow the envelope of the periodic ripple, leading to the following Equation (20):

[0050] The fourth known frequency locking/tuning technique as illustrated in Figs. 8A and 8B simplifies the frequency control circuits as it does not require a phase-frequency detector (PFD) to compare the duty signal with the reference clock signal CLK_REF. However, this fourth frequency-locking technique through direct synchronization signal injection can only work in a very narrow frequency range. The current injection method in FIG. 8A degrades output voltage regulation as it adds a DC offset to V_REF. The voltage injection method in FIG. 8B maintains good voltage regulation at the cost of employing an additional voltage regulation loop. Furthermore, as the phase lag (between converter switching signal and CLK_REF) in FIG. 8B is sensitive to the values of R_sync 866 and C_sync 868, this fourth frequency-locking method is not suitable for multiphase applications where accurate phase interleaving is required.

[0051] In view of the above, all the conventional frequency-locking networks and methods have some common drawbacks, i.e., having difficult or sacrificed output voltage regulation and limited frequency-tuning range. In order to obtain improved frequency locking for high performance electronics requiring stable power supply, a new hysteretic window tuning method which enables frequency fixing is provided in accordance with a present embodiment. Also provided is an easy to implement method to regulate output voltage. DC-DC Buck Converter networks implementing the new method are also provided. In particular, as will be discussed, the present DC-DC buck converter embodiment enables good voltage regulation, while an alternate DC-DC buck converter embodiment enables a wide frequency tuning range.

[0052] Referring to Fig. 9A, a flowchart 900 a method for hysteretic control in accordance with the present embodiment is depicted. At step 902, a tunable hysteretic window module is provided to fix a switching frequency for a hysteretic buck converter, the tunable hysteretic window module comprising a tuning module and a hysteretic window comparator module. At step 904, a current sense/voltage regulation module is provided so that it can be coupled with a buck converter and the hysteretic window comparator module, such that a feedback network can be formed to feed back a signal into the hysteretic window comparator module. At step 906, the tuning module is tuned such that a reference signal, a reference clock and the signal that was fedback into the hysteretic window comparator module are coupled to the tunable hysteretic window module, such that the switching frequency can be fixed.

[0053] Referring to Fig. 9B, a network 950 for providing fixed frequency for hysteretic buck converter is depicted. The network 950 comprises a tunable hysteretic window module 962, a step down/buck converter 954, and a current sense/voltage regulation module 956. A reference voltage signal V_REF 966 and a reference clock signal CLK_REF 968 are provided to be fed into the tunable hysteretic window module 962, wherein the tunable hysteretic window module 962 comprises a hysteretic window comparator module 952 and a tuning module 960. The reference voltage V_REF 966 is fed to the tunable hysteretic window module 962, more preferably, to the hysteretic window comparator module 952. A feedback network 958 is formed engaging the hysteretic window comparator module 952 and the voltage regulation/current sense module 956, such that a feedback voltage V 964 is fed to the hysteretic window comparator module 952 and good regulation of the output voltage V₀UT 970 is achieved. The tuning module 960 is configured to be in a bilateral communication with the hysteretic window comparator module 952 such that the hysteretic window comparator feedback can be changed, thereby modifying the hysteretic window and eventually fixing the switching frequency.

[0054] Referring to Fig. 10A, a circuit diagram 1000 depicts a fix-frequency hysteretic buck converter network in accordance with the present embodiment. The present embodiment 1000 comprises a comparator 1002, a buck converter 1004, a load resistor R 1006, a feedback network 1008, and a tuning module 1010. The tuning module 1010 comprises a resistive component Ri 1012, a phase-frequency detector (PFD)/charge pump (CP)/low pass filter (LPF) module 1014 and a resistor R₂ 1016. The tuning module 1010 is configured to conduct hysteretic window adjustment through tuning the positive feedback amount V₊ 1018 of the comparator 1002. Referring to Fig. 10B, a circuit 1500 depicts an implementation of the hysteretic comparator in accordance with the present embodiment where the resistive component Ri 1012 of Fig. 10A is implemented by a MOS transistor 1512 operating in a triode region.

[0055] In accordance with the first embodiment as illustrated in Fig. 10A, by tuning resistive component R the change in the comparator feedback will modify the hysteretic window and eventually change the switching frequency. The fixed switching frequency f_sw can be derived in accordance with Equation 21 ):

where V_DD is the comparator supply voltage and that the resistive component R1 is implemented by a MOS transistor operating in the triode region as illustrated in Fig. 10B.

[0056] The feedback network 958 of Fig. 9B, illustrated in Fig. 10A as a feedback network 1008 comprising R_fb-R_fb-C_ft, is improved from the conventional feedback network 158 as shown in FIG. 1B. The feedback network 1008 can provide improved output voltage regulation expressed as Equations (22) - (23): (22),

where

(23).

[0057] By using two equal resistors of R_ffi to sense half of the switching node voltage V_x as the feedback voltage V_ft, the output voltage (V_om ) can be designed to be 2V_REF, with a small DC error as derived in Equation (23). The voltage regulation is improved because the first term in Equation (23) becomes zero when two conditions are satisfied: a) the hysteretic comparator 1002, 1502 is supplied by the buck converter output (i.e.,

and b) the difference between the converter real output voltage (V_OUT) and the designated output voltage (V_0UT) isnegligible. The improvement can be shown by a comparison as shown in Table 1 below between the conventional design, the present embodiment with a conventional Rfb-C_ft, feedback network and the present embodiment with the proposed _fb- _fb-C_fb feedback network:

[0058] Table 1

[0059] In addition, the improved feedback network 1008 senses inductor current /_L 1020 when a small inductor ESR r_L is presented, thereby advantageously providing intrinsic over-current protection and adaptive voltage positioning (AVP) for single phase implementation (e.g. for buck converters), as well as droop method current sharing control for multiphase implementation (e.g. for buck converters) . [0060] The circuit 1000 has been fabricated in XFAB 1 pm SOI process with measurement results shown in FIGs. 10C and 10D. Fig. 10C shows the operating waveforms at 20V to 5V voltage conversion, where the switching node voltage V_x (same frequency as the duty signal) is synchronized with the reference clock CLK_REF at a fixed frequency of 1 MHz. Fig. 10D shows that the comparator hysteretic window stays at steady state after the frequency is locked at 1MHz. The glitch on V_H is because a small capacitor is added in parallel with R₂ (see Fig. 10A) to enhance the positive feedback during transient.

[0061] As illustrated in Figs. 10A to 10D, the present embodiment of the frequency-tuning method utilizes simple circuits to provide better output voltage regulation than conventional buck converters. However, dtte to the finite tuning range of Ri, the frequency-tuning range of the hysteretic converter is limited, which introduces frequency control difficulties when using low- cost large-tolerance components and operating the buck converter with wide input/output voltage ranges. Therefore, an alternate embodiment of the present frequency-locking method will be described which provides a wider frequency-tuning range.

[0062] Referring to Fig. 11 A, a circuit 1100 a fixed-frequency hysteretic buck converter network in accordance with the alternate embodiment. The circuit 1100 comprises a comparator 1102, a buck converter 1104, a load resistor R 1106, a feedback network 1108 and a tuning module 1110. The tuning module 1110 comprises a tunable DC current shift 1112, a phase-frequency detector (PFD)/charge pump (CP)/low pass filter (LPF) module 1114 and a resistor R₂ 1116. The tuning module 1110 is configured to conduct hysteretic window adjustment through adding a tunable DC current shift 1112 at the positive input terminal 1118 of the comparator 1102. Referring to Fig. 10B, a circuit 1500 depicts an implementation of the hysteretic comparator where the resistive component 1012 of Fig. 10A is implemented by a MOS transistor 1512 operating in the triode region. [0063] As illustrated in FIG. 11 A, the frequency control signal V_c 1120 will be converted into a current /_sync 1112 which is sunk from the positive input terminal 1118 of the hysteretic comparator 1102. It causes an additional DC shift on the comparator positive feedback, thereby altering the hysteretic window. In this manner, the switching frequency f_sw is adjustable within a very wide range, as expressed in the following Equations (24) and (25):

[0064] It should be noticed that, when /_sync 1112 is positive, the switching frequency f_sw is reduced from a free-running frequency, as in the case of conventional methods/designs. However, under the alternate embodiment, when /_sy„_c 11 2 is negative, the switching frequency can also be increased higher than the free-running frequency. Thus, the frequency tuning in accordance with the alternate embodiment is not only expansive but also bidirectional. Further, in accordance with the alternate embodiment, even if /_sy„_c 1112 is kept positive, the bidirectional frequency tuning can be achieved by retaining or removing the inverter from the comparator output using a switch S 1122.

[0065] The output voltage of the alternate embodiment is derived:

where

[0066] The tuning module 1110 also provides an improved feedback network 1118 that helps to cancel the first term in Equation (27), thereby achieving improved output regulation. [0067] Referring to Fig. 1 1B, a circuit 1150 can convert a frequency control signal V_c 1158 into a current l_sync 1 160. The circuit includes MOS transistors 1 154, 1156 and 1158.

[0068] The simulation results for the alternate embodiment are shown in Figs. 11 C and 1 D. In Fig. 11 C, the DC-DC Buck converter starts with a switching frequency r^"sw of about 3MHz and the target frequency is 1 MHz. The synchronization current /_S/CT7 (i.e. I_blas in Figs. 11C and11D) is increased gradually, and as shown in Equations (24) and (25), the switching frequency f_siv will be reduced. Therefore, at steady state shown in FIG. 11 D, the switching frequency is locked to 1 MHz and the cycle period becomes 1 ps.

[0069] In view of the above description, the present method and embodiments of fixed- frequency hysteretic controlled buck converters are advantageously suitable for modern CPU power supplies. First, hysteretic control in accordance with the present embodiments results in stable operation with fast response. Second, the present method and networks are based on current mode operation, thereby advantageously achieving small output voltage ripple, high noise immunity, inherent adaptive voltage positioning (A P), over-current protection, and multiphase current sharing. Third, the circuits 1000, 1500, 1 100, 1150 in accordance with the present embodiments are simple and no operational amplifier is required. Fourth, the circuits 1000, 1500 are configured in accordance with the present embodiments to provide good voltage regulation by eliminating effects due to frequency control variables; while the circuits 1100, 1150 are configured in accordance with the alternate embodiments to provide a wide frequency- tuning range and bidirectional tuning capability.

[0070] In addition, the above described method and embodiments can also be utilized in an interleaved multiphase configuration, as shown in Fig. 12. The fixed frequency operation will inherently guarantee ripple cancellation, and the current mode thereof will aid in achieving current sharing among the various phases. [0071] It should be appreciated that the exemplary embodiments are only examples, and are not intended to limit the scope, applicability, operation, or configuration of the invention in any way. Rather, the foregoing detailed description will provide those skilled in the art with a convenient road map for implementing an exemplary embodiment of the invention, it being understood that various changes may be made in the function and arrangement of elements and method of operation described in an exemplary embodiment without departing from the scope of the invention as set forth in the appended claims.

Claims

Claims It is claimed that:

1. A method for providing a fixed switching frequency for a hysteretic buck converter, the method comprising using a tunable hysteretic window module to fix the fixed switching frequency.

2. The method in accordance with claim 1 , further comprising using a feedback network to control the fixed switching frequency.

3. The method in accordance with claim 1 , further comprising providing a tuning module to tune the tunable hysteretic window module.

4. The method in accordance with claim 3, further comprising using a tunable resistive component to tune the tuning module.

5. The method in accordance with claim 3, further comprising adding in a direct current (DC) shift to tune the tuning module.

6. The method in accordance with claim 2, further comprising a sensing inductor current in the feedback network to regulate an output voltage.

7. A current mode hysteretic buck converter, comprising:

a tunable hysteretic window module;

a buck converter; and a voltage regulation module, wherein the tunable hysteretic window module, the buck converter and the voltage regulation module are coupled such that a fixed switching frequency can be achieved.

8. The converter in accordance with claim 7, wherein the tunable hysteretic window module comprises a tuning module and a hysteretic window comparator module.

9. The converter in accordance with claim 8, wherein a feedback network is formed connecting the voltage regulation module and the hysteretic window comparator module, and wherein the hysteretic window comparator module and the feedback network are coupled such that voltage regulation can be achieved.

10. The converter in accordance with claim 8, wherein the tuning module comprises a tunable resistive component, and wherein the tuning module is coupled to the hysteretic window comparator module such that a positive feedback of the hysteretic window comparator module is configured to be tuned by the tunable resistive component.

11. The converter in accordance with claim 10, wherein the tunable resistive component is a MOS transistor.

12. The converter in accordance with claim 8, wherein the tuning module comprises a tunable DC shift which is configured to generate a synchronized current, and wherein the DC shift is coupled to the positive input terminal of the hysteretic window comparator module such that the hysteretic window can be tuned in response to the tunable DC shift.

13. An interleaved multiphase circuit comprising one or more current mode hysteretic DC-DC converters, each of the one or more current mode hysteretic DC-DC converters comprising: a tunable hysteretic window module;

a buck converter; and

a voltage regulation module,

wherein the tunable hysteretic window module, the buck converter and the voltage regulation module of each of one or more DC-DC converters are coupled such that a fixed switching frequency can be achieved in the one or more DC-DC converters.