CN117855284A

CN117855284A - Thin film transistor and transistor array substrate

Info

Publication number: CN117855284A
Application number: CN202311208685.4A
Authority: CN
Inventors: 具素英; 金明花; 金億洙; 金亨俊
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2022-10-06
Filing date: 2023-09-19
Publication date: 2024-04-09

Abstract

A thin film transistor and a transistor array substrate are provided. The thin film transistor includes: an active layer including a channel region, a first conductive region, and a second conductive region; a gate insulating layer on a portion of the active layer; a first via penetrating a portion of the first conductive region; a second via penetrating a portion of the second conductive region; a gate electrode overlapping the channel region of the active layer; a first electrode electrically connected to the first conductive region; and a second electrode electrically connected to the second conductive region. The side of the first electrode adjacent to the first through hole is parallel to the side of the first through hole, and the first electrode includes a protrusion portion at both ends thereof and a groove portion concavely recessed from the gate electrode.

Description

Thin film transistor and transistor array substrate

The present application claims priority and benefit of korean patent application No. 10-2022-012888 filed on 10 month 6 of 2022 and korean patent application No. 10-2023-0016817 filed on 2 month 8 of 2023, which are incorporated herein by reference in their entireties.

Technical Field

The present disclosure relates to a thin film transistor and a transistor array substrate including the same.

Background

With the development of information society, the demand for display devices for displaying images has increased and diversified. For example, display devices have been applied to various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart televisions.

The display device may include a display panel emitting light for displaying an image and a driver supplying a signal or power for driving the display panel.

The display panel may include a display region in which light for displaying an image is emitted, and may include a polarizing member or a light emitting member disposed in the display region.

The subpixels emitting light of each brightness and color may be arranged in the display area.

In addition, the display panel may include a transistor array substrate including a substrate and a circuit layer including pixel drivers disposed on the substrate and each corresponding to a subpixel. With such a transistor array substrate, light of each brightness and color can be emitted from the sub-pixels of the display area.

Each of the pixel drivers of the transistor array substrate may include at least one Thin Film Transistor (TFT).

The thin film transistor includes a gate electrode, a first electrode, a second electrode, and an active layer. Such a thin film transistor may be a switching element in which a current flows through a channel region of the active layer when a voltage difference between the gate electrode and the first electrode becomes a threshold value or more by a driving signal transmitted to the gate electrode.

Disclosure of Invention

When manufacturing a transistor array substrate including a thin film transistor, as the number of mask processes increases, manufacturing costs may increase and yield may decrease.

However, when the number of mask processes is reduced, the components of the thin film transistor cannot be set by the mask process suitable for each characteristic, and thus, the components of the thin film transistor will likely not be set as designed, so that the reliability and uniformity of the current characteristics of the thin film transistor may be deteriorated.

Aspects and features of embodiments of the present disclosure provide a thin film transistor that can be provided by a relatively small number of mask processes and has improved current characteristics, and a transistor array substrate including the same.

According to one or more embodiments, a thin film transistor includes: an active layer including a channel region, a first conductive region connected to one side of the channel region, and a second conductive region connected to the other side of the channel region; a gate insulating layer on a portion of the active layer; a first via penetrating a portion of the first conductive region; a second via penetrating a portion of the second conductive region; a gate electrode in the electrode conductive layer on the gate insulating layer and overlapping the channel region of the active layer; a first electrode in the electrode conductive layer adjacent to one side of the first via hole and electrically connected to the first conductive region; and a second electrode in the electrode conductive layer adjacent to one side of the second via hole and electrically connected to the second conductive region. The side of the first electrode adjacent to the first through hole is parallel to the side of the first through hole, and the first electrode includes a protrusion at both ends thereof and a groove portion concavely recessed from the gate electrode as compared with the protrusion.

The first conductive region corresponds to a first electrode connection hole penetrating the gate insulating layer. The second conductive region corresponds to a second electrode connection hole penetrating the gate insulating layer. The first electrode extends to the first conductive region and is in contact with the first contact region of the first conductive region. The second electrode extends to the second conductive region and is in contact with the second contact region of the second conductive region.

The length of the first via region between the side of the first via hole and the first contact region in the first conductive region is greater than the width of the side of the first via hole.

The side of the second electrode adjacent to the second via is parallel to the side of the second via and symmetrical to the first electrode with respect to the gate electrode, and the second electrode includes a protrusion portion and a groove portion. The length of the second via region located between one side of the second via hole and the second contact region in the second conductive region is greater than the width of one side of the second via hole.

The first conductive region further includes a first main region between the channel region and the first via region. The second conductive region further includes a second main region between the channel region and the second via region.

The maximum width of the first contact region is larger than the width of the groove portion in a first direction in which the first electrode and the gate electrode face each other.

In the first direction, a difference between the maximum width of the first contact region and the width of the groove portion is 0.5 μm or more.

The width of the first conductive region is greater than the width of the first via in a second direction intersecting the first direction. One side of the edge of the first through hole in the first direction is in contact with the first via region, and the other side of the edge of the first through hole in the first direction and both sides of the edge of the first through hole in the second direction are in contact with the first main region.

The width of the groove portion in the second direction is equal to or less than 1/2 of the width of the first through hole in the second direction.

The width of the groove portion in the second direction is 1 μm or more.

The length of the first via region corresponds to a sum of twice the width of the first through hole in the second direction and the width of the groove portion in the first direction.

One side of the first electrode further includes an intermediate protruding portion between the two or more recessed portions.

The width of the intermediate protrusion in the second direction is 1 μm or more.

The groove portion has a curved arcuate shape. A portion of the protrusion faces the first through hole in the first direction. The length of the first passage region corresponds to the arc length of the groove portion and the width of the portion of the protrusion portion in the second direction.

The active layer further includes: a first inactive region connected to the first contact region of the first conductive region and covered by the gate insulating layer; and a second inactive region connected to the second contact region of the second conductive region and covered by the gate insulating layer.

According to one or more embodiments, a transistor array substrate includes: a substrate including a display region in which sub-pixels are arranged; and a circuit layer on the substrate and including pixel drivers, each of the pixel drivers corresponding to a sub-pixel of the sub-pixels. Each of the pixel drivers includes at least one thin film transistor. The thin film transistor of the circuit layer includes: an active layer on the substrate and including a channel region, a first conductive region connected to one side of the channel region, and a second conductive region connected to the other side of the channel region; a gate insulating layer on a portion of the active layer; a first via penetrating a portion of the first conductive region; a second via penetrating a portion of the second conductive region; a gate electrode in the electrode conductive layer on the gate insulating layer and overlapping the channel region of the active layer; a first electrode in the electrode conductive layer adjacent to one side of the first via hole and electrically connected to the first conductive region; and a second electrode in the electrode conductive layer adjacent to one side of the second via hole and electrically connected to the second conductive region. The side of the first electrode adjacent to the first through hole is parallel to the side of the first through hole, and the first electrode includes a protrusion at both ends thereof and a groove portion concavely recessed from the gate electrode as compared with the protrusion.

The first conductive region corresponds to a first electrode connection hole penetrating the gate insulating layer. The second conductive region corresponds to a second electrode connection hole penetrating the gate insulating layer. The first electrode extends to the first conductive region and contacts a first contact region of the first conductive region. The second electrode extends to the second conductive region and contacts a second contact region of the second conductive region. The length of the first via region between the side of the first via hole and the first contact region in the first conductive region is greater than the width of the side of the first via hole. The side of the second electrode adjacent to the second via hole is parallel to the side of the second via hole, is symmetrical to the first electrode with respect to the gate electrode, and includes a protruding portion and a recessed portion. The length of the second via region located between one side of the second via hole and the second contact region in the second conductive region is greater than the width of one side of the second via hole.

The first conductive region further includes a first main region between the channel region and the first via region. The maximum width of the first contact region is larger than the width of the groove portion in a first direction in which the first electrode and the gate electrode face each other. The width of the first conductive region is greater than the width of the first via in a second direction intersecting the first direction. One side of the edge of the first through hole in the first direction is in contact with the first via region, and the other side of the edge of the first through hole in the first direction and both sides of the edge of the first through hole in the second direction are in contact with the first main region.

The transistor array substrate further includes: and a light emitting element layer on the via layer of the circuit layer. The light-emitting element layer includes: the light emitting element is electrically connected to the pixel driver through an anode contact hole penetrating through the hole layer and the interlayer insulating layer. The circuit layer further includes: a scan gate line for transmitting a scan signal to the pixel driver; a data line for transmitting a data signal to the pixel driver; and an initialization voltage line for transmitting the initialization voltage to the pixel driver. The pixel driver among the pixel drivers includes: a first thin film transistor connected to a light emitting element among light emitting elements connected in series between a first power line and a second power line for transmitting a first power source and a second power source for driving the light emitting element; a second thin film transistor electrically connected between the data line and the gate electrode of the first thin film transistor and configured to be turned on based on a scan signal scanning the gate line; a pixel capacitor electrically connected to a first node between the gate electrode of the first thin film transistor and the second thin film transistor and a second node between the first thin film transistor and the light emitting element; and a third thin film transistor electrically connected between the initialization voltage line and the second node and configured to be turned on based on an initialization control signal of the initialization gate line.

The circuit layer further includes: a light blocking electrode in the light blocking conductive layer on the substrate and overlapping the active layer; a buffer layer on the substrate and covering the light blocking conductive layer; an interlayer insulating layer on the buffer layer and covering the thin film transistor; and a via layer on the interlayer insulating layer. The interlayer insulating layer is in contact with the buffer layer through each of the first and second via holes.

The first power line is on the light-blocking conductive layer. The first electrode of the first thin film transistor is electrically connected to the first power line through a power connection hole penetrating the gate insulating layer and the buffer layer. The second electrode of the first thin film transistor is electrically connected to the light blocking electrode through a light blocking connection hole penetrating the gate insulating layer and the buffer layer.

A thin film transistor according to one or more embodiments includes an active layer on a substrate, a gate insulating layer on a portion of the active layer, and a gate electrode, a first electrode, and a second electrode in an electrode conductive layer on the gate insulating layer.

In this manner, the gate electrode, the first electrode, and the second electrode are formed in the same layer, and thus, the number of mask processes required for manufacturing the thin film transistor can be reduced.

In addition, the active layer includes a channel region overlapping the gate electrode, a first conductive region connected to one side of the channel region, and a second conductive region connected to the other side of the channel region.

The thin film transistor according to one or more embodiments further includes a first via penetrating a portion of the first conductive region and a second via penetrating a portion of the second conductive region because the manufacturing process has a reduced number of mask processes.

The first electrode may be adjacent to one side of the first via hole and electrically connected to the first conductive region of the active layer. That is, a side of the first electrode adjacent to a side of the first through hole is parallel to the side of the first through hole.

A portion of the first conductive region is removed through the first via, and therefore, the first electrode is in contact with the first via region, which is located between one side of the first via and one side of the first electrode in the first conductive region. Thus, the resistance between the first electrode and the first conductive region may be affected by the length of the first via region.

Thus, in one or more embodiments, a side of the first electrode adjacent to a side of the first via hole includes a protrusion at both ends thereof and a groove portion concavely recessed from the gate electrode as compared to the protrusion.

As such, one side of the first electrode includes the groove portion, and thus, the length of the first via region located between the first electrode and the first via hole in the first conductive region is not limited to a length within the width of one side of the first via hole, and may become larger than the width of one side of the first via hole.

In other words, the length of the first via region may be increased by twice the width of the groove portion recessed more concavely than the protruding portion without increasing the width of the side of the first through hole as compared with the width of the side of the first through hole.

In addition, the second electrode may be symmetrical to the first electrode with respect to the gate electrode. Accordingly, the length of the second via region located between the side of the second via hole and the second electrode in the second conductive region may become greater than the width of the side of the second via hole.

Thus, the resistance between the first conductive region and the first electrode may be reduced by increasing the length of the first via region. In addition, the resistance between the second conductive region and the second electrode may be reduced by increasing the length of the second via region.

Accordingly, the current characteristics of the thin film transistor can be improved, and thus the uniformity of the current characteristics of the thin film transistor can be improved.

In the transistor array substrate according to the embodiment, the pixel driver of the sub-pixel includes the thin film transistor in which the resistance between each of the first electrode and the second electrode and the active layer is reduced, and thus, the difference in driving current due to the difference in current characteristics between the thin film transistors can be reduced. Accordingly, a luminance difference due to a difference in driving current for each sub-pixel may be reduced, and thus, display quality of a display device having a transistor array substrate may be improved.

However, effects, aspects, and features of the present disclosure are not limited to the foregoing effects, aspects, and features, and various other effects, aspects, and features are included in the present disclosure.

Drawings

The above and other aspects and features of the present disclosure will become more apparent by describing in detail embodiments thereof with reference to the attached drawings in which:

FIG. 1 is a perspective view illustrating a display device in accordance with one or more embodiments;

fig. 2 is a plan view illustrating the display device of fig. 1;

FIG. 3 is a cross-sectional view taken along line A-A' of FIG. 1;

fig. 4 is a layout diagram showing an example of a circuit layer of the transistor array substrate of fig. 3;

Fig. 5 is an equivalent circuit diagram showing an example of one pixel driver corresponding to one sub-pixel of the transistor array substrate of fig. 4;

fig. 6 is a plan view showing a first example of a first thin film transistor of the pixel driver of fig. 5;

FIG. 7 is a cross-sectional view taken along line B-B' of FIG. 6;

fig. 8 is an enlarged view illustrating a portion C of fig. 6;

fig. 9 is a plan view showing a comparative example different from the example of fig. 6;

fig. 10 is an enlarged view illustrating a portion D of fig. 9;

fig. 11 is a plan view showing a second example of the first thin film transistor of the pixel driver of fig. 5;

fig. 12 is a plan view showing a third example of the first thin film transistor of the pixel driver of fig. 5;

FIG. 13 is a flow diagram illustrating a method of fabricating a transistor array substrate in accordance with one or more embodiments; and

fig. 14 to 26 are diagrams showing processes related to the respective steps of fig. 13.

Detailed Description

Embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings. However, the embodiments may be provided in different forms and should not be construed as limiting. Like reference numerals refer to like components throughout this disclosure. In the drawings, the thickness of layers and regions may be exaggerated for clarity.

Some of the components that are not relevant to the description may not be provided for the purpose of describing embodiments of the present disclosure.

It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may also be present. In contrast, when an element is referred to as being "directly on" another element, there may be no intervening elements present.

Further, the phrase "in a plan view" means when the object portion is viewed from above, and the phrase "in a schematic cross-sectional view" means when a schematic cross-section taken by vertically cutting the object portion is viewed from the side. The term "stacked" or variations thereof means that a first object may be above or below or sideways from a second object, and vice versa. In addition, the term "stacked" may include stacked, facing or facing, extending over … …, covering or partially covering, or any other suitable terminology as will be appreciated and understood by those of ordinary skill in the art. The expression "not stacked" may include meanings such as "spaced apart from … …" or "offset from … …" or "offset from … …" as would be appreciated and understood by one of ordinary skill in the art. The terms "facing" and "facing" may mean that a first object may be directly or indirectly opposite a second object. In the case where the third object is interposed between the first object and the second object, the first object and the second object may be understood to be indirectly opposite to each other although still facing each other.

For ease of description, spatially relative terms "below … …," "below … …," "lower," "above … …," "upper," and the like may be used herein to describe one element or component's relationship to another element or component as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, in the case of turning the device shown in the drawings, a device positioned "below" or "beneath" another device may be placed "above" the other device. Thus, the illustrative term "below" may include both the lower and upper positions. The device may also be oriented in other directions, so that spatially relative terms may be construed differently depending on the orientation.

When an element is referred to as being "connected" or "coupled" to another element, it can be "directly connected" or "directly coupled" to the other element or be "electrically connected" or "electrically coupled" to the other element with one or more intervening elements therebetween. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and/or groups thereof.

It will be understood that, although the terms "first," "second," "third," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another or for convenience of description and explanation thereof. For example, when "a first element" is discussed in the specification, the "first element" may be referred to as "a second element" or "a third element" and the "second element" and the "third element" may be referred to in a similar manner without departing from the spirit and scope of the disclosure herein.

The term "about" or "approximately" as used herein includes the stated values and means: taking into account the measurements being referred to and errors associated with the measurement of a particular quantity (e.g., limitations of the measurement system), are within acceptable deviations of a particular value as determined by one of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated values.

In the description and claims, the term "and/or" is intended for purposes of its meaning and explanation to include any combination of the terms "and" or ". For example, "a and/or B" may be understood to mean "A, B or a and B". The terms "and" or "may be used in a conjunctive or disjunctive sense and may be understood to be equivalent to" and/or ". In the description and claims, the phrase "at least one (seed/person)" in … … is intended to include, for its meaning and for purposes of explanation, the meaning of "at least one (seed/person) selected from the group of … …". For example, "at least one (seed/person) of a and B" may be understood to mean "A, B or a and B".

Unless otherwise defined or implied, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

Hereinafter, embodiments will be described with reference to the drawings.

Fig. 1 is a perspective view illustrating a display device in accordance with one or more embodiments. Fig. 2 is a plan view illustrating the display device of fig. 1. Fig. 3 is a cross-sectional view taken along line A-A' of fig. 1.

Referring to fig. 1 and 2, a display device 1 is a device that displays moving images or still images, and may be used as a display screen of various products such as televisions, laptop computers, monitors, billboards, and internet of things (IOT) devices, as well as portable electronic devices such as mobile phones, smart phones, tablet Personal Computers (PCs), smartwatches, watch phones, mobile communication terminals, electronic notebooks, electronic books, portable Multimedia Players (PMPs), navigation devices, and/or Ultra Mobile PCs (UMPCs).

The display device 1 may be a light emitting display device such as an organic light emitting display device using an Organic Light Emitting Diode (OLED), a quantum dot light emitting display device including a quantum dot light emitting layer, an inorganic light emitting display device including an inorganic semiconductor, and a micro light emitting display device using a micro or nano light emitting diode (micro LED or nano LED). Hereinafter, the display device 1 will be mainly described as an Organic Light Emitting Diode (OLED) display. However, the present disclosure is not limited thereto, and may be applied to a display device including an organic insulating material, an organic light emitting material, and a metal material.

The display device 1 may be formed flat, but is not limited thereto. For example, the display device 1 may include curved surface portions formed at left and right ends thereof and having a constant curvature or a variable curvature. In addition, the display device 1 may be flexibly formed to be curved, bent, folded, and/or curled.

The display device 1 may include a transistor array substrate 10.

The display device 1 may further include a cover substrate 20 facing the transistor array substrate 10 and covering the light emitting element layer 13 (see, for example, fig. 3).

In addition, the display device 1 may further include a display driving circuit 31 and a circuit board 32, the display driving circuit 31 being for supplying corresponding data signals to the data lines DL (see, for example, fig. 4) of the circuit layer 12 (see, for example, fig. 3) of the transistor array substrate 10, and the circuit board 32 being for supplying various signals and power to the transistor array substrate 10 and the display driving circuit 31.

Referring to fig. 3, the transistor array substrate 10 may include a substrate 11 and a circuit layer 12 disposed on the substrate 11.

The transistor array substrate 10 may further include a light emitting element layer 13 disposed on the circuit layer 12.

That is, the light emitting element layer 13 is disposed between the substrate 11 and the cover substrate 20.

The circuit layer 12 supplies a driving signal corresponding to an image signal for each of the sub-pixels to the light emitting element layer 13. The light emitting element layer 13 may emit light in each of the sub-pixels according to a driving signal. The light emitted from the light emitting element layer 13 may be emitted to the outside through at least one of the substrate 11 and the cover substrate 20. Accordingly, the display device 1 can provide a function of displaying an image.

In addition, the display apparatus 1 may further include a touch sensing unit that senses coordinates of a point touched by a user on a display surface on which light for displaying an image is emitted.

The touch sensing unit may be attached to one surface of the cover substrate 20 or embedded between the transistor array substrate 10 and the cover substrate 20.

The touch sensing unit may include touch electrodes disposed in a touch sensing area corresponding to the display surface and made of a transparent conductive material.

Such a touch sensing unit may detect whether there is a touch input and coordinates of a point at which the touch is input by periodically sensing a change in capacitance value of the touch electrode in a state where a touch driving signal is applied to the touch electrode.

The cover substrate 20 may face the transistor array substrate 10, and may be bonded to the transistor array substrate 10.

The cover substrate 20 may be a device that provides rigidity for withstanding external physical impacts and electrical shocks. The cover substrate 20 may be made of a transparent material having insulating properties and rigidity.

In addition, the display device 1 may further include a sealing layer 30, the sealing layer 30 being disposed at an edge between the transistor array substrate 10 and the cover substrate 20, and bonding the transistor array substrate 10 and the cover substrate 20 to each other.

In addition, the display device 1 may further include a filling layer filling the space between the transistor array substrate 10 and the cover substrate 20.

As shown in fig. 1 and 2, the display surface of the display device 1 may have a rectangular shape having a short side in a first direction DR1 and a long side in a second direction DR2 intersecting the first direction DR 1. However, this is only an example, and the shape of the display surface of the display device 1 may be realized in various forms.

As an example, the display surface may have a shape in which corners where short sides in the first direction DR1 and long sides in the second direction DR2 meet are rounded with a suitable curvature (e.g., a predetermined curvature). Alternatively, the display surface may have a shape such as a polygonal shape, a circular shape, and/or an elliptical shape.

Fig. 1 has shown that the transistor array substrate 10 has a flat plate shape, but the present disclosure is not limited thereto. That is, the transistor array substrate 10 may have a shape of which both ends are bent in the second direction DR 2. Alternatively, the transistor array substrate 10 may be flexibly provided to be bent, folded, or curled.

The display driving circuit 31 outputs signals and voltages for driving the transistor array substrate 10.

For example, the display driving circuit 31 may supply a data signal to the data line DL (see, for example, fig. 4) of the transistor array substrate 10 and a first driving power to the first power line VDL (see, for example, fig. 4) of the transistor array substrate 10. In addition, the display driving circuit 31 may supply a scan control signal to the gate driver 33 embedded in the transistor array substrate 10 (for example, see fig. 4).

The display driving circuit 31 may be provided as an Integrated Circuit (IC).

The integrated circuit chip of the display driving circuit 31 may be directly mounted on the transistor array substrate 10 in a Chip On Glass (COG) manner, a Chip On Plastic (COP) manner, and/or an ultrasonic bonding manner. In this case, as shown in fig. 2, the integrated circuit chip of the display driving circuit 31 may be disposed in an area of the transistor array substrate 10 that is not covered by the cover substrate 20.

Alternatively, an integrated circuit chip of the display driving circuit 31 may be mounted on the circuit board 32.

The circuit board 32 may include an anisotropic conductive film. The circuit board 32 may be a flexible printed circuit board, a printed circuit board, and/or a flexible film such as a chip-on-film.

The circuit board 32 may be attached to electrode pads (also referred to as "pads" or "lands") of the transistor array substrate 10. Accordingly, the leads of the circuit board 32 may be electrically connected to the electrode pads of the transistor array substrate 10.

Fig. 4 is a layout diagram illustrating an example of a circuit layer of the transistor array substrate of fig. 3.

Referring to fig. 4, the transistor array substrate 10 may include a display area DA in which light for displaying an image is emitted and a non-display area NDA, which is a peripheral area of the display area DA, around an edge or periphery of the display area DA. The non-display area NDA may be an area from an edge of the display area DA to an edge of the substrate 11 (see, for example, fig. 3).

The transistor array substrate 10 includes sub-pixels PX arranged in a matrix shape in the display area DA along the longitudinal direction and the transverse direction. Each of the sub-pixels PX may be a unit that individually displays brightness and color.

The non-display area NDA may include a display pad area DPA disposed adjacent to an edge of the substrate 11. The transistor array substrate 10 may further include signal pads SPD disposed in the display pad region DPA of the non-display region NDA.

The circuit board 32 may be attached to the display pad area DPA of the transistor array substrate 10 and electrically connected to the signal pads SPD.

The transistor array substrate 10 further includes a line disposed in the display area DA and supplying a signal or power to the plurality of sub-pixels PX. The lines of the transistor array substrate 10 may include a scan gate line SGL, a data line DL, and a first power line VDL.

The scan gate line SGL may extend in the first direction DR 1.

The data line DL may extend in a second direction DR2 crossing the first direction DR 1.

The first power line VDL may extend in one of the first direction DR1 and the second direction DR 2. As an example, the first power line VDL may extend in the second direction DR2 like the data line DL.

Optionally, the circuit layer 12 (see fig. 3, for example) may further include a first power auxiliary line extending in a direction crossing the first power line VDL and electrically connected to the first power line VDL to reduce an RC delay of the supply of the first power due to a resistance of the first power line VDL.

The scan gate line SGL transmits a scan signal for controlling whether to transmit a data signal to the sub-pixel PX.

The scan gate line SGL may be connected to a gate driver 33 disposed in a portion of the non-display area NDA of the transistor array substrate 10.

The gate driver 33 may be electrically connected to at least one of the signal pads SPD or the display driving circuit 31 through at least one gate control power supply line GLSPL.

The gate driver 33 may apply a scan signal to the scan gate line SGL based on a gate control signal supplied through at least one gate control power line GLSPL, gate level power (gate level power), or the like.

As shown in fig. 4, the gate driver 33 is disposed in a portion of the non-display area NDA adjacent to one side (i.e., the left side of fig. 4) of the display area DA in the first direction DR 1. However, this is only an example, and the gate driver 33 may be disposed in another portion of the non-display area NDA adjacent to the right side of the display area DA. Alternatively, the gate driver 33 may be disposed at both sides of the display area DA in the left-right direction.

The data line DL is electrically connected between the display driving circuit 31 and the sub-pixel PX, and transmits a data signal output from the display driving circuit 31 to the sub-pixel PX.

The display driving circuit 31 may be electrically connected to some of the signal pads SPD through the data link lines DLL. That is, the display driving circuit 31 may be electrically connected to the circuit board 32 through the data link lines DLL and some of the signal pads SPD.

The circuit board 32 may supply digital video data corresponding to the image signal and the timing signal to the display driving circuit 31.

The circuit layer 12 (see, for example, fig. 3) may further include first power lines VDL extending from the non-display area NDA to the display area DA, and each of the first power lines VDL transmitting a first power ELVDD (see, for example, fig. 5) for driving the light emitting element EMD (see, for example, fig. 5), and a second power line VSL (see, for example, fig. 5) transmitting a second power ELVSS (see, for example, fig. 5) for driving the light emitting element EMD. Here, the second power ELVSS may have a voltage level lower than that of the first power ELVDD.

Each of the first and second power supply lines VDL and VSL may be electrically connected to at least one of the signal pads SPD or the display driving circuit 31.

The circuit layer 12 includes pixel drivers PXD (see, for example, fig. 5), each of which corresponds to a sub-pixel PX, and is electrically connected to the scan gate line SGL, the data line DL, and the first power line VDL.

Fig. 5 is an equivalent circuit diagram showing an example of one pixel driver corresponding to one sub-pixel of the transistor array substrate of fig. 4.

Referring to fig. 5, one of the pixel drivers PXD of the transistor array substrate 10 is electrically connected to one of the light emitting elements EMD of the light emitting element layer 13. That is, one pixel driver PXD may be electrically connected to the anode electrode AND of one light emitting element EMD (for example, see fig. 7), AND may supply a driving current corresponding to the data signal VDATA of the data line DL.

One light emitting element EMD may be an Organic Light Emitting Diode (OLED) including a light emitting layer made of an organic material. Alternatively, one light emitting element EMD may include a light emitting layer made of an inorganic material. Alternatively, the light emitting element EMD may be a quantum dot light emitting element including a quantum dot light emitting layer. Alternatively, the light emitting element EMD may be a micro light emitting diode.

One pixel driver PXD may include one or more thin film transistors T1, T2, and T3.

As an example, one pixel driver PXD may include a first thin film transistor T1, a second thin film transistor T2, and a third thin film transistor T3. In addition, one pixel driver PXD may further include a pixel capacitor PC.

The first thin film transistor T1 is connected in series to the light emitting element EMD between the first power line VDL and the second power line VSL. That is, a first electrode (e.g., a source electrode) of the first thin film transistor T1 may be electrically connected to the first power supply line VDL, AND a second electrode (e.g., a drain electrode) of the first thin film transistor T1 may be electrically connected to the anode electrode AND of the light emitting element EMD.

The cathode electrode CTD (see, for example, fig. 7) of the light emitting element EMD may be electrically connected to the second power line VSL.

In addition, the gate electrode of the first thin film transistor T1 may be electrically connected to the second thin film transistor T2 via the first node N1.

The second thin film transistor T2 may be electrically connected between the data line DL and the gate electrode of the first thin film transistor T1, and may be turned on based on the scan signal SCS of the scan gate line SGL.

That is, when the scan signal SCS is applied to the second thin film transistor T2 through the scan gate line SGL, the second thin film transistor T2 may be turned on, and the data line DL and the gate electrode of the first thin film transistor T1 may be electrically connected to each other. In this case, the data signal VDATA of the data line DL may be supplied to the pixel capacitor PC and the gate electrode of the first thin film transistor T1 through the turned-on second thin film transistor T2 and the first node N1.

When a voltage difference between the gate electrode and the first electrode of the first thin film transistor T1 becomes greater than a threshold voltage, the first thin film transistor T1 may be turned on. That is, when the data signal VDATA is applied to the first thin film transistor T1 through the first node N1, a voltage difference between the gate electrode and the first electrode of the first thin film transistor T1 becomes greater than the threshold voltage by the first power ELVDD and a voltage corresponding to the data signal VDATA, so that the first thin film transistor T1 may be turned on. In this case, the current Ids between the first electrode and the second electrode of the first thin film transistor T1 is supplied as the driving current of the light emitting element EMD. In addition, the magnitude of the current Ids between the first electrode and the second electrode of the first thin film transistor T1 corresponds to the data signal VDATA. That is, the current Ids corresponding to the data signal VDATA is supplied to the light emitting element EMD, and thus, the light emitting element EMD can emit light having a luminance corresponding to the data signal VDATA.

The pixel capacitor PC may be electrically connected between the first node N1 and the second node N2. The first node N1 is a contact point between the gate electrode of the first thin film transistor T1 and the second thin film transistor T2. The second node N2 is a contact point between the first thin film transistor T1 and the light emitting element EMD.

Due to this arrangement of the pixel capacitor PC, the potential difference between the gate electrode and the second electrode of the first thin film transistor T1 can be maintained until the potential of the first node N1 changes according to the data signal VDATA.

The third thin film transistor T3 may be electrically connected between the initialization voltage line VIL and the second node N2. The gate electrode of the third thin film transistor T3 may be electrically connected to the initialization gate line IGL.

That is, when the initialization control signal ICS is applied to the third thin film transistor T3 through the initialization gate line IGL, the third thin film transistor T3 may be turned on, and the initialization voltage line VIL and the second node N2 may be electrically connected to each other. In this case, the initialization voltage VINT of the initialization voltage line VIL may be supplied to the anode electrode AND of the light emitting element EMD through the second node N2 AND the turned-on third thin film transistor T3. Therefore, the potential of the anode electrode AND can be initialized to the initialization voltage VINT.

Fig. 5 shows that the pixel driver PXD has a 3T1C structure including a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, and one pixel capacitor PC, but this is only an example. That is, the structure of the pixel driver PXD according to one or more embodiments is not limited to the 3T1C structure shown in fig. 5, and may be changed to a structure different from that shown in fig. 5 if necessary. As an example, the pixel driver PXD may further include a thin film transistor for initializing the potential of the first node N1.

In addition, fig. 5 illustrates a case where one or more thin film transistors T1, T2, and T3 included in the pixel driver PXD are formed as N-type Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), but this is only an example. That is, at least one of the one or more thin film transistors T1, T2, and T3 included in the pixel driver PXD may also be a P-type MOSFET.

Fig. 6 is a plan view illustrating a first example of a first thin film transistor of the pixel driver of fig. 5. Fig. 7 is a sectional view taken along line B-B' of fig. 6.

Referring to fig. 6 and 7, the first thin film transistor T1 included in one of the pixel drivers PXD of the circuit layer 12 of the transistor array substrate 10 according to one or more embodiments includes an active layer ACT and a gate electrode GE, a first electrode ELE1 and a second electrode ELE2 disposed on the substrate 11, the gate electrode GE, the first electrode ELE1 and the second electrode ELE2 being formed as an electrode conductive layer ELCDL on the gate insulating layer GI covering the active layer ACT.

When one pixel driver PXD further includes the second and third thin film transistors T2 and T3 as shown in fig. 5, the second and third thin film transistors T2 and T3 are substantially the same or similar to the first thin film transistor T1 shown in fig. 6 and 7, and thus, repetitive description thereof will be omitted hereinafter.

For reference, in the following description, the first thin film transistor T1 of fig. 6 and 7 may be simply referred to as a thin film transistor T1.

In addition, in the following description of fig. 6 to 26, the first direction DR1 may be referred to as a direction in which each of the first electrode ELE1 and the second electrode ELE2 faces each other with the gate electrode GE, or an extending direction of the active layer ACT, and the second direction DR2 may be referred to as a direction crossing the first direction DR1, or an extending direction of the gate electrode GE. That is, the first direction DR1 and the second direction DR2 in fig. 6 to 26 may be the same as the first direction DR1 and the second direction DR2 in fig. 1 to 4, respectively, but may also be different from the first direction DR1 and the second direction DR2 in fig. 1 to 4, respectively, depending on the structure of the active layer ACT.

As shown in fig. 6, the active layer ACT includes a channel region CHA, a first conductive region COA1 connected to one side of the channel region CHA, and a second conductive region COA2 connected to the other side of the channel region CHA.

The channel region CHA of the active layer ACT overlaps the gate electrode GE in a third direction DR3 (e.g., a thickness direction of the substrate 11). Since the channel region CHA is in a state where it is covered with the gate insulating layer GI disposed under the gate electrode GE, the semiconductor characteristics of the channel region CHA can be maintained. Accordingly, a channel which is a moving channel of carriers can be selectively generated in the channel region CHA according to the potential of the gate electrode GE.

The first conductive region COA1 of the active layer ACT may correspond to a first electrode connection hole ECH1 (e.g., see fig. 7) penetrating the gate insulating layer GI. That is, the first conductive region COA1 is exposed to the etching material or the like through the first electrode connection hole ECH1 such that the oxygen content or the hydrogen content in the first conductive region COA1 is reduced or increased as compared to the channel region CHA, and thus, the first conductive region COA1 may be in a state in which it becomes conductive.

Similarly, the second conductive region COA2 of the active layer ACT may correspond to a second electrode connection hole ECH2 (see, e.g., fig. 7) penetrating the gate insulating layer GI. That is, the second conductive region COA2 is exposed to the etching material or the like through the second electrode connection hole ECH2 such that the oxygen content or the hydrogen content in the second conductive region COA2 is reduced or increased as compared to the channel region CHA, and thus, the second conductive region COA2 may be in a state in which it becomes conductive.

According to one or more embodiments, the electrode conductive layer ELCDL on the gate insulating layer GI covering a portion of the active layer ACT includes a gate electrode GE, a first electrode ELE1, and a second electrode ELE2. In this way, the number of mask processes required to provide the thin film transistor T1 can be reduced.

As described above, according to one or more embodiments, the first thin film transistor T1 further includes the first via THH1 penetrating a portion of the first conductive region COA1 and the second via THH2 penetrating a portion of the second conductive region COA2 due to the manufacturing process having the reduced number of mask processes.

The first electrode ELE1 is adjacent to one side of the first through hole THH1, and one side of the first electrode ELE1 adjacent to the first through hole THH1 is parallel to one side of the first through hole THH 1.

In addition, the first electrode ELE1 may extend toward the first conductive region COA1 to contact the first contact region COA11 of the first conductive region COA1. Accordingly, the first electrode ELE1 is electrically connected to the first conductive region COA1.

In addition, as described above, a portion of the first conductive region COA1 is removed through the first via THH 1.

Accordingly, the first conductive region COA1 may include a first contact region COA11 contacting the first electrode ELE1, a first via region COA12 disposed between one side of the first via THH1 and the first contact region COA11, and a first main region COA13 disposed between the channel region CHA and the first via region COA 12.

Since the first contact region COA11 is in contact with the first electrode ELE1, the first via region COA12 is disposed between the first through hole THH1 and the first electrode ELE 1.

The first via THH1 has a smaller width than that of the first conductive region COA1, and thus, other portions of the edge of the first via THH1 except for one side of the edge of the first via THH1 adjacent to the first electrode ELE1 may be in contact with the first main region COA 13.

That is, in the first direction DR1 in which the gate electrode GE and the first electrode ELE1 face (e.g., oppose) each other, one side (right side of fig. 6) of the first through hole THH1 is adjacent to the first electrode ELE1 and is in contact with the first via region COA 12. In addition, the other side (left side of fig. 6) of the first through hole THH1 in the first direction DR1 may be in contact with the first main area COA 13.

In the second direction DR2 intersecting the first direction DR1, both sides (upper and lower sides in fig. 6) of the first through hole THH1 may be in contact with the first main area COA 13.

The side of the first electrode ELE1 of the first thin film transistor T1 disposed in parallel with the first through hole THH1 according to one or more embodiments includes a protrusion portion PRO disposed at both ends thereof in the second direction DR2 and a groove portion GRO concavely recessed from the gate electrode GE as compared with the protrusion portion PRO.

In this way, the side of the first through hole THH1 and the side of the first electrode ELE1 facing each other are parallel to each other, and thus, the length of the first passage area COA12 between the first electrode ELE1 and the first through hole THH1 may not be limited to a length within the width of the first through hole THH1 due to the groove portion GRO of the first electrode ELE 1. As a result, the resistance between the first electrode ELE1 and the first conductive region COA1 may be reduced, and thus the current characteristics of the first thin film transistor T1 may be improved. This will be described in detail below with reference to fig. 8.

The second electrode ELE2 is adjacent to one side of the second through hole THH2, and one side of the second electrode ELE2 adjacent to the second through hole THH2 is parallel to one side of the second through hole THH 2.

The second electrode ELE2 may extend to the second conductive region COA2 to contact the second contact region COA21 of the second conductive region COA2. Accordingly, the second electrode ELE2 is electrically connected to the second conductive region COA2.

A portion of the second conductive region COA2 is removed through the second via THH2, and thus, the second conductive region COA2 may include a second contact region COA21 contacting the second electrode ELE2, a second via region COA22 disposed between one side of the second via THH2 and the second contact region COA21, and a second main region COA23 disposed between the channel region CHA and the second via region COA 22.

In addition, the second electrode ELE2 may be symmetrical to the first electrode ELE1 with respect to the gate electrode GE.

That is, similar to the first electrode ELE1, a side of the second electrode ELE2 adjacent to the second through hole THH2 may include a protrusion portion PRO and a groove portion GRO.

As shown in fig. 6 and 7, the first and second conductive regions COA1 and COA2 of the active layer ACT correspond to the first and second electrode connection holes ECH1 and ECH2, respectively. Accordingly, the active layer ACT may further include first and second inactive areas IAA1 and IAA2 due to an arrangement margin of the first and second electrode connection holes ECH1 and ECH 2.

The first inactive area IAA1 is connected to the first contact area COA11 of the first conductive area COA1 and is covered by the gate insulating layer GI. The first inactive area IAA1 may overlap the first electrode ELE1 in the third direction DR 3.

The second inactive area IAA2 is connected to the second contact area COA21 of the second conductive area COA2 and is covered by the gate insulating layer GI. The second inactive area IAA2 may overlap the second electrode ELE2.

The circuit layer 12 of the transistor array substrate 10 according to one or more embodiments may further include a light blocking electrode LSE included in the light blocking conductive layer LSCDL on the substrate 11 and overlapped with the active layer ACT, and a buffer layer 121 disposed on the substrate 11 and covering the light blocking conductive layer LSCDL. For example, the buffer layer 121 may be disposed between the light blocking conductive layer LSCDL and the active layer ACT.

In addition, the circuit layer 12 may further include an interlayer insulating layer 122 and a via layer 123 disposed on the interlayer insulating layer 122, the interlayer insulating layer 122 being disposed on the buffer layer 121 and covering the gate electrode GE, the first electrode ELE1, and the second electrode ELE2 of the thin film transistor T1.

The first and second through holes THH1 and THH2 of the first thin film transistor T1 penetrate portions of the first and second conductive regions COA1 and COA2 of the active layer ACT that are not covered by the gate insulating layer GI, and thus, the interlayer insulating layer 122 may contact the buffer layer 121 through the first and second through holes THH1 and THH 2.

The substrate 11 may be made of an insulating material such as a polymer resin. For example, the substrate 11 may be made of polyimide. The substrate 11 may be a flexible substrate that can be bent, folded, and rolled.

Alternatively, the substrate 11 may be made of a rigid insulating material such as glass.

Each of the buffer layer 121, the gate insulating layer GI, and the interlayer insulating layer 122 may be formed as at least one inorganic film. As an example, each of the buffer layer 121, the gate insulating layer GI, and the interlayer insulating layer 122 may be formed as a plurality of films in which two or more inorganic films of a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a titanium oxide film, and an aluminum oxide film are alternately stacked.

Alternatively, the interlayer insulating layer 122 may be formed as an organic film made of acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

The via layer 123 may be disposed on the interlayer insulating layer 122 flat. Such a via layer 123 may be formed as an organic film made of acrylic resin, epoxy resin, phenol resin, polyamide resin, polyimide resin, or the like.

The light blocking conductive layer LSCDL on the substrate 11 may be formed as a single layer or a plurality of layers made of one or more selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and/or an alloy thereof.

As an example, the light blocking conductive layer LSCDL may have a double layer structure including a diffusion blocking layer and a low resistance layer. The diffusion barrier layer of the light blocking conductive layer LSCDL may be made of titanium (Ti). In addition, the low resistance layer of the light blocking conductive layer LSCDL may be made of copper (Cu).

The light blocking conductive layer LSCDL may further include a first power supply line VDL.

In addition, in one or more embodiments, the light blocking conductive layer LSCDL may further include at least one of a data line DL and an initialization voltage line VIL.

The light blocking electrode LSE overlaps the active layer ACT, and blocks light from the substrate 11 toward the active layer ACT.

Alternatively, the light blocking electrode LSE may overlap only a portion of the active layer ACT including at least the channel region CHA in the third direction DR 3.

Due to such a light blocking electrode LSE, leakage current of the active layer ACT can be prevented.

The active layer ACT may be disposed on the buffer layer 121 covering (e.g., overlapping) the light blocking conductive layer LSCDL.

The active layer ACT may be made of one or more semiconductor materials selected from among polycrystalline silicon, amorphous silicon, and oxide semiconductor.

The gate insulating layer GI is disposed on the buffer layer 121 and covers a portion of the active layer ACT.

The electrode conductive layer ELCDL on the gate insulating layer GI may be formed to include a single layer or a plurality of layers including one or more selected from molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu) and/or an alloy thereof.

As an example, the electrode conductive layer ELCDL may be formed as a plurality of layers including a diffusion barrier layer, a low resistance layer, and a capping layer. The diffusion barrier layer of the electrode conductive layer ELCDL may include titanium (Ti). The low resistance layer of the electrode conductive layer ELCDL may include at least one selected from aluminum (Al), chromium (Cr), gold (Au), nickel (Ni), neodymium (Nd), and copper (Cu). The cover layer of the electrode conductive layer ELCDL may be made of Indium Tin Oxide (ITO) to prevent corrosion and easily bond the signal pads SPD thereto.

The electrode conductive layer ELCDL is disposed on the gate insulating layer GI, and includes a gate electrode GE, a first electrode ELE1, and a second electrode ELE2.

In addition, the electrode conductive layer ELCDL may further include at least one of a scan gate line SGL, a first power line VDL, and an initialization gate line IGL.

The first electrode ELE1 of the first thin film transistor T1 may be electrically connected to the first power line VDL through a power connection hole VDCH penetrating the gate insulating layer GI and the buffer layer 121.

The anode electrode AND of the light emitting element layer 13 disposed on the via layer 123 may be electrically connected to the second electrode ELE2 of the first thin film transistor T1 through the anode contact hole ANCH penetrating the interlayer insulating layer 122 AND the via layer 123.

In addition, the second electrode ELE2 of the first thin film transistor T1 may be electrically connected to the light blocking electrode LSE through the light blocking connection hole LSCH penetrating the gate insulating layer GI and the buffer layer 121. Therefore, the potential of the second node N2 between the first thin film transistor T1 and the light emitting element EMD can be stably maintained.

The transistor array substrate 10 according to one or more embodiments may include a light emitting element layer 13 disposed on the via layer 123 of the circuit layer 12.

The light emitting element layer 13 includes light emitting elements EMD each corresponding to a subpixel PX, and the light emitting elements EMD may correspond to a light emitting area EA, and the non-light emitting area NEA may surround the light emitting area EA. One of the light emitting elements EMD may include anode AND cathode electrodes AND CTD facing each other (e.g., opposite) AND a light emitting layer EML interposed between the anode AND cathode electrodes AND CTD AND made of a photoelectric conversion material.

The light emitting element layer 13 may further include a pixel defining layer PDL covering an edge of the anode electrode AND.

The transistor array substrate 10 according to one or more embodiments may further include a sealing layer 14 disposed on the light emitting element layer 13.

The sealing layer 14 may have a structure in which at least one inorganic film and at least one organic film are alternately stacked. As an example, the sealing layer 14 may include a first inorganic layer 141, an organic layer 142, and a second inorganic layer 143, the first inorganic layer 141 being disposed on the light emitting element layer 13 and made of an inorganic insulating material, the organic layer 142 being disposed on the first inorganic layer 141 and made of an organic insulating material, the second inorganic layer 143 being disposed over the organic layer 142, covering the organic layer 142, and made of an inorganic insulating material.

Fig. 8 is an enlarged view illustrating a portion C of fig. 6.

Referring to fig. 8, the thin film transistor T1 according to one or more embodiments includes a first via THH1 penetrating a portion of the first conductive region COA1 connected to one side of the channel region CHA, and a first electrode ELE1 formed as an electrode conductive layer ELCDL on the gate insulating layer GI and extending toward the first conductive region COA1 to be adjacent to one side of the first via THH 1.

The first conductive region COA1 may include a first contact region COA11 contacting the first electrode ELE1, a first via region COA12 between the first contact region COA11 and the first via THH1, and a first main region COA13 between the first via region COA12 and the channel region CHA.

In the second direction DR2 intersecting the first direction DR1 in which the first electrode ELE1 and the gate electrode GE face each other, the width of the active layer ACT (i.e., the width W21 of the first conductive region COA 1) is greater than the width W22 of the first via THH 1. That is, the first via THH1 may penetrate the central portion of the first conductive region COA1, and may be surrounded by the first conductive region COA 1.

One side of the edge of the first through hole THH1 in the first direction DR1 may be in contact with the first via area COA12, and the other side of the edge of the first through hole THH1 in the first direction DR1 and both sides of the edge of the first through hole THH1 in the second direction DR2 may be in contact with the first main area COA 13.

In this case, the portion of the first main area COA13 that contacts both sides of the first through hole THH1 in the second direction DR2 may have a width W23 within the same or similar range. In this way, the current concentration around the first via THH1 can be reduced.

When a channel is created in the channel region CHA, carriers CP move between the first conductive region COA1 and the second conductive region COA 2.

In this case, carriers CP moving within the first conductive region COA1 may flow from the first main region COA13 to the first contact region COA11 through the first via region COA12 to reach the first electrode ELE1.

Therefore, the width, thickness, length, etc. of the first via region COA12 affect the mobility of the thin film transistor T1.

Since the first via area COA12 is disposed between the first electrode ELE1 and the first through hole THH1, the width of the first via area COA12 may be limited to the interval between the first electrode ELE1 and the first through hole THH 1.

Since the first conductive region COA1 of the thin film transistor T1 is made of a semiconductor material that becomes conductive, the thickness of the first via region COA12 may be limited by process conditions or the like in a process of making the semiconductor material conductive.

In addition, the length of the first via area COA12 may correspond to the length of a portion of the edge of the first electrode ELE1 adjacent to the first through hole THH 1.

That is, the length of the first via area COA12 in the second direction DR2 may correspond to the width W22 of the first through hole THH1 in the second direction DR 2.

In addition, the shape of the side (left side of fig. 8) of the first electrode ELE1 adjacent to the first through hole THH1 may affect the length of the first via area COA 12.

As such, according to one or more embodiments, in order to increase the length of the first via area COA12, the side of the first electrode ELE1 adjacent to the first through hole THH1 in the first direction DR1 (left side of fig. 8) includes the protruding portions PRO provided at both ends thereof in the second direction DR2 and the groove portions GRO concavely recessed compared to the protruding portions PRO.

In this way, the length of the first passage area COA12 (for example, the length in the second direction DR 2) may become larger than the width W22 of the first through hole THH1 in the second direction DR2 by a difference proportional to the width W12 of the groove portion GRO in the first direction DR 1. That is, the length of the first via area COA12 may not be limited to the length within the width W22 of the first through hole THH1 in the second direction DR 2.

That is, the length of the first via area COA12 can be derived as the sum of the width W22 of the first through hole THH1 in the second direction DR2 and twice the width W12 of the groove portion GRO in the first direction DR 1.

The groove portion GRO of the first electrode ELE1 overlaps the first contact area COA 11. For this reason, the maximum width W11 of the first contact area COA11 may be larger than the width W12 of the groove portion GRO in the first direction DR 1.

That is, in the first direction DR1, the width W13 of the portion of the first contact area COA11 overlapping the groove portion GRO may be derived as a difference between the maximum width W11 of the first contact area COA11 and the width W12 of the groove portion GRO. As an example, in view of the etching margin, the width W13 of the portion of the first contact region COA11 overlapping the groove portion GRO may be 0.5 μm or more.

On a side of the first electrode ELE1 adjacent to the first through hole THH1 in the first direction DR1, the protrusion portion PRO and the groove portion GRO may be arranged along the second direction DR 2.

The protrusions PRO may be provided at both ends of one side of the first electrode ELE1 in the first direction DR1, respectively.

The groove portions GRO may be provided between the protruding portions PRO.

For this reason, the width W24 of the groove portion GRO in the second direction DR2 may be equal to or smaller than 1/2 of the width W22 of the first through hole THH1 in the second direction DR 2. As an example, when the width W22 of the first through hole THH1 in the second direction DR2 is about 4 μm, the width W24 of the groove portion GRO in the second direction DR2 may be about 2 μm.

In addition, the width W24 of the groove portion GRO in the second direction DR2 may be about 1 μm or more in view of the etching margin.

In addition, the groove portion GRO may be provided at the center of one side of the first electrode ELE1 in the first direction DR 1. Accordingly, in the second direction DR2, the protruding portion PRO may have a width W25 within the same or similar range.

The second electrode ELE2 is symmetrical to the first electrode ELE1 with respect to the gate electrode GE, and thus, a repetitive description will be omitted.

Fig. 9 is a plan view showing a comparative example different from the example of fig. 6. Fig. 10 is an enlarged view illustrating a portion D of fig. 9.

Referring to fig. 9 and 10, a side of each of the first electrode ELE1 'and the second electrode ELE2' of the thin film transistor REF according to the comparative example facing the gate electrode GE is formed in a straight line shape.

As such, according to the comparative example, the length of the first via area COA12 'is limited to the length within the width W22 of the first through hole THH1' in the second direction DR 2.

In addition, the length of the second passage area COA22 'is limited to a length within the width W22 of the second through holes THH2' in the second direction DR 2.

Therefore, in the case of the comparative example REF, the resistance decrease and the mobility improvement may not be deduced from the length of the first via area COA12 'and the length of the second via area COA 22'.

On the other hand, as shown in fig. 6 and 8, in the thin film transistor T1 according to one or more embodiments, a side of each of the first electrode ELE1 and the second electrode ELE2 facing the gate electrode GE is formed in an uneven shape including the protrusion portion PRO and the groove portion GRO, and thus, the length of the first via region COA12 and the length of the second via region COA22 may increase due to the width of the groove portion GRO.

Accordingly, the resistance of the thin film transistor T1 may be reduced, and thus the mobility of the thin film transistor T1 may be increased, so that the current characteristics of the thin film transistor T1 may be improved and the uniformity of the current characteristics of the thin film transistor T1 may be improved.

In addition, since uniformity of current characteristics of the thin film transistor T1 included in the transistor array substrate 10 is improved, a luminance difference between the sub-pixels PX can be improved, and thus display quality of the display device 1 can be improved.

Fig. 6 and 7 show a first example in which one groove portion GRO is included on the side opposite to the gate electrode GE of each of the first electrode ELE1 and the second electrode ELE 2. However, the thin film transistor T1 according to one or more embodiments is not limited to the thin film transistor shown in fig. 6 and 7.

Fig. 11 is a plan view illustrating a second example of the first thin film transistor of the pixel driver of fig. 5.

Referring to fig. 11, in the thin film transistor T12 (including the first and second through holes THH12 and THH 22) according to one or more embodiments, a side of each of the first and second electrodes ELE12 and ELE22 facing the gate electrode GE may include two or more groove portions GRO and an intermediate protrusion MPRO disposed between the groove portions GRO. The second example is substantially the same as the first example shown in fig. 6 to 8 except that the number of groove portions GRO is plural, and thus a repetitive description will be omitted.

Here, two or more groove portions GRO may have the same width in the first direction DR 1.

In this way, the mobility characteristics of the thin film transistor T12 can be easily predicted.

In addition, two or more groove portions GRO may have the same width W242 in the second direction DR 2. The protrusions PRO at both ends may have the same width W252 in the second direction DR 2.

In this way, the intermediate protrusion MPRO may be disposed at the center of each of the first electrode ELE12 and the second electrode ELE22 in the second direction DR2, and thus, a process error may be reduced.

The width W27 of the middle projection MPRO in the second direction DR2 may be different from the width W252 of the projections PRO at both ends in the second direction DR 2.

The width W27 of the intermediate projection MPRO in the second direction DR2 may be about 1 μm or more in view of the etching margin.

When one side of each of the first electrode ELE12 and the second electrode ELE22 includes two or more groove portions GRO as in the second example, the length of the first via area COA12 and the length of the second via area COA22' may be further increased, and thus, the mobility of the thin film transistor may be more easily improved.

According to the first example and the second example shown in fig. 6 and 11, the edge of the groove portion GRO has a curved shape. However, the shape of the groove portion GRO according to one or more embodiments is not limited to the shape shown in fig. 6 and 11.

Fig. 12 is a plan view showing a third example of the first thin film transistor of the pixel driver of fig. 5.

Referring to fig. 12, the first thin film transistor T13 (including the first through hole THH13 and the second through hole THH 23) of the third example is substantially the same as the first thin film transistor T1 of the first example shown in fig. 6 to 8 except that the groove portion CGRO provided on one side of each of the first electrode ELE13 and the second electrode ELE23 has a curved arc shape, and thus, a repetitive description will be omitted hereinafter.

According to the third example, since the groove portions CGRO between the protruding portions PRO are formed in a curved shape, the width of the curved portion decreases toward the center in the second direction DR2 from both sides in each of the first passage area COA12 and the second passage area COA22, and thus, the current concentration in the curved portion can be reduced. Therefore, the current characteristics and heat generation of the thin film transistor T13 can be improved. In this embodiment, since the groove portion CGRO has a curved arc shape and a portion of the protrusion portion PRO faces the first through hole THH13 in the first direction DR1, the length of the first passage area COA12 corresponds to the arc length of the groove portion CGRO and the width of the portion of the protrusion portion PRO in the second direction DR 2.

Fig. 13 is a flowchart illustrating a method of manufacturing a transistor array substrate in accordance with one or more embodiments. Fig. 14 to 26 are diagrams showing processes related to the respective steps of fig. 13, wherein fig. 24 to 26 are cross-sectional views corresponding to a section line B-B' in fig. 23 in the respective steps.

Referring to fig. 13, a method of manufacturing a transistor array substrate 10 according to one or more embodiments may include the steps of: disposing a light blocking conductive layer LSCDL on the substrate 11 (S11); providing a buffer layer 121 covering the light blocking conductive layer LSCDL (S12); disposing a semiconductor material layer SEM (see, for example, fig. 14 and 15) on the buffer layer 121 (S13); providing a gate insulating layer GI covering the semiconductor material layer SEM (S14); a first auxiliary hole PECH1 and a second auxiliary hole PECH2 penetrating the gate insulating layer GI are provided (see fig. 17) (S15); disposing an electrode conductive layer ELCDL on the gate insulating layer GI (S16); an active layer ACT including a channel region CHA, a first conductive region COA1, and a second conductive region COA2 is provided by partially removing the gate insulating layer GI (S17); an interlayer insulating layer 122 covering the electrode conductive layer ELCDL is provided and a via layer 123 is provided on the interlayer insulating layer 122 (S18); an anode contact hole ANCH penetrating the interlayer insulating layer 122 and the via layer 123 is provided (S21); a light emitting element layer 13 is provided on the via layer 123 (S22); and providing a sealing layer 14 covering the light emitting element layer 13 (S31).

Referring to fig. 14 and 15, a light blocking conductive layer LSCDL including a light blocking electrode LSE and a first power line VDL may be provided by partially removing the conductive layer on the substrate 11 (S11).

The light blocking conductive layer LSCDL may further include a data line DL and an initialization voltage line VIL.

Then, the buffer layer 121 covering the light blocking conductive layer LSCDL including the light blocking electrode LSE and the first power line VDL may be provided by stacking an insulating material on the substrate 11 (S12).

Then, a semiconductor material layer SEM may be disposed on the buffer layer 121 (S13).

Then, a gate insulating layer GI covering the semiconductor material layer SEM may be provided by stacking an inorganic insulating material on the buffer layer 121 and the semiconductor material layer SEM (S14).

Referring to fig. 16 and 17, a power connection hole VDCH and a light blocking connection hole LSCH penetrating the gate insulating layer GI and the buffer layer 121, and first and second auxiliary holes PECH1 and PECH2 penetrating the gate insulating layer GI may be provided using a halftone mask (S15).

The power connection hole VDCH may expose a portion of the first power line VDL.

The light blocking connection hole LSCH may expose a portion of the light blocking electrode LSE.

The first auxiliary hole PECH1 and the second auxiliary hole PECH2 may expose different portions of the semiconductor material layer SEM, respectively.

The portion of the semiconductor material layer SEM exposed through the first auxiliary hole PECH1 is exposed to the etching process to become conductive, and thus may be provided as a first pre-conductive region PCOA1.

Another portion of the semiconductor material layer SEM exposed through the second auxiliary hole PECH2 is exposed to the etching process to become conductive, and thus may be provided as a second pre-conductive region PCOA2.

To ensure the etching margin, the first auxiliary hole PECH1 and the second auxiliary hole PECH2 may be spaced apart from both ends of the semiconductor material layer SEM, respectively.

Accordingly, a first inactive area IAA1 (see, for example, fig. 6) adjacent to the first auxiliary hole PECH1 may be disposed at one end of the semiconductor material layer SEM, and a second inactive area IAA2 (see, for example, fig. 6) adjacent to the second auxiliary hole PECH2 may be disposed at the other end of the semiconductor material layer SEM.

Referring to fig. 18, a conductive material layer covering the semiconductor material layer SEM and the gate insulating layer GI may be deposited by stacking a conductive material on the buffer layer 121, and then a photo mask layer PM may be disposed on the conductive material layer.

Referring to fig. 19 and 20, an electrode conductive layer ELCDL including a gate electrode GE, a first electrode ELE1, and a second electrode ELE2 may be provided by partially etching the conductive material layer based on the photomask layer PM (S16).

The gate electrode GE overlaps a portion of the semiconductor material layer SEM in the third direction DR3 and is spaced apart from each of the first and second pre-conductive regions PCOA1 and PCOA 2.

The first electrode ELE1 overlaps the power supply connection hole VDCH and extends to the first pre-conductive area PCOA1 to overlap a portion of the first pre-conductive area PCOA 1.

The second electrode ELE2 overlaps the light blocking connection hole LSCH and extends to the second pre-conductive region PCOA2 to overlap a portion of the second pre-conductive region PCOA 2.

As shown in fig. 19, according to one or more embodiments, a side of each of the first electrode ELE1 and the second electrode ELE2 facing the gate electrode GE includes a protrusion portion PRO and a groove portion GRO.

As shown in fig. 21 and 22, the first auxiliary hole PECH1 may be extended to the first electrode connection hole ECH1 and the second auxiliary hole PECH2 may be extended to the second electrode connection hole ECH2 by partially etching the gate insulating layer GI based on the photomask layer PM.

In this case, the first conductive region COA1 and the second conductive region COA2 formed of different portions of the semiconductor material layer SEM may be provided by the first electrode connection hole ECH1 and the second electrode connection hole ECH2, respectively.

Accordingly, an active layer ACT including a channel region CHA, a first conductive region COA1, and a second conductive region COA2 may be provided (S17).

The active layer ACT may further include a first inactive area IAA1 and a second inactive area IAA2, the first inactive area IAA1 being connected to the first conductive area COA1, covered by the gate insulating layer GI, and overlapping the first electrode ELE1 in the third direction DR3, and the second inactive area IAA2 being connected to the second conductive area COA2, covered by the gate insulating layer GI, and overlapping the second electrode ELE2 in the third direction DR 3.

In addition, in the process (S17) of partially etching the gate insulating layer GI based on the photomask layer PM, a portion of the first pre-conductive region PCOA1 and a portion of the second pre-conductive region PCOA2 are not covered by the photomask layer PM, and may be exposed to and removed through the etching process. That is, the first and second through holes THH1 and THH2 are generated.

Then, as shown in fig. 23 and 24, the photo mask layer PM may be removed, and then an interlayer insulating layer 122 and a via layer 123 covering the electrode conductive layer ELCDL including the gate electrode GE, the first electrode ELE1, and the second electrode ELE2 may be sequentially disposed on the buffer layer 121 (S18).

Then, an anode contact hole ANCH penetrating the interlayer insulating layer 122 and the via layer 123 and exposing a portion of the second electrode ELE2 of the first thin film transistor T1 may be provided (S21).

As shown in fig. 25, the light emitting element layer 13 may be disposed on the via layer 123 (S22).

The light emitting element layer 13 may include an anode electrode electrically connected to the first thin film transistor T1 through the anode contact hole ANCH, a pixel defining layer PDL disposed at a portion between the anode electrodes AND of the sub-pixels PX spaced apart from each other, a light emitting layer EML disposed on the anode electrode AND, AND a cathode electrode CTD disposed on the light emitting layer EML.

The anode electrode AND may be a pixel electrode corresponding to each of the sub-pixels PX. The anode electrode AND may reflect at least a portion of the light generated from the light emitting layer EML.

The cathode electrode CTD may be a common electrode corresponding to the sub-pixel PX as a whole. The cathode electrode CTD may transmit at least a portion of light generated in the light emitting layer EML therethrough.

The emission layer EML may be disposed in each of the sub-pixels PX. Alternatively, when the display device 1 includes a color filter member or a color conversion member or displays a single color, the light emitting layer EML may be equally disposed in the sub-pixel PX as a whole.

Then, the sealing layer 14 may be provided on the light emitting element layer 13 (S31).

Thus, a transistor array substrate 10 according to one or more embodiments may be provided.

As described above, the method of manufacturing the transistor array substrate 10 according to one or more embodiments includes providing the electrode conductive layer ELCDL including the gate electrode GE, the first electrode ELE1, and the second electrode ELE2 (S16), and thus, the number of mask processes may be reduced.

In addition, a side of each of the first electrode ELE1 and the second electrode ELE2 facing the gate electrode GE includes a groove portion GRO concavely recessed from the gate electrode GE. Accordingly, the length of the first via area COA12 and the length of the second via area COA22 are increased, so that the resistance of the thin film transistor T1 can be reduced, and thus, the current characteristics and the uniformity of the current characteristics of the thin film transistor T1 can be improved.

However, aspects and features of the present disclosure are not limited to the aspects and features set forth herein. The above and other aspects and features of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referencing the claims, wherein functional equivalents thereof are included.

Claims

1. A thin film transistor, the thin film transistor comprising:

an active layer including a channel region, a first conductive region connected to one side of the channel region, and a second conductive region connected to the other side of the channel region;

A gate insulating layer on a portion of the active layer;

a first via penetrating a portion of the first conductive region;

a second via penetrating a portion of the second conductive region;

a gate electrode in the electrode conductive layer on the gate insulating layer and overlapping the channel region of the active layer;

a first electrode in the electrode conductive layer adjacent to one side of the first via hole and electrically connected to the first conductive region; and

a second electrode in the electrode conductive layer adjacent to one side of the second via hole and electrically connected to the second conductive region,

wherein a side of the first electrode adjacent to the first through hole is parallel to the side of the first through hole, the first electrode including a protrusion at both ends thereof and a groove portion concavely recessed from the gate electrode as compared with the protrusion.

2. The thin film transistor of claim 1, wherein the first conductive region corresponds to a first electrode connection hole penetrating the gate insulating layer,

wherein the second conductive region corresponds to a second electrode connection hole penetrating the gate insulating layer,

wherein the first electrode extends to the first conductive region and is in contact with a first contact region of the first conductive region, and

Wherein the second electrode extends to the second conductive region and is in contact with a second contact region of the second conductive region.

3. The thin film transistor of claim 2, wherein a length of a first via region in the first conductive region between the one side of the first via and the first contact region is greater than a width of the one side of the first via.

4. The thin film transistor according to claim 3, wherein a side of the second electrode adjacent to the second via hole is parallel to the side of the second via hole and symmetrical to the first electrode with respect to the gate electrode, the second electrode includes a protrusion portion and a groove portion, and

wherein a length of a second via region located between the one side of the second via hole and the second contact region in the second conductive region is greater than a width of the one side of the second via hole.

5. The thin film transistor of claim 4, wherein the first conductive region further comprises a first main region between the channel region and the first via region, and

wherein the second conductive region further comprises a second main region between the channel region and the second via region.

6. The thin film transistor according to claim 5, wherein a maximum width of the first contact region is larger than a width of the groove portion in a first direction in which the first electrode and the gate electrode face each other.

7. The thin film transistor according to claim 6, wherein a difference between the maximum width of the first contact region and the width of the groove portion in the first direction is 0.5 μm or more.

8. The thin film transistor of claim 6, wherein the width of the first conductive region is greater than the width of the first via in a second direction intersecting the first direction, and

wherein an edge of the first through hole is in contact with the first via area on one side in the first direction, and the other side of the edge of the first through hole and the two sides of the edge of the first through hole in the second direction are in contact with the first main area.

9. The thin film transistor according to claim 8, wherein a width of the groove portion in the second direction is equal to or less than 1/2 of a width of the first via hole in the second direction.

10. The thin film transistor according to claim 9, wherein the width of the groove portion in the second direction is 1 μm or more.

11. The thin film transistor according to claim 8, wherein the length of the first via region corresponds to a sum of the width of the first via in the second direction and twice the width of the groove portion in the first direction.

12. The thin film transistor of claim 8, wherein the one side of the first electrode further comprises an intermediate protrusion between two or more groove portions.

13. The thin film transistor according to claim 12, wherein a width of the intermediate protrusion in the second direction is 1 μm or more.

14. The thin film transistor according to claim 8, wherein the groove portion has a curved arc shape,

wherein a portion of the protrusion faces the first through hole in the first direction, and

wherein the length of the first passage region corresponds to an arc length of the groove portion and a width of the portion of the protrusion portion in the second direction.

15. The thin film transistor of claim 2, wherein the active layer further comprises:

A first inactive region connected to the first contact region of the first conductive region and covered by the gate insulating layer; and

and a second inactive area connected to the second contact area of the second conductive area and covered by the gate insulating layer.

16. A transistor array substrate, the transistor array substrate comprising:

a substrate including a display region in which sub-pixels are arranged; and

a circuit layer on the substrate and including pixel drivers, each of the pixel drivers corresponding to a sub-pixel of the sub-pixels,

wherein each of the pixel drivers includes at least one thin film transistor, and

wherein the thin film transistor of the circuit layer includes:

an active layer on the substrate and including a channel region, a first conductive region connected to one side of the channel region, and a second conductive region connected to the other side of the channel region;

a gate insulating layer on a portion of the active layer;

a first via penetrating a portion of the first conductive region;

a second via penetrating a portion of the second conductive region;

17. The transistor array substrate of claim 16, wherein the first conductive region corresponds to a first electrode connection hole penetrating the gate insulating layer,

wherein the first electrode extends to the first conductive region and contacts a first contact region of the first conductive region,

wherein the second electrode extends to the second conductive region and contacts a second contact region of the second conductive region,

Wherein a length of a first via region located between the one side of the first via and the first contact region in the first conductive region is greater than a width of the one side of the first via,

wherein a side of the second electrode adjacent to the second via is parallel to the side of the second via and symmetrical to the first electrode with respect to the gate electrode, and includes a protrusion portion and a groove portion, and

18. The transistor array substrate of claim 17, wherein the first conductive region further comprises a first main region between the channel region and the first via region,

wherein a maximum width of the first contact region is larger than a width of the groove portion in a first direction in which the first electrode and the gate electrode face each other,

wherein the width of the first conductive region is larger than the width of the first via hole in a second direction crossing the first direction, and

19. The transistor array substrate of claim 18, wherein the length of the first via region corresponds to a sum of the width of the first via in the second direction and twice the width of the groove portion in the first direction.

20. The transistor array substrate of claim 17, wherein the active layer further comprises:

21. The transistor array substrate of claim 17, further comprising: a light emitting element layer on the via layer of the circuit layer,

wherein the light emitting element layer includes: a light emitting element electrically connected to the corresponding pixel driver through an anode contact hole penetrating the via layer and the interlayer insulating layer,

Wherein the circuit layer further comprises: a scan gate line for transmitting a scan signal to the pixel driver; a data line for transmitting a data signal to the pixel driver; and an initialization voltage line for transmitting an initialization voltage to the pixel driver, an

Wherein the pixel driver among the pixel drivers includes:

a first thin film transistor connected to a light emitting element among the light emitting elements connected in series between a first power line and a second power line for transmitting a first power source and a second power source for driving the light emitting element;

a second thin film transistor electrically connected between the data line and a gate electrode of the first thin film transistor and configured to be turned on based on the scan signal of the scan gate line;

a pixel capacitor electrically connected to a first node between the gate electrode of the first thin film transistor and the second thin film transistor and a second node between the first thin film transistor and the light emitting element; and

and a third thin film transistor electrically connected between the initialization voltage line and the second node and configured to be turned on based on an initialization control signal of the initialization gate line.

22. The transistor array substrate of claim 21, wherein the circuit layer further comprises:

a light blocking electrode in the light blocking conductive layer on the substrate and overlapped with the active layer;

a buffer layer on the substrate and covering the light blocking conductive layer;

an interlayer insulating layer on the buffer layer and covering the thin film transistor; and

a via layer on the interlayer insulating layer,

wherein the interlayer insulating layer is in contact with the buffer layer through each of the first and second via holes.

23. The transistor array substrate of claim 22, wherein the first power line is in the light blocking conductive layer,

wherein the first electrode of the first thin film transistor is electrically connected to the first power line through a power connection hole penetrating the gate insulating layer and the buffer layer, and

wherein the second electrode of the first thin film transistor is electrically connected to the light blocking electrode through a light blocking connection hole penetrating the gate insulating layer and the buffer layer.