CN117854565A - Antifuse circuit, structure, array, programming method and memory - Google Patents

Antifuse circuit, structure, array, programming method and memory Download PDF

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Publication number
CN117854565A
CN117854565A CN202211204511.6A CN202211204511A CN117854565A CN 117854565 A CN117854565 A CN 117854565A CN 202211204511 A CN202211204511 A CN 202211204511A CN 117854565 A CN117854565 A CN 117854565A
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China
Prior art keywords
antifuse
gate
transistor
region
voltage
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CN202211204511.6A
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Chinese (zh)
Inventor
侯闯明
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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Priority to CN202211204511.6A priority Critical patent/CN117854565A/en
Priority to PCT/CN2022/127090 priority patent/WO2024065909A1/en
Publication of CN117854565A publication Critical patent/CN117854565A/en
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/16—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM using electrically-fusible links
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/14—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
    • G11C17/18—Auxiliary circuits, e.g. for writing into memory
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
    • G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/20—Programmable ROM [PROM] devices comprising field-effect components
    • H10B20/25—One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

The present disclosure relates to the field of semiconductors, and more particularly, to an antifuse circuit, structure, array, programming method, and memory, the antifuse circuit comprising: an antifuse, a select transistor, and a clamp capacitor, a first end of the antifuse configured to receive a programming signal; the gate of the select transistor is configured to receive a select signal, and the first pole of the select transistor is configured to receive a bit line voltage; the first end of the clamping capacitor is configured to receive a preset voltage; a second terminal of the antifuse, a second pole of the select transistor, and a second terminal of the clamp capacitor are coupled to each other; the clamp capacitor is added between the anti-fuse and the selection transistor, and due to the potential clamping function of the clamp capacitor, the abrupt rise of the potential of the second end of the anti-fuse is avoided when the anti-fuse is programmed, namely the voltage difference between the two ends of the anti-fuse is maintained, and the successful writing of the anti-fuse is ensured when the width of the selection transistor device is reduced.

Description

Antifuse circuit, structure, array, programming method and memory
Technical Field
The present disclosure relates to the field of semiconductors, and more particularly, to an antifuse circuit, structure, array, programming method, and memory.
Background
An antifuse memory (Anti-fuse) may be implemented by an array of antifuse memory cells, where a gate oxide dielectric of the antifuse memory cells breaks down after a high voltage is applied, and the resistance of the via decreases after breakdown; the information stored in the antifuse memory cell can be read by detecting the state of the via resistance after breakdown.
For example, an antifuse (AF cell) and a selection transistor (XADD) are included in the Anti-fuse cell. When data writing is performed, high voltage (for example, about 5.5-6V) is applied to the grid electrode of the AF cell, 0V is arranged at the end of the corresponding Bit Line (BL), and XADD is started, so that the thin grid oxide of the AF cell is broken down under high voltage, the resistance is obviously reduced, and the writing purpose is achieved.
To reduce the chip size, the area of the Anti-fuse array needs to be reduced, and thus the device width of XADD needs to be reduced. However, when the device width of XADD is small, the channel resistance of the XADD device increases. When the drain current of the AF cell is increased during data writing, when the width of the XADD device is small, the partial voltage of the XADD device starts to be increased, so that the voltage difference between two ends of the AF cell is small, the energy for breaking through the oxide of the AF cell is weakened, and the AF cell is difficult to write.
Disclosure of Invention
The embodiment of the disclosure provides an antifuse circuit, a structure, an array, a programming method and a memory, so as to improve the write success rate of an AF cell when the device width of XADD is reduced.
An embodiment of the present disclosure provides an antifuse circuit, including: an antifuse, a select transistor, and a clamp capacitor, a first end of the antifuse configured to receive a programming signal; the gate of the select transistor is configured to receive a select signal, and the first pole of the select transistor is configured to receive a bit line voltage; the first end of the clamping capacitor is configured to receive a preset voltage; the second terminal of the antifuse, the second pole of the select transistor, and the second terminal of the clamp capacitor are coupled to one another.
With the antifuse circuit provided in this embodiment, the clamp capacitor is added between the antifuse and the select transistor, so that a steep rise in the potential of the second terminal of the antifuse is avoided when programming the antifuse due to the potential clamping action of the clamp capacitor, that is, a voltage difference across the antifuse is maintained, and successful writing to the antifuse is ensured when the width of the select transistor device is reduced; in addition, the clamp capacitor is also used for stabilizing the potential of the second end of the anti-fuse, and the stabilizing of the potential of the second end of the anti-fuse is beneficial to reducing energy impact to the selection transistor device and the related bit line circuit.
In addition, the clamp capacitor includes: the MOS transistor is in a conducting state under the control of a preset voltage, the conducting MOS transistor is used as an MOS capacitor to form the clamping capacitor, the device size of the MOS transistor is smaller than the device size of the capacitor, and the MOS capacitor formed by the MOS transistor can greatly reduce the size of an anti-fuse circuit, thereby being beneficial to further miniaturization of the anti-fuse circuit.
In addition, the MOS transistor comprises a depletion type MOS transistor, and the gate of the depletion type NMOS can be turned on after receiving a small voltage, and the depletion type NMOS is used as a clamping capacitor to reduce the voltage value of a preset voltage required to be provided, so that the power consumption of the antifuse circuit is reduced.
In addition, the preset voltage is zero voltage, the grid electrode of the MOS transistor is coupled with the grounding end to receive the preset voltage, and by setting the preset voltage to be zero voltage, the depletion type MOS transistor is conducted, and the power consumption of the anti-fuse circuit is reduced.
In addition, the MOS transistor includes a single gate transistor or a double gate transistor.
Another embodiment of the present disclosure also provides an antifuse structure including: an active region and an antifuse cell disposed over the active region, the antifuse cell including a clamp capacitor, and an antifuse and a select transistor respectively located on opposite sides of the clamp capacitor; the clamp capacitor comprises an initial channel region positioned in the active region, and a first dielectric layer and a first grid electrode which are sequentially stacked on the initial channel region; the antifuse comprises a first doped region in the active region, and a second dielectric layer and a second gate which are sequentially stacked on one side of the first doped region away from the first gate; the selection transistor comprises a second doped region and a third doped region which are positioned in the active region, and a third dielectric layer and a third grid electrode which are sequentially stacked between the second doped region and the third doped region; the first doped region and the second doped region are positioned on two opposite sides of the first grid electrode.
In addition, the first doped region, the initial channel region and the second doped region are formed as one integrated doped region to simplify the formation of the antifuse structure.
In addition, polar ions are doped in the first dielectric layer, so that the clamp capacitor is formed based on the depletion type NMOS, and because the grid electrode of the depletion type NMOS can be opened after receiving small voltage, the voltage value of the preset voltage required to be provided is reduced by taking the depletion type NMOS as the clamp capacitor, and therefore the power consumption of the antifuse circuit is reduced.
In addition, the initial channel region comprises a first initial sub-channel region and a second initial sub-channel region which are arranged at intervals, the first grid electrode comprises a first sub-grid electrode positioned on the first initial sub-channel region and a second sub-grid electrode positioned on the second initial sub-channel region, and the first sub-grid electrode and the second sub-grid electrode are mutually coupled; the active region further includes a fourth doped region located between the first initial sub-channel region and the second initial sub-channel region.
In addition, the antifuse structure includes two antifuse cells symmetrically disposed over the active region, wherein the third doped regions of the select transistors of the two antifuse cells are formed as one integrated doped region.
Yet another embodiment of the present disclosure provides an antifuse array, including: the plurality of antifuse structures provided in the above-described embodiments arranged in an array.
In addition, the plurality of antifuse structures are arranged in an array along a first direction along which the active region extends, and a second direction different from the first direction.
In addition, the first gate of one row of antifuse cells arranged in the second direction is formed as a first gate line, the second gate of one row of antifuse cells arranged in the second direction is formed as a second gate line, and the third gate of one row of antifuse cells arranged in the second direction is formed as a third gate line.
In addition, the third doped regions of a column of antifuse structures arranged in a first direction are coupled to the same bit line.
Still another embodiment of the present disclosure further provides a programming method applied to the antifuse circuit provided in the above embodiment, including: applying a selection signal to a gate of the selection transistor to turn on the selection transistor, applying a preset voltage to a first terminal of the clamp capacitor, and applying a bit line voltage to a first pole of the selection transistor such that a potential of a second terminal of the antifuse is the bit line voltage; and applying a programming signal to the first terminal of the antifuse such that the first and second terminals of the antifuse are turned on to improve a write success rate of the AF cell when the device width of the XADD is reduced.
In addition, there is a time delay between the time node to which the programming signal is applied and the time node to which the selection signal is applied, the time delay being used to ensure that the potential of the second terminal of the antifuse is the bit line voltage.
In addition, the preset voltage is zero voltage.
Still another embodiment of the present disclosure further provides a memory including the antifuse circuit provided in the above embodiment, or the antifuse structure provided in the above embodiment, to improve the write success rate of the AF cell when the device width of XADD is reduced.
Drawings
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, which are not to be construed as limiting the embodiments unless specifically indicated otherwise; in order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the conventional technology, the drawings required for the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present disclosure, and other drawings may be obtained according to these drawings without inventive effort to those of ordinary skill in the art.
FIG. 1 is a schematic diagram of an antifuse circuit based on a clamp capacitor design according to an embodiment of the present disclosure;
fig. 2 is a schematic diagram of an antifuse circuit designed based on MOS transistors according to an embodiment of the present disclosure;
FIG. 3 is a schematic diagram of an antifuse circuit based on depletion NMOS design according to an embodiment of the present disclosure;
FIG. 4 is a schematic top view of an antifuse structure according to another embodiment of the present disclosure;
FIG. 5 is a schematic cross-sectional view of the antifuse structure of FIG. 4 in the AB direction;
FIG. 6 is a schematic cross-sectional view of a first doped region, an initial channel region and a second doped region in a common doped region according to another embodiment of the present disclosure;
fig. 7 is a schematic top view of a clamp capacitor based on a dual gate transistor according to another embodiment of the present disclosure;
FIG. 8 is a schematic cross-sectional view of the antifuse structure of FIG. 7 in the CD direction;
FIG. 9 is a schematic top view of an antifuse structure according to another embodiment of the present disclosure, including two antifuse cells arranged symmetrically;
FIG. 10 is a schematic diagram of an antifuse array formed when an antifuse structure according to another embodiment of the present disclosure includes an antifuse cell;
FIG. 11 is a schematic diagram of an antifuse array formed when an antifuse structure according to another embodiment of the present disclosure includes two antifuse cells;
fig. 12 is a schematic diagram of an antifuse array formed by forming a clamp capacitor based on a double-gate transistor according to another embodiment of the present disclosure.
Detailed Description
As is known from the background, the channel resistance of XADD devices increases when the device width of XADD is small. When the drain current of the AF cell is increased during data writing, when the width of the XADD device is small, the partial voltage of the XADD device starts to be increased, so that the voltage difference between two ends of the AF cell is small, the energy for breaking through the oxide of the AF cell is weakened, and the AF cell is difficult to write.
An embodiment of the present disclosure provides an antifuse circuit to improve the write success rate of an AF cell when the device width of XADD is reduced.
Those of ordinary skill in the art will understand that in various embodiments of the present disclosure, numerous technical details are set forth in order to provide a better understanding of the present disclosure. However, the technical solutions claimed in the present disclosure can be implemented without these technical details and with various changes and modifications based on the following embodiments. The following embodiments are divided for convenience of description, and should not be construed as limiting the specific implementation of the disclosure, and the embodiments can be combined with each other and cited with each other without contradiction.
Fig. 1 is a schematic structural diagram of an antifuse circuit based on a clamp capacitor design according to the present embodiment, fig. 2 is a schematic structural diagram of an antifuse circuit based on a MOS transistor design according to the present embodiment, fig. 3 is a schematic structural diagram of an antifuse circuit based on a depletion NMOS design according to the present embodiment, and the antifuse circuit according to the present embodiment is described in detail below with reference to the accompanying drawings, specifically as follows:
referring to fig. 1, an antifuse circuit includes:
antifuse 101, select transistor 102, and clamp capacitor 103, a first terminal of antifuse 101 is configured to receive a programming signal.
The programming signal is used to encode the antifuse 101, such that the corresponding antifuse 101 stores a data "1" or "0" by puncturing a dielectric layer (e.g., an oxide layer) of the antifuse 101; accordingly, when the dielectric layer of antifuse 101 is not broken down, antifuse 101 stores data "0" or "1".
The gate of the select transistor 102 is configured to receive a select signal and the first pole of the select transistor 102 is configured to receive a bit line voltage. In some embodiments, the bit line voltage may be zero voltage, but is not limited thereto.
The selection signal is used to select the target antifuse 101 from the antifuse array, and the corresponding selection transistor 102 receives the selection signal to conduct, so that the bit line voltage is transferred to the second terminal of the antifuse 101, and the bit line voltage forms a voltage difference at the programming signal, so that the dielectric layer of the corresponding antifuse 101 breaks down, and data writing of the antifuse 101 is completed.
The first terminal of the clamp capacitor 103 is configured to receive a preset voltage.
The second terminal of antifuse 101, the second pole of select transistor 102, and the second terminal of clamp capacitor 103 are coupled to one another.
For example, a selection signal is applied to the gate of the selection transistor 102 to turn on the selection transistor 102 such that the first pole and the second pole of the selection transistor 102 are electrically connected to each other, thereby transmitting a bit line voltage applied to the first pole of the selection transistor 102 to the second pole, and the second pole of the selection transistor is coupled to the second terminal of the antifuse 101 such that the potential of the second terminal of the antifuse 101 becomes the bit line voltage based on the conduction of the selection transistor 102; in programming antifuse 101, a programming signal is applied to a first terminal of antifuse 101, and since the first terminal of antifuse 101 receives the programming signal, the potential of the second terminal is the bit line voltage, and antifuse 101 breaks down a dielectric layer in antifuse 101 based on the voltage difference between the bit line voltage and the programming signal, so that the first terminal and the second terminal of antifuse are turned on, thereby programming antifuse 101.
For an antifuse memory cell, when the first and second terminals of the antifuse are turned on, i.e., the antifuse breaks down, the potential in the line is pulled down rapidly, so that the data read based on the read clock is low, i.e., data "1" or "0"; accordingly, when the first and second terminals of the antifuse are not turned on, i.e., the antifuse is not broken down, the circuit pull-down rate in the line is slow, so that the data read based on the read clock is high, i.e., data "0" or "1".
However, in the process of programming the antifuse 101, since the programming signal is a large voltage, the leakage current through the antifuse 101 increases, and when the device width of the selection transistor 102 decreases, the voltage division of the selection transistor 102 starts to increase, thereby raising the voltage at the second terminal of the antifuse 101, reducing the voltage difference between the first terminal and the second terminal of the antifuse 101, and affecting the success rate of writing of the antifuse 101.
With the antifuse circuit provided in this embodiment, the clamp capacitor 103 is added between the antifuse 101 and the select transistor 102, so that a steep rise of the potential at the second end of the antifuse 101 is avoided when programming the antifuse due to the potential clamping action of the clamp capacitor 103, that is, the voltage difference across the antifuse 101 is maintained, and successful writing to the antifuse 101 is ensured when the device width of the select transistor 102 is reduced; in addition, the clamp capacitor 103 is also used to stabilize the potential at the second terminal of the antifuse 101, which is advantageous in reducing the energy impact to the select transistor 102 device and associated bit line BL circuit.
Referring to fig. 2, in some embodiments, clamp capacitor 103 includes: a first electrode of the MOS transistor is coupled to the second terminal of the antifuse 101, a second electrode of the MOS transistor is coupled to the second electrode of the selection transistor 102, a gate of the MOS transistor is used as the first terminal of the clamp capacitor 103, a channel region of the MOS transistor is used as the second terminal of the clamp capacitor 103, and the MOS transistor is in a conductive state under the control of a preset voltage.
The clamp capacitor 103 is formed by using an on MOS transistor as a MOS capacitor, and for a memory, the device size of the MOS transistor is smaller than that of the capacitor, and the clamp capacitor 103 is formed by using the MOS capacitor formed by the MOS transistor, so that the size of the antifuse circuit can be greatly reduced, which is advantageous for further miniaturization of the antifuse circuit.
Referring to fig. 3, in some embodiments, the MOS transistor includes a depletion type MOS transistor, and since the gate of the depletion type NMOS (or PMOS) is turned on upon receiving a small voltage, the voltage value of the preset voltage to be supplied is reduced by using the depletion type NMOS (or PMOS) as the clamp capacitor 103, thereby reducing the power consumption of the antifuse circuit. It should be appreciated that in the case where the clamp capacitor is a MOS transistor, the conductivity type of the MOS transistor and the select transistor is typically the same, i.e., either NMOS or PMOS, to simplify the manufacturing process.
In some embodiments, the preset voltage is zero, i.e., the gate of the MOS transistor is coupled to the ground to receive the preset voltage, and by setting the preset voltage to zero, both the depletion MOS transistor is turned on and the power consumption of the antifuse circuit is reduced.
It should be noted that, in other embodiments, the MOS transistor may be implemented as an enhancement MOS transistor, and the preset voltage is a high voltage at this time, and the preset voltage may be provided by the internal power supply voltage of the memory, so as to ensure the turn-on of the MOS transistor.
In addition, with the clamp capacitor 103 mentioned above, whether it is formed based on a capacitor or a MOS transistor, the capacitance value of the clamp capacitor 103 should not be excessively large, otherwise more energy will be used to charge the capacitance, and the write success rate of the antifuse 101 is reduced. In practical applications, the capacitance value of the clamp capacitor 103 may be set as needed as long as it can improve the write success rate of the antifuse 101.
In conjunction with fig. 1-3, in some embodiments, the MOS transistor comprises a single gate transistor or a double gate transistor, i.e., the MOS transistor may be formed based on a single gate transistor or may be formed based on a double gate transistor.
It should be noted that the above description of the "clamp capacitor 103" focuses on describing how the clamp capacitor 103 is configured based on a MOS transistor, and in some embodiments, the clamp capacitor 103 may be formed directly based on a capacitive device.
With the antifuse circuit provided in this embodiment, the clamp capacitor 103 is added between the antifuse 101 and the select transistor 102, so that a steep rise of the potential at the second end of the antifuse 101 is avoided when programming the antifuse due to the potential clamping action of the clamp capacitor 103, that is, the voltage difference across the antifuse 101 is maintained, and successful writing to the antifuse 101 is ensured when the device width of the select transistor 102 is reduced; in addition, the clamp capacitor 103 is also used to stabilize the potential at the second terminal of the antifuse 101, which is advantageous in reducing the energy impact to the select transistor 102 device and associated bit line BL circuit.
It should be noted that the features disclosed in the antifuse circuit provided in the above embodiments may be arbitrarily combined without collision, and a new antifuse circuit embodiment may be obtained.
Another embodiment of the present disclosure provides an antifuse structure to improve the write success rate of an AF cell when the device width of XADD is reduced.
Fig. 4 is a schematic top view of an antifuse structure according to the present embodiment, fig. 5 is a schematic top view of the antifuse structure in the AB direction, fig. 6 is a schematic top view of a first doped region, an initial channel region and a second doped region, wherein the first doped region, the initial channel region and the second doped region share a doping region, fig. 7 is a schematic top view of a clamp capacitor based on a dual-gate transistor, fig. 8 is a schematic top view of the antifuse structure in the CD direction, fig. 9 is a schematic top view of the antifuse structure in the CD direction, and the antifuse structure in the CD direction includes two antifuse units symmetrically arranged, and the antifuse circuit in the present embodiment is described in detail with reference to the drawings, wherein:
referring to fig. 4 and 5, an antifuse structure comprising:
an active region 200 and an antifuse cell disposed over the active region 200, the antifuse cell including a clamp capacitor 203, and an antifuse 201 and a select transistor 202 located on opposite sides of the clamp capacitor 203, respectively.
The clamp capacitor 203 includes an initial channel region 213 located in the active region 200, and a first dielectric layer 223 and a first gate 233 sequentially stacked on the initial channel region 213.
The antifuse 201 includes a first doped region 211 in the active region 200, and a second dielectric layer 221 and a second gate 231 stacked in sequence on a side of the first doped region 211 remote from the first gate 233.
The selection transistor 202 includes a second doped region 212 and a third doped region 222 in the active region 200, and a third dielectric layer 232 and a third gate 242 stacked in sequence between the second doped region 212 and the third doped region 222.
Wherein the first doped region 211 and the second doped region 212 are located at opposite sides of the first gate 233.
For example, referring to fig. 5, as can be seen from the description of the above embodiment, the third doped region 222 is configured to receive the bit line voltage, when the third gate 242 receives the selection signal and is turned on, the third doped region 222 is electrically connected to the second doped region 212, so as to transmit the bit line voltage to the second doped region 212, and the clamp capacitor 203 (in the form of a structure similar to a MOS transistor, for example) is in a normally-on state based on a preset voltage, i.e., the initial channel region 213 is in a turned-on state, the second doped region 212 is electrically connected to the first doped region 211 through the initial channel region 213, so as to transmit the bit line voltage to the first doped region 211, and when the second gate 231 receives the programming signal, the voltage difference formed by the programming signal and the bit line voltage breaks down the second dielectric layer 221, so as to complete breakdown of the antifuse 201, i.e., complete data writing of the antifuse structure. In addition, because the clamping capacitor 203 clamps the potential of the first doped region 211, the potential of the first doped region 211 is prevented from rising sharply due to the sharp increase of the leakage current, so that the voltage difference between the programming signal and the bit line voltage is ensured to be enough to break down the second dielectric layer 221, and the writing success rate of the antifuse structure is improved.
Referring to fig. 5 in combination with fig. 6, in some embodiments, the first doped region 211, the initial channel region 213, and the second doped region 212 form one integrated doped region 204 to simplify the formation of the antifuse structure.
In some embodiments, the first dielectric layer 223 is doped with a polar ion, such as a cation (na+ or k+), or an anion, so that the clamp capacitor 203 is formed based on a depletion NMOS (or PMOS), and since the gate of the depletion NMOS (or PMOS) can be turned on after receiving a small voltage, the voltage value of the preset voltage to be provided is reduced by using the depletion NMOS (or PMOS) as the clamp capacitor 203, thereby reducing the power consumption of the antifuse circuit.
In some embodiments, the preset voltage is zero, i.e. the first gate 233 is coupled to the ground to receive the preset voltage, and by setting the preset voltage to zero, both the depletion type NMOS (or PMOS) is turned on and the power consumption of the antifuse circuit is reduced.
It should be noted that, in other embodiments, the clamp capacitor 203 may also be implemented by an enhancement MOS transistor, where the preset voltage is a high voltage, and the preset voltage may be provided by the internal power supply voltage of the memory, so as to ensure the turn-on of the enhancement MOS transistor.
Referring to fig. 7 and 8, in some embodiments, the clamp capacitor 203 is formed based on a dual gate transistor, for example, the initial channel region 213 includes a first initial sub-channel region 301 and a second initial sub-channel region 302 that are spaced apart, the first gate 233 includes a first sub-gate 301 located on the first initial sub-channel region 301 and a second sub-gate 320 located on the second initial sub-channel region 302, the first sub-gate 310 and the second sub-gate 320 are coupled to each other, and the active region 200 further includes a fourth doped region 304 located between the first initial sub-channel region 310 and the second initial sub-channel region 320.
For example, referring to fig. 8, as can be seen from the description of the above embodiment, the third doped region 222 is configured to receive the bit line voltage, when the third gate 242 receives the selection signal to be turned on, the third doped region 222 is electrically connected to the second doped region 212, so as to transmit the bit line voltage to the second doped region 212, the second doped region 212 transmits the bit line voltage to the second initial sub-channel region 302, the clamp capacitor 203 is in a normally open state based on the preset voltage, i.e. the initial channel region 213 is in a turned-on state, and accordingly, the first initial sub-channel region 301, the second initial sub-channel region 302 and the fourth doped region 304 are in a turned-on state, so as to transmit the bit line voltage to the first doped region 211, and when the second gate 231 receives the programming signal, the voltage difference between the programming signal and the bit line voltage breaks down to the second dielectric layer 221, thereby completing the breakdown of the antifuse 201, i.e. the data writing of the antifuse structure. In addition, because the clamping capacitor 203 clamps the potential of the first doped region 211, the voltage of the first doped region 211 is prevented from being rapidly increased due to leakage current, so that the voltage difference between the programming signal and the bit line voltage is ensured to be enough to break down the second dielectric layer 221, and the writing success rate of the antifuse structure is improved.
Referring to fig. 9 in conjunction with fig. 4, in some embodiments, the antifuse structure includes two antifuse cells symmetrically disposed over the active region 200, wherein the select transistors 202 of the two antifuse cells are formed as one integrated doped region in the third doped region 222, i.e., the select transistors 202 of the two antifuses share the third doped region 222.
It should be noted that, the structure shown in fig. 9 is an antifuse structure formed by symmetrically disposing antifuse cells shown in the structure of fig. 4, and in some embodiments, the antifuse structure may be formed based on the antifuse cell symmetrical disposition shown in fig. 7, which is not described in detail in this embodiment.
In addition, the above description of the "clamp capacitor 203" focuses on describing how the clamp capacitor 203 structure is constituted based on MOS transistors; in some embodiments, clamp capacitor 203 may be formed directly based on a capacitive device.
For the antifuse structure provided in this embodiment, because the clamping capacitor is used for clamping the potential of the first doped region 211, the voltage of the first doped region 211 is prevented from being increased sharply due to leakage current, so that the voltage difference between the programming signal and the bit line voltage is ensured to be enough to break down the second dielectric layer 221, and the writing success rate of the antifuse structure is improved.
It should be noted that the features disclosed in the antifuse structures provided in the foregoing embodiments may be arbitrarily combined without conflict, and a new antifuse structure embodiment may be obtained, for example, a scheme of forming an integrated doped region by the first doped region 211, the initial channel region 213, and the second doped region 212 shown in fig. 6 is applied to the scheme shown in fig. 7 or the scheme shown in fig. 9, or a scheme of forming a clamp capacitor based on a double gate transistor shown in fig. 8 is applied to the scheme shown in fig. 4 or the scheme shown in fig. 9.
Yet another embodiment of the present disclosure provides an antifuse array to improve the write success rate of an AF cell as the device width of XADD decreases.
Fig. 10 is a schematic structural view of an antifuse array formed when the antifuse structure provided in this embodiment includes one antifuse unit, fig. 11 is a schematic structural view of an antifuse array formed when the antifuse structure provided in this embodiment includes two antifuse units, and fig. 12 is a schematic structural view of an antifuse array formed when the clamp capacitor provided in this embodiment is formed based on a double-gate transistor, and the antifuse array provided in this embodiment is described in detail below with reference to the drawings, specifically as follows:
referring to fig. 10 to 12, the antifuse array includes: a plurality of antifuse structures provided according to the above-described embodiments are arrayed.
The plurality of antifuse structures are arranged in an array along a first direction and a second direction, and the active region 400 extends along the first direction, the second direction being different from the first direction.
In some embodiments, the first gates of a row of anti-fuse cells arranged in the second direction form a first gate line 402, the second gates of a row of anti-fuse cells arranged in the second direction form a second gate line 401, and the third gates of a row of anti-fuse cells arranged in the second direction form a third gate line 403.
In some embodiments, the third doped regions of a column of antifuse structures arranged in a first direction are coupled to the same bit line 404. For example, a third doped region in the antifuse structure is connected to bit line 404 through bit line contact 405.
It should be noted that, for the examples of fig. 10 to 12, the first direction is a longitudinal direction as shown in the drawing, and the second direction is a transverse direction as shown in the drawing, and in this embodiment, the first direction and the second direction are perpendicular to each other as shown in the drawing, so that those skilled in the art understand the arrangement of the antifuse array, and the present embodiment is not limited, and in a specific application, the antifuse array may be formed based on the antifuse structure by the difference between the extension directions of the first direction and the second direction.
With reference to fig. 10, in particular, for an antifuse array formed by the antifuse structures shown in fig. 4 to 6, the corresponding bit line 404 and the second gate line 401 are selected to select a target antifuse, and the first gate line 402 and the third gate line 403 corresponding to the second gate line 401 are selected to select an antifuse cell in which the target antifuse is located, thereby programming the target antifuse.
For the antifuse array formed by the antifuse structure shown in fig. 9, referring specifically to fig. 11, two antifuse cells are included in the antifuse structure, and the third doped regions between the two antifuse cells are connected to each other so as to connect the bit lines 404 through the same bit line contacts 405, and the antifuse structures arranged in the first direction connect the same bit lines 404, the two antifuse cells are disposed in the same antifuse structure to reduce the number of isolation structures to be disposed, thereby reducing the area of the antifuse array formed by the same number of antifuse memory cells. In some embodiments, a third doped region may be shared between two antifuse cells, further shrinking the size of the antifuse structure so that an antifuse array of the same layout area may accommodate more antifuse memory cells.
Accordingly, for the antifuse array shown in fig. 11, different antifuse structures may be provided in the same active region 400 as well, i.e., in the first direction, all of the antifuse structures are provided in the same active region, to further reduce the number of isolation structures that need to be provided to reduce the area of the antifuse array formed by the same number of antifuse memory cells.
For the antifuse structures shown in fig. 7 and 8, and referring to fig. 12 in particular, the antifuse structure includes two antifuse cells, and the clamp capacitor in each antifuse cell is configured based on a double-gate transistor, where a first sub-gate arranged in the second direction forms a first sub-gate line 412, a second sub-gate arranged in the second direction forms a second sub-gate line 422, and the same parts as those in fig. 11 are not described here; in the example of fig. 12, the antifuse array further includes a connection line 406 extending in a first direction for connecting the first sub-gate line 412 and the second sub-gate line 422 arranged in the first direction, the first sub-gate line 412 and the second sub-gate line 422 being coupled to the connection line 406 through respective contact points, and the preset voltage being transmitted to all of the first sub-gate line 412 and the second sub-gate line 422 in the antifuse array by transmitting the preset voltage to the connection line 406.
In some embodiments, the first sub-gate line 412 and the second sub-gate line 422 are connected to form a ring gate on both sides of the antifuse array and the second inversion, and the connection line 406 is disposed on top of the connection portion of the first sub-gate line 412 and the second sub-gate line 422, so that the contact point is reduced, and the formation process of the antifuse array is simplified.
It should be noted that the features disclosed in the antifuse array provided in the foregoing embodiments may be arbitrarily combined without collision, so as to obtain a new antifuse array embodiment, for example: the connection line 406 shown in fig. 12 is applied to the scheme of fig. 10 or 11, or the dual gate transistor structure shown in fig. 12 is applied to the scheme of fig. 10.
Yet another embodiment of the present disclosure provides a programming method applied to the antifuse circuit provided in the above embodiment, so as to improve the write success rate of the AF cell when the device width of XADD is reduced.
For the programming method provided in this embodiment, the programming method includes: applying a selection signal to a gate of the selection transistor to turn on the selection transistor, applying a preset voltage (e.g., a fixed voltage) to a first terminal of the clamp capacitor, and applying a bit line voltage to a first pole of the selection transistor such that a potential of a second terminal of the antifuse is the bit line voltage; and applying a programming signal to the first terminal of the antifuse such that the first and second terminals of the antifuse are conductive.
For example, a selection signal is applied to a gate of the selection transistor to turn on the selection transistor such that a first pole and a second pole of the selection transistor are electrically connected to each other, thereby transmitting a bit line voltage applied to the first pole of the selection transistor to the second pole, and the second pole of the selection transistor is coupled to a second terminal of the antifuse such that a potential of the second terminal of the antifuse becomes a bit line voltage based on the conduction of the selection transistor; in the process of programming the antifuse, a programming signal is applied to the first end of the antifuse, and because the first end of the antifuse receives the programming signal, the potential of the second end is the bit line voltage, and the antifuse breaks down a dielectric layer in the antifuse based on the voltage difference between the bit line voltage and the programming signal, so that the first end and the second end of the antifuse are conducted, and programming of the antifuse is achieved.
For an antifuse memory cell, when the first and second terminals of the antifuse are turned on, i.e., the antifuse breaks down, the potential in the line is pulled down rapidly, so that the data read based on the read clock is low, i.e., data "1" or "0"; accordingly, when the first and second terminals of the antifuse are not turned on, i.e., the antifuse is not broken down, the circuit pull-down rate in the line is slow, so that the data read based on the read clock is high, i.e., data "0" or "1".
However, in the process of programming the antifuse, since the programming signal is a large voltage, the leakage current through the antifuse increases, and when the device width of the select transistor decreases, the voltage division of the select transistor starts to increase, thereby raising the voltage at the second end of the antifuse, reducing the voltage difference between the first end and the second end of the antifuse, and affecting the success rate of writing of the antifuse.
For the programming method and the anti-fuse circuit provided by the embodiment, the second end of the anti-fuse is also connected with the clamping capacitor, and a preset voltage is applied to the first end of the clamping capacitor before the anti-fuse is programmed, the clamping capacitor prevents the second end of the anti-fuse from rising sharply based on the potential clamping function of the capacitor when the anti-fuse is programmed, so that the voltage difference between the first end and the second end of the anti-fuse in the process of programming the anti-fuse is ensured, namely the success rate of breakdown of the anti-fuse based on a programming signal is ensured.
In some embodiments, there is a time delay between the time node at which the programming signal is applied and the time node at which the select signal is applied, the time delay being used to ensure that the potential of the second terminal of the antifuse is the bit line voltage.
Based on the above discussion, when the select signal is applied to turn on the select transistor, the second end of the antifuse receives the bit line voltage, which pulls down the potential of the second end of the antifuse, and by ensuring that the bit line voltage pulls down the antifuse for a time to ensure that the potential of the second end of the antifuse is the bit line voltage, the voltage difference between the first and second ends of the antifuse is greater when the programming signal is applied to the antifuse to start programming, so that programming of the antifuse is successfully completed.
In some embodiments, the preset voltage is zero voltage.
In some embodiments, the bit line voltage is zero to further increase the voltage difference between the programming signal and the bit line voltage received across the antifuse when programming the antifuse, thereby ensuring the success rate of writing to the antifuse.
Based on the above discussion, when the clamp capacitor is formed based on a MOS capacitor, the size of the antifuse circuit can be reduced; when the MOS capacitor is formed based on the depletion type NMOS (or PMOS), the depletion type NMOS (or PMOS) is also sufficiently conducted when the preset voltage is a small voltage, so that the power consumption of the anti-fuse circuit is reduced; in some embodiments, the preset voltage is set to zero, that is, the gate of the depletion NMOS (or PMOS) is coupled to the ground GND, so that the preset voltage received by the clamp capacitor is zero, and the power consumption of the antifuse circuit is further reduced.
It should be noted that, features disclosed in the programming method provided in the foregoing embodiments may be arbitrarily combined without conflict, so as to obtain a new programming method embodiment, for example: a scheme in which a time delay is provided between a time node to which a program signal is applied and a time node to which a selection signal is applied and a preset voltage is zero, or a scheme in which a time delay is provided between a time node to which a program signal is applied and a time node to which a selection signal is applied and a bit line voltage may be set to zero, or a scheme in which a preset voltage is zero and a bit line voltage may be set to zero.
Yet another embodiment of the present disclosure provides a memory including the antifuse circuit provided in the above embodiment, or the antifuse structure provided in the above embodiment, to improve the write success rate of the AF cell when the device width of XADD is reduced.
For example, a clamp capacitor is added between the antifuse and the select transistor, so that the abrupt rise of the potential of the second end of the antifuse is avoided when programming the antifuse due to the potential clamping action of the clamp capacitor, namely, the voltage difference across the antifuse is maintained, and the successful writing of the antifuse is ensured when the width of the select transistor device is reduced; in addition, the clamp capacitor is also used for stabilizing the potential of the second end of the anti-fuse, and the stabilizing of the potential of the second end of the anti-fuse is beneficial to reducing energy impact to the selection transistor device and the related bit line circuit.
In some embodiments, the memory may be a semiconductor device or component based memory cell or device. For example, the memory device may be a volatile memory such as dynamic random access memory DRAM, synchronous dynamic random access memory SDRAM, double data rate synchronous dynamic random access memory DDR SDRAM, low power double data rate synchronous dynamic random access memory LPDDR SDRAM, graphics double data rate synchronous dynamic random access memory GDDR SDRAM, double data rate type double synchronous dynamic random access memory DDR2SDRAM, double data rate type triple synchronous dynamic random access memory DDR3SDRAM, double data rate fourth generation synchronous dynamic random access memory DDR4SDRAM, thyristor random access memory TRAM, etc.; or may be a non-volatile memory such as a phase change random access memory PRAM, MRAM, resistive random access memory RRAM, etc.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific embodiments for carrying out the present disclosure, and that various changes in form and details may be made therein without departing from the spirit and scope of the present disclosure.

Claims (18)

1. An antifuse circuit, comprising:
an antifuse, a select transistor, and a clamp capacitor, a first end of the antifuse configured to receive a programming signal, a gate of the select transistor configured to receive a select signal, a first pole of the select transistor configured to receive a bit line voltage;
the first end of the clamping capacitor is configured to receive a preset voltage;
the second terminal of the antifuse, the second pole of the select transistor, and the second terminal of the clamp capacitor are coupled to one another.
2. The antifuse circuit of claim 1, wherein the clamp capacitor comprises: and a MOS transistor, wherein a first electrode of the MOS transistor is coupled with a second end of the antifuse, a second electrode of the MOS transistor is coupled with a second electrode of the selection transistor, a gate of the MOS transistor is used as a first end of the clamping capacitor, a channel region of the MOS transistor is used as a second end of the clamping capacitor, and the MOS transistor is in a conducting state under the control of the preset voltage.
3. The antifuse circuit of claim 2, wherein the MOS transistor comprises a depletion MOS transistor.
4. The antifuse circuit of claim 3, wherein the preset voltage is zero voltage.
5. The antifuse circuit of any of claims 2-4, wherein the MOS transistor comprises a single gate transistor or a double gate transistor.
6. An antifuse structure, comprising: an active region and an antifuse cell disposed over the active region, the antifuse cell including a clamp capacitor, and an antifuse and a select transistor respectively located on opposite sides of the clamp capacitor;
the clamping capacitor comprises an initial channel region positioned in the active region, and a first dielectric layer and a first grid electrode which are sequentially stacked on the initial channel region; the antifuse comprises a first doped region in the active region, and a second dielectric layer and a second gate which are sequentially stacked on one side of the first doped region away from the first gate; the selection transistor comprises a second doping region and a third doping region which are positioned in the active region, and a third dielectric layer and a third grid electrode which are sequentially stacked between the second doping region and the third doping region;
the first doped region and the second doped region are positioned on two opposite sides of the first grid electrode.
7. The antifuse structure of claim 6, wherein the first doped region, the initial channel region, and the second doped region are formed as one integrated doped region.
8. The antifuse structure of claim 6, wherein the first dielectric layer is doped with polar ions.
9. The antifuse structure of any of claims 6-8, wherein the initial channel region comprises first and second initial sub-channel regions arranged at intervals, the first gate comprising a first sub-gate located over the first initial sub-channel region and a second sub-gate located over the second initial sub-channel region, the first and second sub-gates being coupled to each other; the active region further includes a fourth doped region located between the first initial sub-channel region and the second initial sub-channel region.
10. The antifuse structure of any of claims 6-8, comprising two of the antifuse cells symmetrically disposed over the active region, wherein the third doped regions of the select transistors of two of the antifuse cells are formed as one integrated doped region.
11. An antifuse array, comprising: an array of a plurality of antifuse structures according to any of claims 6-10.
12. The antifuse array of claim 11, wherein the plurality of antifuse structures are arrayed in a first direction and a second direction, the active region extending in the first direction, the second direction being different from the first direction.
13. The antifuse array of claim 12, wherein a first gate of a row of the antifuse cells arranged in the second direction is formed as a first gate line, a second gate of a row of the antifuse cells arranged in the second direction is formed as a second gate line, and a third gate of a row of the antifuse cells arranged in the second direction is formed as a third gate line.
14. The array of claim 12 or 13, wherein the third doped regions of a column of the antifuse structures arranged in the first direction are coupled to a same bit line.
15. A programming method applied to the antifuse circuit of any one of claims 1 to 5, comprising: applying a selection signal to a gate of a selection transistor to turn on the selection transistor, applying a preset voltage to a first terminal of a clamp capacitor, and applying a bit line voltage to a first pole of the selection transistor such that a potential of a second terminal of the antifuse is the bit line voltage; and applying the programming signal to the first terminal of the antifuse such that the first and second terminals of the antifuse are conductive.
16. The programming method of claim 15, wherein there is a time delay between the time node at which the programming signal is applied and the time node at which the select signal is applied, the time delay being used to ensure that the potential of the second terminal of the antifuse is the bit line voltage.
17. A programming method according to claim 15 or 16, wherein the predetermined voltage is zero voltage.
18. A memory comprising an antifuse circuit according to any one of claims 1 to 5, or an antifuse structure according to any one of claims 6 to 10.
CN202211204511.6A 2022-09-29 2022-09-29 Antifuse circuit, structure, array, programming method and memory Pending CN117854565A (en)

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