CN117852494A - Logic simulation acceleration method and device for DFF optimization - Google Patents
Logic simulation acceleration method and device for DFF optimization Download PDFInfo
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Abstract
The application relates to a logic simulation acceleration method and device for DFF optimization, wherein the method comprises the following steps: if the current output value of the circuit gate is inconsistent with the last output value, adding an event generated by the circuit gate into an event queue; adding the fan-out gate into the event queue or the DFF identification queue according to the type of the fan-out gate corresponding to the circuit gate, wherein the fan-out gate refers to a directly subordinate module of the circuit gate; after the event processing in the event queue is completed, if the DFF identification queue is determined not to be empty, determining whether the DFF is a valid event according to the input port change information of the DFF in the DFF identification queue; and if the DFF is an effective event, adding the effective event in the DFF identification queue to the event queue, and processing the effective event. The simulation performance is improved.
Description
Technical Field
The application relates to the technical field of simulation, in particular to a logic simulation acceleration method and device aiming at DFF optimization.
Background
During the logic simulation, it was found that the number of events of DFF (D type flip-flop) is up to 90%, and the number of DFFs is about 20% of the entire circuit, in which a large number of ineffective computations may occur. The principle of the event driven algorithm is: if the input of a gate changes, the gate needs to be recalculated once, if the result obtained by the calculation is inconsistent with the result obtained by the previous calculation, the output of all gates after the gate needs to be recalculated, namely all fan-outs of the gate need to be added to an event queue, so that the events in the event queue are excessive, the simulation calculation time is long, and the simulation performance is reduced.
Disclosure of Invention
The application provides a logic simulation acceleration method and device aiming at DFF optimization, so as to solve the problem of low simulation performance.
In a first aspect, the present application provides a logic simulation acceleration method for DFF optimization, the method including: if the current output value of the circuit gate is inconsistent with the last output value, adding an event generated by the circuit gate into an event queue; adding the fan-out gate into the event queue or the DFF identification queue according to the type of the fan-out gate corresponding to the circuit gate, wherein the fan-out gate refers to a directly subordinate module of the circuit gate; after the event processing in the event queue is completed, if the DFF identification queue is determined not to be empty, determining whether the DFF is a valid event according to the input port change information of the DFF in the DFF identification queue; and if the DFF is an effective event, adding the effective event in the DFF identification queue to the event queue, and calculating the effective event.
Optionally, determining whether the DFF is a valid event according to input port variation information of the DFF in the DFF identification queue includes: if the Set port and Reset port of the DFF in the DFF identification queue are converted from the effective value to the ineffective value, acquiring the changes of the D end, the CLK end and the M end of the DFF; if the D terminal is changed and the CLK terminal is 0, or the M terminal is changed and the CLK terminal is 1, the DFF is determined to be valid.
Optionally, determining whether the DFF is a valid event according to input port variation information of the DFF in the DFF identification queue, and the method further includes: and if the Set port and the Reset port of the DFF in the DFF identification queue are converted from the invalid value to the valid value, determining that the DFF is valid.
Optionally, adding the fanout gate to the event queue or DFF identification queue according to the type of the fanout gate corresponding to the circuit gate includes: if the fan-out gate corresponding to the circuit gate is a DFF, adding the fan-out gate into the DFF identification queue, and recording the input port change information of the DFF; and if the fan-out gate corresponding to the circuit gate is not the DFF, adding the fan-out gate into the event queue.
Optionally, before determining that the current output value of the circuit gate and the last output value are inconsistent, the method further comprises: reading a netlist file through a netlist analyzer, and reading a vector file through a vector analyzer; extracting excitation data of a netlist from the vector file according to an input port and an output port of the netlist file, and recording the excitation data to an input port of a circuit gate at the forefront end in the netlist, wherein the netlist indicates a connection relationship among a plurality of circuit gates; taking the excitation data as an input value of the circuit gate; if the excitation data is inconsistent with the previous excitation data, the circuit gate is calculated again to obtain the current output value.
Optionally, when calculating the valid event, the method further includes: when the effective event is calculated, a Remove function interface of the DFF identification queue is called, and input port change information in the DFF identification queue associated with calculation is deleted; and if all the input port change information of the DFF is changed, deleting the DFF from the DFF identification queue.
Optionally, after calculating the valid event, the method further comprises: adding the calculated DFF to a tabu table, wherein the DFF in the tabu table can no longer be added to an event queue.
In a second aspect, the present application provides a logic simulation acceleration apparatus optimized for DFF, the apparatus comprising: the first adding module is used for adding an event generated by the circuit gate into the event queue if the current output value of the circuit gate is inconsistent with the last output value; the second joining module is used for joining the fan-out gate into the event queue or the DFF identification queue according to the type of the fan-out gate corresponding to the circuit gate, wherein the fan-out gate refers to a directly subordinate module of the circuit gate; the determining module is used for determining whether the DFF is a valid event according to the input port change information of the DFF in the DFF identification queue if the DFF identification queue is determined not to be empty after the event processing in the event queue is completed; and the processing module is used for adding the effective event in the DFF identification queue to the event queue if the DFF is the effective event, and processing the effective event.
In a third aspect, the present application provides an electronic device, including: at least one communication interface; at least one bus connected to the at least one communication interface; at least one processor coupled to the at least one bus; at least one memory coupled to the at least one bus.
In a fourth aspect, the present application further provides a computer storage medium storing computer executable instructions for performing the logic simulation acceleration method for DFF optimization described in any one of the above applications.
Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages: if the output value of the circuit gate is inconsistent with the last output value, all fan-out gates are not required to be added into the event queue, if the fan-out gates are DFFs, the fan-out gates are added into the event queue only when the DFF calculation is effective, namely, invalid calculation of the DFFs in the logic simulation process is reduced, the logic simulation time is shortened, and therefore simulation performance is improved.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments of the invention or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated.
FIG. 1 is a flowchart of a method for logic simulation acceleration for DFF optimization provided in an embodiment of the present application;
fig. 2 is a schematic diagram of a DFF identification queue provided in an embodiment of the present application;
fig. 3 is a schematic structural diagram of a DFF model according to an embodiment of the present application;
FIG. 4 is a flowchart of a logic simulation acceleration for DFF optimization provided by an embodiment of the present application;
fig. 5 is a schematic structural diagram of a logic simulation accelerator for DFF optimization according to an embodiment of the present application;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present application based on the embodiments herein.
The following disclosure provides many different embodiments, or examples, for implementing different structures of the invention. In order to simplify the present disclosure, components and arrangements of specific examples are described below. They are, of course, merely examples and are not intended to limit the invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
The application provides a logic simulation acceleration method for DFF optimization, which is applied to a processor and is used for reducing invalid events in an event queue, as shown in FIG. 1, and the method comprises the following steps:
step 101: and if the current output value of the circuit gate is inconsistent with the last output value, adding the event generated by the circuit gate into an event queue.
The netlist comprises a connection relation among a plurality of circuit gates, the connection relation exists in a netlist file, a netlist analyzer reads a netlist file in a Verilog format, a processor analyzes the netlist file and stores the netlist file in an internal data structure, a vector analyzer reads a vector file in a VCD format, the processor analyzes the vector file and stores the vector file in the internal data structure, and the processor extracts excitation data of the netlist from the analyzed vector file according to input and output ports of the netlist and loads the excitation data to an input port of a first circuit gate in the netlist. Since the current stimulus data and the previously loaded data are not identical, the circuit gate needs to be recalculated once, and the output value of the circuit gate is usually calculated according to the input value of the circuit gate and the type of the circuit gate.
If the output value obtained by this calculation is not consistent with the output value obtained by the previous calculation, then an event is generated at the input port of the netlist, and the event is added to the event queue.
In addition, in the netlist, the output of the circuit gate is taken as the input of other circuit gates, and as the output of the current circuit gate changes, it is indicated that all fanouts of the circuit gate also need to be recalculated, because the output of all fanouts corresponding to the circuit gate depends on the output of the circuit gate, and then the fanouts also need to be recalculated. The fanout gate refers to a circuit gate that takes the output of the current circuit gate as a direct input.
Step 102: and adding the fan-out gate into an event queue or a DFF identification queue according to the type of the fan-out gate corresponding to the circuit gate. The fan-out gate refers to a directly subordinate module of the circuit gate.
For the current circuit gate, whether its corresponding fanout gate is added to the event queue or the DFF identification queue depends on the type of fanout gate.
Specifically, if the fanout gate is a DFF, the processor invokes an ADD function interface of the DFF identification queue, adding the DFF and input port variation information of the DFF to the DFF identification queue. That is, the fan-out gate is added to the DFF identification queue, and input port variation information of the DFF is recorded, the input port variation information including variation information of Set terminal, reset terminal, D terminal, CLK terminal, and M terminal.
If the fanout gate is not a DFF, the fanout gate is added to the event queue.
Fig. 2 is a schematic diagram of a DFF identification queue, where two DFFs, DFF1 and DFF2, are included in the DFF identification queue, and each input port of the DFFs includes a Set end, a Reset end, a D end, a CLK end, and an M end.
Step 103: after the event processing in the event queue is completed, if the DFF identification queue is determined not to be empty, determining whether the DFF is a valid event according to the input port variation information of the DFF in the DFF identification queue.
And after the processor finishes the event processing in the event queue, the event queue is empty, at the moment, whether the DFF identification queue is empty is judged, if the DFF identification queue is empty, the current circuit reaches a stable state, no more events to be processed exist, and the flow is ended. If the DFF identification queue is not empty, it is indicated that there may be valid computed events in the DFF identification queue, where those valid computed events need to be found from the DFF identification queue, specifically, at least one DFF exists in the DFF identification queue, and for each DFF, it needs to be determined whether the DFF is a valid event based on its input port variation information.
Determining that the DFF is a valid event includes two cases, one of which is: if the Set port and Reset port of the DFF are changed from the invalid value to the valid value, the DFF is considered as a valid event; another case is: if the Set port and Reset port of the DFF transition from an active value to an inactive value, it is determined whether they are active according to the changes of the D, CLK and M terminals, specifically, if the D terminal changes and the CLK terminal is 0, or the M terminal changes and the CLK terminal is 1, it is determined that the DFF is active.
Other cases consider the DFF as an invalidation event, which continues to remain in the DFF identification queue.
Step 104: if the DFF is an effective event, adding the effective event in the DFF identification queue to the event queue, and calculating the effective event.
If the DFF is an effective event, the processor adds the effective event in the DFF identification queue to the event queue, and then calculates the effective event, where the event in the event queue may be calculated in a common calculation manner, which is not specifically limited in this application.
In the application, if the output value of the circuit gate is inconsistent with the last output value, all fan-out gates are not required to be added into the event queue, if the fan-out gates are DFFs, the fan-out gates are added into the event queue only when the DFF calculation is effective, namely, invalid calculation of the DFFs in the logic simulation process is reduced, logic simulation time is shortened, and therefore simulation performance is improved.
As an alternative embodiment, determining whether the DFF is valid based on the input port variation information of the DFF includes two examples, as follows.
In a first embodiment, if the Set port and Reset port of the DFF transition from an active value to an inactive value, acquiring the changes of the D, CLK, and M ends of the DFF; if the D terminal is changed and the CLK terminal is 0, or the M terminal is changed and the CLK terminal is 1, the DFF is determined to be valid.
Fig. 3 is a schematic diagram of a DFF model, where ports of the DFF include a Set end, a Reset end, a D end, a CLK end, an M end, and a Q end, where the Q end is an output end and other ports are input ends. DFF has both rising edge triggering and falling edge triggering, and for convenience of description, the following will be directed to rising edge triggering unless otherwise specified. If CLK is 0, then data at D can be transferred to M and data at M cannot be transferred to Q; if CLK is 1, data at D terminal cannot be transferred to M terminal, and data at M terminal can be transferred to Q terminal.
If the value after the Set or Reset change is an invalid value (typically 0 invalid), then the values of the M and Q terminals are controlled by the current D and CLK terminals. If the D port changes and the current CLK port is 0, then the DFF needs to be recalculated, and since CLK is 0, the data of the D port can be transmitted to the M terminal, the DFF is added to the event queue; if the M port changes and the current CLK port is 1, then the DFF needs to be recalculated because CLK is 1 and the data for the M port can be transferred to the Q terminal.
In a second embodiment, if the Set port and Reset port of the DFF transition from invalid values to valid values, the DFF is determined to be valid.
If the Set port or Reset port transitions from an invalid value to a valid value (typically 1 valid), the DFF is determined to be valid, and the DFF is added to the event queue to recalculate the Q value.
After the DFF calculation is completed, the calculated DFF is added to the tabu list, and it is impossible to add the DFF added to the tabu list to the event queue. The purpose of adding the tabu table is to prevent the change information of the CLK, D, M terminals from affecting it, because the Set terminal or Reset terminal is active, the value of Q is constant and not controlled by other ports. The Q-terminal of the DFF is a fixed value regardless of the D-terminal or CLK-terminal of the DFF. If the Set port or Reset port is active, then the Q terminal outputs a constant 1. The DFF is then deleted from the tabu table if the Set port or Reset port of the DFF changes from a valid value to an invalid value.
Compared with the prior art that events which are invalid to be calculated are added into an event queue, so that a large number of invalid calculations are generated.
As an alternative implementation manner, if the DFF identifies that the Set port and the Reset port of the DFF in the queue transition from the invalid value to the valid value, the DFF is determined to be valid, and when calculating the valid event, the method further includes: calling a Remove function interface of the DFF identification queue, and deleting the input port change information associated with calculation; if the input port change information of all the DFFs is changed, the DFFs are deleted from the DFF identification queue.
The DFF identification queue also has a Remove function interface. When calculating the effective event, the change information of part of the input ports is needed, that is, the change information of all the input ports is not needed, the used change information of the input ports can be considered to be outdated, and the outdated change information of the input ports can not be reused by the following calculation, so that the input ports with changes in the DFF identification queue are deleted. Wherein the change is for the last time.
Illustratively, if the last time the value of D port was calculated to be 1 and the D port is valid for calculation, then the next change in D port is for the value of D port to be 1. Assuming that at time i the value of D becomes 0, then it is indicated that the D-terminal is changed (1- > 0); at time i+1, assuming that the value of M changes (1- > 0) and clk=1, then the DFF needs to be recalculated (because clk=1, M changes). However, since this calculation only consumes the change information of M, and the change information of D is not effective for this calculation, only the change information of M needs to be emptied, and whether M changes for 0 later.
The DFF identification queue is only used for retaining DFFs with changed input ports, after calculation, some input port change information is consumed, and all the calculated input port change information of the DFFs may be consumed, so that the DFFs have no port change information and need to be deleted from the identification queue. That is, if all of the input port change information of the DFF is consumed, the DFF is deleted from the DFF identification queue using the Remove function.
The logic simulation acceleration method for DFF optimization improves logic simulation speed and saves test cost by reducing invalid calculation of the DFF. In practical application, logic simulation tests are performed on circuits such as ISCAS89, ITC99, E203, xuantie and the like, and the results are shown in table 1, and the effectiveness of the invention is confirmed in table 1.
TABLE 1
The present application provides a flow diagram of logic simulation acceleration for DFF optimization, as shown in fig. 4, a processor parses a netlist file and a vector file, stores the parsing result in an internal data structure, extracts excitation data and response data of the netlist from the vector file, loads the excitation data to an input end of a first circuit gate of the netlist, then loads a fan-out gate to an event queue or a DFF identification queue respectively for whether the fan-out gate is a DFF event, and executes an event driven algorithm, wherein the event driven algorithm is used for identifying whether DFF calculation in the DFF identification queue is effective. After all events are processed, whether the excitation data and the response data are consistent or not needs to be judged, if so, the event-driven algorithm is correct, and the subsequent flow can be continuously executed. If the event-driven algorithms are inconsistent, indicating that the event-driven algorithms are wrong, the flow ends.
Based on the same technical concept, the application provides a logic simulation accelerating device optimized for DFF, as shown in FIG. 5, the device comprises:
a first adding module 501, configured to add an event generated by the circuit gate to the event queue if the current output value of the circuit gate is inconsistent with the last output value;
the second joining module 502 is configured to join the fanout gate to the event queue or the DFF identification queue according to a type of fanout gate corresponding to the circuit gate, where the fanout gate is a subordinate module of the circuit gate;
a determining module 503, configured to determine, after the event processing in the event queue is completed, if it is determined that the DFF identification queue is not empty, whether the DFF is a valid event according to input port variation information of the DFF in the DFF identification queue;
and the processing module 504 is configured to add the effective event in the DFF identification queue to the event queue if the DFF is the effective event, and calculate the effective event.
Optionally, the determining module 503 is configured to:
if the DFF marks that the Set port and the Reset port of the DFF in the queue are converted from the effective value to the invalid value, acquiring the changes of the D end, the CLK end and the M end of the DFF;
if the D terminal is changed and the CLK terminal is 0, or the M terminal is changed and the CLK terminal is 1, the DFF is determined to be valid.
Optionally, the device is further configured to:
if the DFF identifies that the Set port and Reset port of the DFF in the queue transition from invalid values to valid values, the DFF is determined to be valid.
Optionally, the second joining module 502 is configured to:
if the fan-out gate corresponding to the circuit gate is the DFF, adding the fan-out gate into a DFF identification queue, and recording the input port change information of the DFF;
and if the fan-out gate corresponding to the circuit gate is not the DFF, adding the fan-out gate into the event queue.
Optionally, the device is further configured to:
reading a netlist file through a netlist analyzer, and reading a vector file through a vector analyzer;
extracting excitation data of the netlist from the vector file according to the input port and the output port of the netlist file, and recording the excitation data to the input port of the forefront circuit gate in the netlist, wherein the netlist indicates the connection relation among a plurality of circuit gates;
taking excitation data as an input value of a circuit gate;
if the excitation data is inconsistent with the previous excitation data, the circuit gate is calculated again to obtain the current output value.
Optionally, the device is further configured to:
when effective event calculation is carried out, a Remove function interface of the DFF identification queue is called, and input port change information in the DFF identification queue associated with calculation is deleted;
and if all the input port change information of the DFF is changed, deleting the DFF from the DFF identification queue.
Optionally, the device is further configured to:
and adding the calculated DFF into a tabu table, wherein the DFF in the tabu table can not be added into an event queue any more.
As shown in fig. 6, an embodiment of the present application provides an electronic device, which includes a processor 601, a communication interface 602, a memory 603, and a communication bus 604, where the processor 601, the communication interface 602, and the memory 603 perform communication with each other through the communication bus 604.
Memory 603 for storing a computer program.
In one embodiment of the present application, the processor 601 is configured to implement the logic emulation acceleration method for DFF optimization provided in any one of the foregoing method embodiments when executing the program stored on the memory 603, where the method includes:
if the current output value of the circuit gate is inconsistent with the last output value, adding an event generated by the circuit gate into an event queue; adding a fan-out gate into an event queue or a DFF identification queue according to the type of the fan-out gate corresponding to the circuit gate, wherein the fan-out gate refers to a directly subordinate module of the circuit gate; after the event processing in the event queue is completed, if the DFF identification queue is determined not to be empty, determining whether the DFF is an effective event according to the input port change information of the DFF in the DFF identification queue; if the DFF is an effective event, adding the effective event in the DFF identification queue to the event queue, and calculating the effective event.
Optionally, determining whether the DFF is a valid event based on the input port variation information of the DFF in the DFF identification queue includes: if the DFF marks that the Set port and the Reset port of the DFF in the queue are converted from the effective value to the invalid value, acquiring the changes of the D end, the CLK end and the M end of the DFF; if the D terminal is changed and the CLK terminal is 0, or the M terminal is changed and the CLK terminal is 1, the DFF is determined to be valid.
Optionally, determining whether the DFF is a valid event according to the input port variation information of the DFF in the DFF identification queue, the method further includes: if the DFF identifies that the Set port and Reset port of the DFF in the queue transition from invalid values to valid values, the DFF is determined to be valid.
Optionally, adding the fanout gate to the event queue or the DFF identification queue according to the type of fanout gate corresponding to the circuit gate includes: if the fan-out gate corresponding to the circuit gate is the DFF, adding the fan-out gate into a DFF identification queue, and recording the input port change information of the DFF; and if the fan-out gate corresponding to the circuit gate is not the DFF, adding the fan-out gate into the event queue.
Optionally, before determining that the current output value of the circuit gate and the last output value are inconsistent, the method further comprises: reading a netlist file through a netlist analyzer, and reading a vector file through a vector analyzer; extracting excitation data of the netlist from the vector file according to the input port and the output port of the netlist file, and recording the excitation data to the input port of the forefront circuit gate in the netlist, wherein the netlist indicates the connection relation among a plurality of circuit gates; taking excitation data as an input value of a circuit gate; if the excitation data is inconsistent with the previous excitation data, the circuit gate is calculated again to obtain the current output value.
Optionally, when calculating the effective event, the method further includes: when effective event calculation is carried out, a Remove function interface of the DFF identification queue is called, and input port change information in the DFF identification queue associated with calculation is deleted; and if all the input port change information of the DFF is changed, deleting the DFF from the DFF identification queue.
Optionally, after calculating the valid event, the method further comprises: and adding the calculated DFF into a tabu table, wherein the DFF in the tabu table can not be added into an event queue any more.
The present application also provides a computer readable storage medium having stored thereon a computer program which, when executed by a processor, implements the steps of the logic simulation acceleration method for DFF optimization provided by any one of the method embodiments described above.
The apparatus embodiments described above are merely illustrative, wherein elements illustrated as separate elements may or may not be physically separate, and elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
From the above description of embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus a general purpose hardware platform, or may be implemented by hardware. Based on such understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the related art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, a server, or a network device, etc.) to execute the method of the respective embodiments or some parts of the embodiments.
It is to be understood that the terminology used herein is for the purpose of describing particular example embodiments only, and is not intended to be limiting. As used herein, the singular forms "a", "an", and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "includes," "including," and "having" are inclusive and therefore specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order described or illustrated, unless an order of performance is explicitly stated. It should also be appreciated that additional or alternative steps may be used.
The foregoing is merely exemplary of embodiments of the present invention to enable those skilled in the art to understand or practice the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A logic simulation acceleration method for DFF optimization, the method comprising:
if the current output value of the circuit gate is inconsistent with the last output value, adding an event generated by the circuit gate into an event queue;
adding the fan-out gate into the event queue or the DFF identification queue according to the type of the fan-out gate corresponding to the circuit gate, wherein the fan-out gate refers to a directly subordinate module of the circuit gate;
after the event processing in the event queue is completed, if the DFF identification queue is determined not to be empty, determining whether the DFF is a valid event according to the input port change information of the DFF in the DFF identification queue;
and if the DFF is an effective event, adding the effective event in the DFF identification queue to the event queue, and calculating the effective event.
2. The method of claim 1, wherein determining whether the DFF is a valid event based on input port variation information of DFFs in the DFF identification queue comprises:
if the Set port and Reset port of the DFF in the DFF identification queue are converted from the effective value to the ineffective value, acquiring the changes of the D end, the CLK end and the M end of the DFF;
if the D terminal is changed and the CLK terminal is 0, or the M terminal is changed and the CLK terminal is 1, the DFF is determined to be valid.
3. The method of claim 1, wherein determining whether the DFF is a valid event based on input port variation information of DFFs in the DFF identification queue, the method further comprising:
and if the Set port and the Reset port of the DFF in the DFF identification queue are converted from the invalid value to the valid value, determining that the DFF is valid.
4. The method of claim 1, wherein adding the fanout gate to the event queue or DFF identification queue based on a type of fanout gate to which the circuit gate corresponds comprises:
if the fan-out gate corresponding to the circuit gate is a DFF, adding the fan-out gate into the DFF identification queue, and recording the input port change information of the DFF;
and if the fan-out gate corresponding to the circuit gate is not the DFF, adding the fan-out gate into the event queue.
5. The method of claim 1, wherein prior to determining that the current output value of the circuit gate and the last output value do not agree, the method further comprises:
reading a netlist file through a netlist analyzer, and reading a vector file through a vector analyzer;
extracting excitation data of a netlist from the vector file according to an input port and an output port of the netlist file, and recording the excitation data to an input port of a circuit gate at the forefront end in the netlist, wherein the netlist indicates a connection relationship among a plurality of circuit gates;
taking the excitation data as an input value of the circuit gate;
if the excitation data is inconsistent with the previous excitation data, the circuit gate is calculated again to obtain the current output value.
6. The method of claim 1, wherein when calculating the valid event, the method further comprises:
when the effective event is calculated, a Remove function interface of the DFF identification queue is called, and input port change information in the DFF identification queue associated with calculation is deleted;
and if all the input port change information of the DFF is changed, deleting the DFF from the DFF identification queue.
7. A method according to claim 3, wherein after calculating the valid event, the method further comprises:
adding the calculated DFF to a tabu table, wherein the DFF in the tabu table can no longer be added to an event queue.
8. A logic simulation acceleration apparatus optimized for DFF, the apparatus comprising:
the first adding module is used for adding an event generated by the circuit gate into the event queue if the current output value of the circuit gate is inconsistent with the last output value;
the second joining module is used for joining the fan-out gate into the event queue or the DFF identification queue according to the type of the fan-out gate corresponding to the circuit gate, wherein the fan-out gate refers to a directly subordinate module of the circuit gate;
the determining module is used for determining whether the DFF is a valid event according to the input port change information of the DFF in the DFF identification queue if the DFF identification queue is determined not to be empty after the event processing in the event queue is completed;
and the processing module is used for adding the effective event in the DFF identification queue to the event queue if the DFF is the effective event, and processing the effective event.
9. The electronic equipment is characterized by comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory are communicated with each other through the communication bus;
a memory for storing a computer program;
a processor for implementing the method of any of claims 1-7 when executing a program stored on a memory.
10. A computer readable storage medium, characterized in that the computer readable storage medium has stored therein a computer program which, when executed by a processor, implements the method of any of claims 1-7.
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