CN117850880A - Three-level pipeline BCH decoding method for high-error-rate memory - Google Patents
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Abstract
The invention discloses a three-level pipeline BCH decoding method for a high-error-rate memory, and belongs to the technical field of integrated circuits. The invention cuts the decoder into a syndrome generating circuit, an error equation generating circuit and a Qian's search circuit, wherein the algebraic structure of the error equation is not changed, and the decoding frequency of the whole decoder is increased in multiple. The invention improves the decoding frequency and increases the range of a decoder applicable system.
Description
Technical Field
The invention belongs to the technical field of BCH coding and decoding circuit implementation in the fields of memory and error correction coding, and particularly relates to a BCH decoding method with low delay and low resource loss.
Background
Memories are often subject to random errors, such as Single Event Upset (SEU) and multi-bit single event upset (MBU). To cope with these soft errors, ECC algorithms are widely used, where BCH codes are widely used for soft error correction in memory, communication and embedded systems with their excellent performance. The anti-MBU ECC algorithm is crucial for memory protection, and considers the single event upset resistance of the memory, which is commonly expressed as error/bits. For the mass storage, algorithms such as BCH codes are often adopted, but the improvement of error correction capability is accompanied by the increase of redundancy bits, thereby affecting the storage space and the cost. [1].
For a large-capacity memory such as Nand flash, page table-level ECC error correction can provide a better error correction effect, but has a certain consideration on cost and performance. In embedded products, particularly MCU-level memory cells, the requirements on the speed and parallelization degree of ECC encoding and decoding are high, so that encoding and decoding processes can be finished within a limited clock period, and the running speed of a processor and the utilization rate of a pipeline are improved.
Research on ECC algorithm has been advanced toward high error correction performance, low resource consumption and high error correction efficiency since the hamming code in 1950. High performance refers to low latency, high bandwidth, multi-bit error correction, low resource consumption requires circuitry to achieve low power consumption, small area, while high error correction efficiency means more data bits are error corrected with fewer parity bits. For civil embedded systems, particularly flash, SRAM, ROM and other memories in MCU, the system is sensitive to the requirements of low delay and low resource consumption.
For an embedded memory device which can generate multi-bit errors but has fewer error patterns, smaller memory quantity, important memory content, close memory and high memory access speed requirement, the BCH parallelization coding and decoding circuit can be used as a choice of an ECC scheme. After circuit optimization, the scheme can realize good time delay and frequency performance in the control resource loss range.
The BCH decoding method mainly comprises three steps of generating a syndrome equation, generating an error equation and solving the error equation through Qian's search. At present, a team adopts a 2-stage pipeline cutting mode to optimize a BCH decoding circuit, which is beneficial to synthesizing circuits with better performance, power consumption and size performance.
Disclosure of Invention
The invention provides a three-level pipeline BCH decoding method for a high-error-rate memory, which aims to increase the BCH decoding frequency and reduce the decoding delay, and is different from the prior table lookup decoding method and BM iteration method.
The technical scheme of the invention is as follows:
a three-level pipeline BCH decoding method for a high bit error rate memory is characterized by comprising the following specific steps:
1) In the first stage pipeline, a syndrome calculation circuit receives a codeword polynomial r according to an mth decoding period m (x) Calculating to obtain the ith accompanying S in the mth decoding period i，m (x) For the n-bit total codeword length and the k-bit data bit length, the BCH code correcting t-bit errors is (n, k, t) BCH code, r m (x) And S is equal to i，m (x) The calculation formula is as follows:
wherein r is j，m The value of the j-th codeword received for the m-th decoding period, a being the primitive of the corresponding number field, can be regarded as a constant.
2) Will S i，m (x) Storing into a first stage pipeline register;
3) In the second stage pipeline, the mth decoding period of the current system is taken as the reference value of the time dimension, and the error equation generating circuit generates a syndrome S according to the result of the output end of the previous stage pipeline i，m-1 (x) (corresponding to the received codeword of the m-1 th cycle input system), an error equation delta is calculated m-1 (x) Error equation delta m-1 (x) The form of (2) is as follows:
solving error equation delta m-1 (x) Coefficient delta of each item in (a) j，m-1 The error location, delta, at the index can be obtained j，m-1 The value of (2) and S obtained in the previous step i，m-1 (x) There is a relationship where v refers to the number of erroneous bits, specifically solving for delta j.m-1 The formula of (2) is as follows:
S j+v，m-1 +δ 1，m-1 S j+v-1，m-1 +…+δ v-1，m-1 S j+1，m-1 +δ v，m-1 S j，m-1 ＝01≤j≤2t-v
(4)
5) Error equation delta m-1 (x) Each coefficient of (2) is stored in a second stage pipeline register;
6) In the third stage pipeline, the mth decoding period which the current system proceeds to is also used as a reference value of the time dimension. Output error equation delta for second stage pipeline m-2 (x) (corresponding to the received codeword of the m-2 th cycle input system), the present invention solves the difference using a Chien search circuitAnd (5) misequation. The Chien search circuit determines the location of the error by searching for a zero point (the root of the polynomial) over a finite field. I.e. by evaluating the value of each finite field element, an element is found that makes the error polynomial zero, and thus the location of the error. The specific steps include evaluating each element in the finite field and checking if the result is zero. If the result is zero, it indicates that the element is the root of the error polynomial, thereby determining an error location. This process is repeated until all the error locations are found.
The beneficial effects of the invention are as follows:
the invention adopts a three-stage pipeline structure, one is to protect the integrity of algebraic structures and further ensure the correct function of the decoder, and the other is to prove that the three-stage pipeline achieves better balance in decoding period, decoding frequency and circuit area, improves the decoding frequency by combining actual scenes, and increases the range of applicable systems of the decoder.
Drawings
FIG. 1 is a block diagram of the overall hardware of a Peterson decoder based on a three-stage pipeline in accordance with an embodiment of the present invention;
FIG. 2 illustrates a syndrome generating circuit according to an embodiment of the present invention;
FIG. 3 shows a BCH decoder error equation generation circuit (44, 32) in accordance with an embodiment of the present invention;
FIG. 4 shows a verification equation sub-circuit of the Chien search circuit of the BCH decoder (44, 32) according to an embodiment of the present invention;
fig. 5 is a schematic diagram showing the results of comparing the time delay and the hardware resource occupation of various decoding methods of BCH according to the embodiment (44, 32) of the present invention.
Detailed Description
The invention is described below in terms of a BCH decoder implementation based on a chien search circuit for (44, 32, 2) BCH codes (n=44, k=32, t=2).
The (44, 32, 2) BCH code has the common features of several BCH codes:
1. the number of data bits before encoding is k=32, the number of total codeword bits after encoding is n=44 bits, and the number of check bits is n-k=12.
2. The error correction capability of the (44, 32, 2) BCH code is 2, and the maximum two-bit random error in the 44-bit total codeword can be corrected, and the encoding and decoding operation of the BCH code occurs in a galois field GF (26) because of 26-1>44>25-1, and if m=6, the length of the check bit is mt=6x2=12.
The overall architecture of the Peterson decoder based on the three-stage pipeline is shown in fig. 1, the pipeline structure is introduced among all sub-modules, and the key paths of the circuit are divided on the premise of ensuring that the algebraic structure is not changed, so that the decoding frequency is improved.
1) In the first stage pipeline, a syndrome calculation circuit receives a codeword polynomial r according to an mth decoding period m (x) Calculating to obtain the ith accompanying S in the mth decoding period i，m (x) For the n-bit total codeword length and the k-bit data bit length, the BCH code correcting t-bit errors is (n, k, t) BCH code, r m (x) And S is equal to i，m (x) The calculation formula is as follows:
wherein r is j，m The value of the j-th codeword received for the m-th decoding period, a being the primitive of the corresponding number field, can be regarded as a constant.
Specifically, in the first stage pipeline with a solving part, the invention uses the modular multiplication and modular addition operation in the finite field, and for the modular addition operation between any two elements in the finite field, the modular multiplication is represented by "x" and the modular addition is represented by "+", the syndrome generating circuit shown in fig. 2 can be constructed, and according to the Peterson decoding principle, the (44, 32) BCH code only needs to calculate S 1，m And S is equal to 3，m Can (S) 2，m 、S 4，m And S is equal to 1，m Equal), as can be seen from fig. 2, these two syndromes are actually implementation (1). The companion computing circuit replaces "+" with bitwise exclusive OR, i.e. modulo addition, to computeAnd outputting the syndrome value.
2) Will S i，m (x) Storing into a first stage pipeline register;
3) In the second stage pipeline, the mth decoding period of the current system is taken as the reference value of the time dimension, and the error equation generating circuit generates a syndrome S according to the result of the output end of the previous stage pipeline i，m-1 (x) (corresponding to the received codeword of the m-1 th cycle input system), an error equation delta is calculated m-1 (x) Error equation delta m-1 (x) The form of (2) is as follows:
solving error equation delta m-1 (x) Coefficient delta of each item in (a) j，m-1 The error location, delta, at the index can be obtained j，m-1 The value of (2) and S obtained in the previous step i，m-1 (x) There is a relationship where v refers to the number of erroneous bits, specifically solving for delta j.m-1 The formula of (2) is as follows:
S j+v，m-1 +δ 1，m-1 Sj +v-1，m-1 +…+δ v-1，m-1 S j+1，m-1 +δ v，m-1 S j，m-1 ＝0 1≤j≤2t-v
(4)
Specifically, in the error equation solving section of the second stage pipeline, S is outputted based on the first stage pipeline register 1,m-1 、S 3，m-1 (corresponding to the received codeword of the m-1 th cycle input system), the modulo multiplier and modulo adder employed by the present invention constructs an error equation generation circuit. According to the Peterson decoding principle, the error equation of the (44, 32) BCH code is shown in the formula (4), the coefficient is obtained by deduction, the operation in the formula is modular multiplication and modular addition, and because S1 and S3 are variables, the modular multiplication of the variables is adopted, and the modular addition operation can be replaced by bitwise exclusive OR. The circuit configuration is shown in fig. 3.
4) Error equation delta m-1 (x) Each coefficient of (2) is stored in a second stage pipeline register;
5) In the third stage pipeline, an error equation delta is output for the second stage pipeline m-2 (x) And solving an error equation by adopting a Chien search circuit to find the error position.
Specifically, in the third stage pipeline, delta is output according to the second stage pipeline register 0，m-2 、δ 1，m-2 、δ 2，m-2 (corresponding to the received codeword of the m-2 th cycle input system), the Chien search circuit substitutes 44 finite field elements a0 to a-43 representing the error positions into the error equation to generate 44 verification equations, wherein the result of the verification equation is 0, which indicates that the corresponding position is error, and the result of two verification equations is 0 in the scene of two-bit error.
FIG. 4 shows the validation equation sub-circuit of the Chien search circuit, which functions to solve the error equation to yield a vector that characterizes the error location, i.e., an error pattern. Since the verification equation sub-circuit has a large number of scenes multiplied by 44 finite field elements, namely a0 to a-43, constant modulus multiplication can be used to save circuit area and reduce decoding delay.
By adopting the invention, in the aspect of occupying hardware resources, the invention only adds the Pipeline register on the basis of single-period pipeless Peterson decoding. And because a large number of bit exclusive OR logics exist in each part of the circuit adopted in the invention, the DC tool can combine common sub-expressions among all parts under the condition of fan-out permission, and the DC can optimize the combination logic more after cutting complex combination logic along with the insertion of a register.
Fig. 5 shows a comparison of the time delay and hardware resource occupancy of various decoding methods of the (44, 32, 2) BCH code. From the above results, the Peterson decoder based on the three-stage pipeline in the invention is optimal in time sequence in all schemes, the longest path delay is only 2.20ns under the clock of 400Mhz, and no violation exists. Due to its pipelined structure, the frequency boost is quite significant.
Reference is made to:
[1] error correction coding technique [ M ]. People's post and telecommunications Press 1987
[2] ECC error detection and correction techniques review [ C ] Wang Ning. University of southeast university school celebration report society of research, 2020
[3]1.Liu yang,Li jie,et alA BCH error correction scheme applied to FPGA with embedded
memoryJL.Frontiers ofInformation Technology&Electronic Engineering2021-11):
[4]Hughes H L,Benedetto J M.Radiation Effects and Hardening of MOS
Technology:Devices and Circuits[J].IEEE Transaction on Nuclear Science,2003,50(3):500-521.
[5] Zhang Jun, wang Zhigong, hu Qingsheng, shore-clean high speed parallel BCH (2184,2040) encoder VLSI optimization
Design, circuit and System theory 2006,11 (1): 88-94.
Claims (5)
1. A three-level pipeline BCH decoding method for a high bit error rate memory is characterized by comprising the following steps:
1) In the first stage pipeline, a syndrome calculation circuit receives a codeword polynomial r according to an mth decoding period m (x) Calculating to obtain the ith accompanying S in the mth decoding period i，m (x) For BCH codes with n-bit total codeword length, k-bit length and t-bit error correction, r m (x) And S is equal to i，m (x) The calculation formula is as follows:
wherein r is j，m Receiving the value of the j-bit code word for the m-th decoding period, wherein a is the primitive element of the corresponding number domain;
2) Will S i，m (x) Storing into a first stage pipeline register;
3) In the second stage pipeline, the error equation generating circuit generates a syndrome S according to the result of the output end of the previous stage pipeline i，m-1 (x) Calculating an error equation delta m-1 (x) Error equation delta m-1 (x) The form of (2) is as follows:
solving error equation delta m-1 (x) Coefficient delta of each item in (a) j，m-1 Solving delta j.m-1 The formula of (2) is as follows: where v refers to the number of erroneous bits,
S j+v，m-1 +δ 1，m-1 S j+v，m-1 +…+δ v-1，m-1 S j+1，m-1 +δ v，m-1 S j，m-1 ＝0 1≤j≤2t-v
(4)
4) Error equation delta m-1 (x) Each coefficient of (2) is stored in a second stage pipeline register;
5) In the third stage pipeline, an error equation delta is output for the second stage pipeline m-2 (x) And solving an error equation by adopting a Chien search circuit to find the error position.
2. The three-stage pipelined BCH decoding method for high bit error rate memory as in claim 1, wherein the syndrome computation circuit in step 1) is a syndrome computation using bit exclusive or circuit to construct (n, k, t) BCH codes.
3. The three-stage pipelined BCH decoding method for high-bit-error-rate memory as in claim 1, wherein the error equation generating circuit is constructed using a modulo multiplier and modulo adder in step 3).
4. The three-stage pipelined BCH decoding method for high bit error rate memory as recited in claim 1, wherein in step 5), the Chien search circuit determines the location of the error by searching for zero points over the finite field, i.e., evaluates each element in the finite field and checks if the result is zero, it indicates that the element is the root of the error polynomial, thereby determining an error location, and the process is repeated until all error locations are found.
5. The three-level pipelined BCH decoding method for a high bit error rate memory as in claim 4, wherein the error location is converted into an error pattern.
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