CN117835698A - Memory, method for manufacturing the same, and memory system - Google Patents

Abstract

The embodiment of the disclosure discloses a memory, wherein the memory comprises: a substrate having a first surface and a second surface disposed opposite to each other in a thickness direction of the substrate; a storage structure located on the first surface; the memory structure includes a memory array including a plurality of memory cells; each memory cell includes a write transistor and a read transistor, wherein a resistance state between a source and a drain of the read transistor is changed by the write transistor; a peripheral structure located on the second surface; and the connecting structure penetrates through the substrate and is electrically connected with the storage structure and the peripheral structure.

Description

Memory, method for manufacturing the same, and memory system

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a memory, a manufacturing method thereof and a memory system.

Background

With the rapid increase of popularity of electronic devices and the vigorous development of the electronic device market, electronic products are increasingly required to be miniaturized and thinned while having high performance, multiple functions, high reliability and convenience. Such demands place higher demands on the integration level and reliability of the memory.

Disclosure of Invention

In view of the above, embodiments of the present disclosure provide a memory, a method for manufacturing the same, and a memory system.

According to one aspect of the present disclosure, there is provided a memory including:

a substrate having a first surface and a second surface disposed opposite to each other in a thickness direction of the substrate;

a storage structure located on the first surface; the memory structure includes a memory array including a plurality of memory cells; each memory cell includes a write transistor and a read transistor, wherein a resistance state between a source and a drain of the read transistor is changed by the write transistor;

a peripheral structure located on the second surface;

and the connecting structure penetrates through the substrate and is electrically connected with the storage structure and the peripheral structure.

In the above aspect, the memory includes a plurality of memory structures stacked in a thickness direction of the substrate.

In the above scheme, the memory further comprises an isolation layer, and the isolation layer is located between two adjacent memory structures.

In the above solution, the storage structure further includes: a storage interconnect layer; the storage interconnection layer is positioned on the surface of the storage array, which is far away from the substrate, and is electrically connected with the storage array;

the peripheral structure includes: peripheral circuitry and peripheral interconnect layers; the peripheral circuit is positioned on the second surface; the peripheral interconnection layer is positioned on the surface of the peripheral circuit, which is far away from the substrate, and is electrically connected with the peripheral circuit;

the connection structure electrically connects the storage interconnect layer and the peripheral interconnect layer.

In the above scheme, the storage structure is located above the peripheral structure.

In the above solution, the storage array includes: a read word line, a read transistor, a write word line, a read bit line, and a write bit line stacked in the thickness direction of the substrate; wherein,

one of a source or a drain of the read transistor is connected to the read word line, and the remaining one of the source or the drain is connected to the read bit line;

one of a source or a drain of the write transistor is connected to a gate of the read transistor, the remaining one of the source or the drain is connected to the write bit line, and the gate is connected to the write word line.

In the above scheme, the memory further comprises an electric lead-out structure, which is positioned on the surface of the memory structure or the peripheral structure away from the substrate; the memory is connected with an external device through the electric lead-out structure;

the electrical extraction structure includes: a through hole in the memory structure or the peripheral structure; a conductive plunger located in the through hole; a rewiring layer located on a surface of the memory structure or the peripheral structure remote from the substrate; and a pad on the rewiring layer.

According to another aspect of the present disclosure, there is provided a memory system, the memory system including any one of the memories described above; and a memory controller connected with the memory and used for controlling the memory.

According to another aspect of the present disclosure, there is provided a method of manufacturing a memory, the method comprising:

providing a substrate, wherein the substrate is provided with a first surface and a second surface which are oppositely arranged along the thickness direction of the substrate;

forming a storage structure on a first surface of the substrate; the storage structure includes: the memory structure includes a memory array including a plurality of memory cells; each memory cell includes a write transistor and a read transistor, wherein a resistance state between a source and a drain of the read transistor is changed by the write transistor;

forming a peripheral structure at a second surface of the substrate;

a connection structure is formed through the substrate and electrically connects the memory structure and the peripheral structure.

In the above scheme, forming a storage structure on the first surface of the substrate includes:

forming a plurality of storage structures stacked in a thickness direction of the substrate on the first surface, forming each storage structure, including:

forming a memory array;

and forming a storage interconnection layer on the surface of the storage array, which is far away from the substrate.

In the above scheme, the method further comprises:

an isolation layer is formed between two adjacent memory structures. In the above scheme, forming the memory array includes:

sequentially forming a read word line, a read transistor, a write word line, a read bit line and a write bit line along the thickness direction of the substrate; wherein,

one of a source or a drain of the read transistor is connected to the read word line, and the remaining one of the source or the drain is connected to the read bit line;

one of a source or a drain of the write transistor is connected to a gate of the read transistor, the remaining one of the source or the drain is connected to the write bit line, and the gate is connected to the write word line.

In the above scheme, forming the peripheral structure includes:

forming a peripheral circuit on a second surface of the substrate;

a peripheral interconnect layer is formed on a second surface of the substrate.

In the above aspect, forming the connection structure includes:

after forming the memory structure and the peripheral structure, forming a connection structure penetrating the memory structure, the substrate and the peripheral structure;

or,

forming a storage connection structure penetrating through the storage structure and the substrate when forming the storage structure; forming a peripheral connection structure penetrating through the peripheral structure when forming the peripheral structure; the electrically connected memory connection structure and the peripheral structure together form the connection structure.

In the above scheme, the method further comprises: forming an electrical lead-out structure on a surface of the memory structure remote from the substrate or the peripheral structure remote from the substrate; the memory is connected with an external device through the electric lead-out structure;

forming the electrical lead-out structure, comprising:

forming a through hole in the memory structure or the peripheral structure;

filling conductive materials in the through holes to form conductive plungers;

forming a rewiring layer on the surface of the storage structure away from the substrate or the surface of the peripheral structure away from the substrate;

and forming a welding pad on the rewiring layer.

The embodiment of the disclosure provides a memory, a manufacturing method thereof and a memory system, wherein the memory comprises: the memory structure is electrically connected with the peripheral structure through a connecting structure penetrating through the substrate. The memory structure includes a memory array including a plurality of memory cells, each memory cell including a write transistor and a read transistor, wherein a resistance state between a source and a drain of the read transistor is changed by the write transistor. On one hand, the storage structure and the peripheral structure are respectively arranged on the two sides of the substrate, so that the occupied area of the memory is effectively reduced, and the integration level of the memory is improved; on the other hand, the connection between the storage structure and the peripheral structure is realized through the connection structure penetrating through the substrate, so that the connection distance between the storage array and the peripheral circuit can be shortened, and the delay problem is effectively improved; in still another aspect, the memory cells in the memory array adopt a 2T0C architecture, it can be appreciated that the memory cells in the 2T0C architecture are easy to implement in a fully epitaxial manner, damage to the substrate can be reduced to improve the success rate of double-sided integration, and the charge retention time of the 2T0C architecture is longer than that of the capacitor in the conventional 1T1C architecture, so that the refresh frequency is lower, and further the memory power consumption is lower.

Drawings

Fig. 1 is a flow chart of a method for manufacturing a memory according to an embodiment of the disclosure;

fig. 2-7 are schematic cross-sectional views illustrating a manufacturing process of a memory according to an embodiment of the disclosure.

Detailed Description

In order to make the technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the present disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

The present disclosure is described more specifically in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become more fully apparent from the following description and appended claims. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the disclosure.

It will be understood that the meanings of "on … …", "over … …" and "over … …" in this disclosure should be interpreted in the broadest manner so that "on … …" means not only that it is "on" something with no intervening features or layers therebetween (i.e., directly on something), but also that it is "on" something with intervening features or layers therebetween.

Further, spatially relative terms such as "on … …," "above … …," "above … …," "upper" and the like may be used herein to describe one element or feature's relationship to another element or feature as illustrated for ease of description. In addition to the orientations depicted in the drawings, the spatially relative terms are intended to encompass different orientations of the device in use or operation. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In the presently disclosed embodiments, the terms "first," "second," and "second" are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present disclosure, the meaning of "a plurality" is two or two and, unless specifically defined otherwise.

In the presently disclosed embodiments, the terms "mounted," "connected," "secured," and the like are to be construed broadly, as well as being either permanently connected, detachably connected, or integrally connected, unless otherwise explicitly stated and defined, for example; can be mechanically or electrically connected; can be directly connected or indirectly connected through an intermediate medium, and can be communication between two elements. The specific meaning of the terms in this disclosure will be understood by those of ordinary skill in the art as the case may be.

The technical solutions described in the embodiments of the present disclosure may be arbitrarily combined without any conflict.

Memory referred to in embodiments of the present disclosure includes, but is not limited to, dynamic random access memory (DRAM, dynamic Random Access Memory). It should be noted, however, that the description of the embodiments below with respect to the dynamic random access memory is only for illustrating the present disclosure, and is not intended to limit the scope of the present disclosure.

The dynamic random access memory may include peripheral circuitry and a memory structure; wherein the peripheral circuitry may comprise any suitable digital, analog, and/or mixed signal circuitry configured to facilitate various operations of a memory implementation read operations, write operations, erase operations, and the like. For example, the peripheral circuits may include control logic (e.g., control circuits or controllers), data buffers, decoders (decoders may also be referred to as decoders), drivers and read and write circuits and so forth. When the control logic receives the read-write operation command and the address data, under the action of the control logic, the decoder can apply corresponding voltages obtained from the driver to corresponding bit lines and word lines based on the decoded address so as to realize the read-write of the data and perform data interaction with the outside through the data buffer.

The memory structure includes a memory array, which may include a plurality of memory cells; each memory cell may be a structure including one Transistor and one Capacitor, i.e., the dynamic random access memory is 1 Transistor (T) and 1 Capacitor (C) (1T 1C); it may also be a two Transistor architecture, i.e. a dynamic random access memory is a 2 Transistor (T) and 0 Capacitor (C) (2T 0C) architecture. It should be appreciated that whether the dynamic random access memory is a 1T1C architecture or a 2T0C architecture, its main principle of operation is to use the capacitance or the amount of charge stored in the storage nodes between the transistors to represent whether a binary bit is l or 0.

In forming a memory, peripheral circuitry is typically disposed on the same surface of a substrate as a memory array and connected to the memory array by an interconnect layer disposed over the peripheral circuitry. In the arrangement mode, the peripheral circuit occupies a part of area, so that the use area of the memory array is limited, the improvement of the memory storage density of the memory is limited, the integration of the memory is not facilitated, and meanwhile, the delay problem exists between the peripheral circuit and the memory array due to the long circuit connected with the peripheral circuit.

Based on this, in order to solve one or more of the above problems, the embodiments of the present disclosure provide a memory manufacturing method. Fig. 1 is a flow chart of a method for manufacturing a memory according to an embodiment of the disclosure. As shown in fig. 1, a memory manufacturing method provided by an embodiment of the present disclosure includes the following steps:

s100: providing a substrate, wherein the substrate is provided with a first surface and a second surface which are oppositely arranged along the thickness direction of the substrate;

s200: forming a storage structure on a first surface of the substrate; the storage structure includes: the memory structure includes a memory array including a plurality of memory cells; each memory cell includes a write transistor and a read transistor, wherein a resistance state between a source and a drain of the read transistor is changed by the write transistor;

s300: forming a peripheral structure at a second surface of the substrate;

s400: a connection structure is formed through the substrate and electrically connects the memory structure and the peripheral structure.

It should be understood that the steps shown in fig. 1 are not exclusive and that other steps may be performed before, after, or between any of the steps in the illustrated operations. The steps shown in fig. 1 can be sequentially adjusted according to actual requirements. Fig. 2 to 7 are schematic cross-sectional views illustrating a manufacturing process of a memory according to an embodiment of the disclosure. It should be noted that fig. 2 to fig. 7 are schematic views of an implementation process of a manufacturing method of a complete reflection memory, and the unlabeled portions of the drawings may be shared with each other. The following describes in detail the method for manufacturing the memory provided in the embodiment of the present disclosure with reference to fig. 1 and fig. 2 to fig. 7.

In step S100, a substrate is mainly provided.

In some embodiments, the substrate may include an elemental semiconductor material substrate (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a silicon germanium (SiGe) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Preferably, the substrate is a silicon substrate.

Here, the first surface S1 and the second surface S2 are two surfaces of the substrate which are disposed opposite to each other in the thickness direction thereof as shown in fig. 2. The first surface and the second surface may be interchangeable. In some embodiments, the first surface may be a front surface of the substrate and the second surface may be a back surface of the substrate; in other embodiments, the first surface may be a back surface of the substrate and the second surface may be a front surface of the substrate. Here, the front surface may be understood as a surface of the substrate which is generally used for growing the functional thin film layer, and the back surface may be understood as a surface of the substrate which is generally used for being placed on the susceptor.

In step S200, a memory structure is formed primarily on a first surface of a substrate.

In some embodiments, forming a memory structure on a first surface of the substrate includes:

forming a plurality of storage structures stacked in a thickness direction of the substrate on the first surface, forming each storage structure, including:

forming a memory array;

and forming a storage interconnection layer on the surface of the storage array, which is far away from the substrate.

The process of forming the memory array is described in detail below with reference to fig. 2.

In some embodiments, forming a memory array includes:

sequentially forming a read word line, a read transistor, a write word line, a read bit line and a write bit line along the thickness direction of the substrate; wherein,

one of a source or a drain of the read transistor is connected to the read word line, and the remaining one of the source or the drain is connected to the read bit line;

one of a source or a drain of the write transistor is connected to a gate of the read transistor, the remaining one of the source or the drain is connected to the write bit line, and the gate is connected to the write word line.

As shown in fig. 2, a memory array 200 is formed on a substrate 100, the memory array 200 including a plurality of memory cells, each memory cell including a read transistor 201 and a write transistor 202. The write transistor 202 is used to control data writing and the read transistor 201 is used to read data, and it is understood that the gate of the read transistor is connected to one of the source or drain of the write transistor, and that the charge in the gate capacitance (i.e., storage Node) of the read transistor can be changed by the write transistor to complete writing and reading of data. The specific read-write process is as follows:

during the process of writing a "1", a positive voltage (greater than a threshold voltage) is applied to the gate of the Write transistor (i.e., the Write Word Line) so that the Write transistor turns on, and a positive voltage is applied to one of the source or drain of the Write transistor (i.e., the Write Bit Line) so that charge is injected to the gate capacitance of the read transistor. Removing the voltage written into one of the grid electrode and the source electrode or the drain electrode of the transistor after the charge injection, and then storing a '1' state in the memory cell;

a process of reading 1, namely, applying a reading voltage to one of a source electrode or a drain electrode of a reading transistor (and a reading Word Line), wherein the reading transistor is in a lower resistance state to obtain a larger current due to a certain charge stored in a gate capacitor, and then completing a reading 1 process after the peripheral circuit is amplified and identified;

during the process of writing a "0", a positive voltage (greater than the threshold voltage) is applied to the gate of the read transistor (i.e., write word line WWL) causing the write transistor to turn on, and a negative voltage is applied to one of the source or drain of the write transistor (i.e., write bit line WBL) to draw charge to the read transistor gate capacitance. After the charge is extracted, removing the voltage of one of the grid electrode and the source electrode or the drain electrode of the writing transistor, and then the memory cell keeps a 0 state;

and in the process of reading 0, a reading voltage is applied to one of the source electrode or the drain electrode of the reading transistor (and a reading Word Line), and the reading transistor is in a higher resistance state due to no charge in the gate capacitor, so that smaller current is obtained, and the reading 0 process is completed after the peripheral circuit is amplified and identified.

The write transistor 202 is directly above the read transistor 201, and it is understood that the read transistor 201 and the write transistor are stacked to form more memory cells on the same area, which is beneficial to provide the memory density of the memory.

In practice, the arrangement of the writing transistor 202 and the reading transistor 201 is not limited thereto, and the writing transistor 202 and the reading transistor 201 may be located on the same horizontal plane.

In some embodiments, one or more layers of the memory array may be formed by epitaxial deposition.

Illustratively, a read word line 203 is formed in an epitaxial layer by epitaxially depositing a semiconductor layer 207 on the substrate 100, followed by forming a read transistor 201, the read transistor 201 including a pillar gate 209, a dielectric layer 210, and an active layer 211, the dielectric layer 210 covering the sidewalls and bottom of the pillar gate 209, the active layer 211 covering the sidewalls and bottom of the dielectric layer 210, the bottom of the active layer 211 being electrically connected to the read word line 203. Doping the bottom surface of the active layer 211 to form one of a source or a drain, in other words, the read word line 203 is connected to one of the source or the drain of the read transistor 201; the sidewalls of the active layer 211 are doped to form the remaining one of the source or drain around which the read bit line 204 is formed, in other words, the read bit line 204 is connected to the remaining one of the source or drain of the read transistor 201.

After the read transistor 201 is formed, the write transistor 202 is formed above the read transistor 201, the write transistor 202 includes a column gate 212, a dielectric layer 213, and an active layer 214, the dielectric layer 213 covers the sidewall and bottom surface of the column gate 212, the active layer 214 covers the sidewall and bottom surface of the dielectric layer 213, and the bottom surface of the active layer 214 is electrically connected to the gate of the read transistor 201. Specifically, the bottom surface of the active layer 214 may be connected to the gate of the read transistor 201 through a Storage Node (SN) 208, and the material of the Storage Node SN includes a titanium nitride (TiN) material, which has good thermal stability, good compatibility with a high-K dielectric layer, and good mechanical strength, and effectively electrically connects the read transistor 201 and the write transistor 202 while reducing contact resistance. Here, the gate of the read transistor may be directly used as the storage node, or the storage node may be additionally formed.

Next, the bottom surface of the active layer 211 of the writing transistor 202 is doped to form one of a source or a drain, in other words, one of the source or the drain of the writing transistor 202 is electrically connected to the gate of the reading transistor 201; doping the sidewall of the active layer 211 to form the remaining one of the source or the drain, forming a write bit line 205 around the remaining one of the source or the drain, in other words, the write bit line 205 is connected to the remaining one of the source or the drain of the write transistor 202; a write word line 206 is formed, the write word line 206 being connected to a gate 212 of the write transistor 202.

It can be appreciated that the thickness of the epitaxial layer can be conveniently controlled by controlling the epitaxial process, and damage to the substrate due to excessive etching of the substrate, etc. can be avoided by means of epitaxy.

Next, a storage interconnect layer is formed on a surface of the storage array remote from the substrate. As shown in fig. 3, the storage interconnect layer 302 may include a plurality of layers, which are connected by conductive pillars, and each of which may include a plurality of metal electrodes 301, or referred to as electrodes in layers. Illustratively, the material of the electrodes in the layer may include, but is not limited to, copper.

In fig. 3, two stacked interconnect layers are shown, the two interconnect layers are connected by conductive pillars, and one interconnect layer is connected to the write bit line WBL and write word line WWL of the write transistor 202, and the other interconnect layer is connected to peripheral circuitry by conductive pillars as can be seen in the following figures. It should be noted that the storage interconnect layer shown in fig. 3 is only used as an exemplary illustration of the embodiments of the present disclosure, and is not intended to limit the structure of the storage interconnect layer in the embodiments of the present disclosure.

In some embodiments, a plurality of memory structures are formed that are stacked in a thickness direction of the substrate.

In the case where two memory structures are formed to be stacked in the thickness direction of the substrate, as shown in fig. 4, three or more memory structures may be formed to be stacked in the thickness direction of the substrate in other embodiments.

In some embodiments, the same method of forming a memory structure as described above may be used to form a new memory array layer on the memory interconnect layer of the previous memory structure and a new memory interconnect layer on the new memory array layer.

In some embodiments, the method further comprises:

an isolation layer is formed between two adjacent memory structures.

Here, the material of the isolation layer includes, but is not limited to, silicon oxide.

It can be appreciated that the formation of the isolation layer can well reduce crosstalk between two layers of memory structures, and improve the working efficiency of the memory. For example, charge leakage from one memory structure into another memory structure is reduced.

Next, step S300 is performed, mainly to form a peripheral structure.

Next, the formation of the peripheral structure will be described in detail with reference to fig. 5.

The substrate 100 having the memory structure formed on the first surface is flipped over and the peripheral structure 500 is formed on the second surface of the substrate 100. In some embodiments, a carrier is formed on a surface of the storage structure remote from the second surface of the substrate 100 prior to forming the peripheral structure 500 on the second surface. The carrier may facilitate processing of the substrate 100 after flipping.

In some specific embodiments, the substrate may be thinned from the second surface of the substrate prior to forming the peripheral structure.

In some embodiments, the thinned substrate is subjected to a planarization process, which includes, but is not limited to, chemical mechanical polishing (CMP, chemistry Mechanical Polishing).

It will be appreciated that the thinned substrate is more advantageous for the formation of connection structures in subsequent processes, which require through-substrate, since the connection structures are formed by through-silicon vias (TSV, through Silicon Via) technology, the thinner the substrate, the simpler the through-process, and the larger the through-process window.

In some embodiments, forming the peripheral structure includes: forming a peripheral circuit 500 on a second surface of the substrate; a peripheral interconnect layer 502 is formed on a second surface of the substrate.

In some particular embodiments, the peripheral circuitry 500 may include command decoders, address buffers, row address multiplexers, row decoders, bank control logic, column address latches, column decoders, input/output strobe circuits, data input/output buffers, and so forth. In some embodiments, the peripheral circuit may be formed using Metal-Oxide-Semiconductor (MOS) technology.

In some embodiments, the forming the peripheral circuit 500 includes:

forming a ridge structure on the second surface of the substrate, wherein an isolation structure 501 is formed between the ridge structures;

a transistor is formed on the ridge structure, the source and drain of the transistor being connected to the peripheral interconnect layer.

Here, the ridge structure may include a protrusion structure.

In addition, one or more positioning marks may be disposed on the portion of the ridge structure, where the positioning marks are used for interconnection of the peripheral circuit 500 with other device structures.

Here, the isolation structure 501 may include, but is not limited to, shallow trench isolation (STI, shallow Trench Solation)

It will be appreciated that the peripheral circuitry is coupled to the memory structure through the peripheral interconnect layer, and controls the memory array for controlling the memory cells to perform writing, reading, refreshing operations, etc. of data.

In some embodiments, the transistor is formed in a manner including: a P-well or an N-well is formed in the substrate 100 by means of diffusion, and then a source and a drain are formed in the P-well or the N-well by means of ion implantation. Next, a gate structure is formed on the surface of the corresponding doped region remote from the substrate 100, which may include, in some specific embodiments: and the protection side walls are positioned at the two sides of the grid electrode.

Then, an insulating layer covering the gate structure is formed, and next, a peripheral interconnect layer 502 connected to the gate structure and the doped region is formed in the insulating layer.

Next, step 400 is performed to mainly form a connection structure through which an electrical connection between the memory structure and the peripheral structure is achieved.

The formation of the connection structure will be described in detail with reference to fig. 6.

In some embodiments, forming the connection structure 600 includes:

after forming the memory structure and the peripheral structure, a connection structure is formed through the memory structure, the substrate, and the peripheral structure.

Specifically, a plurality of through holes penetrating through the substrate and the storage structure are formed; the plurality of through holes are filled with conductive materials respectively, and a plurality of conductive columns with one ends connected with the storage interconnection layer and one ends connected with the peripheral interconnection layer are formed respectively, so that the connection structure 600 is formed.

Here, the connection structure penetrating through the substrate, the semiconductor layer where the memory structure is located, and the dielectric layer where the peripheral structure is located may be formed by TSV technology.

Specifically, a plurality of through holes penetrating through the substrate, the semiconductor layer where the memory structure is located, and the dielectric layer where the peripheral structure is located are formed by dry etching, and the method for forming the through holes includes, but is not limited to, dry etching. Next, a conductive material is filled in each of the through holes to form a plurality of conductive pillars, and the connection structure connects the memory structure and the peripheral structure. In some embodiments, the conductive material may include a metal, such as copper (Cu), cobalt (Co), tungsten (W), molybdenum (Mo), and the like.

In other embodiments, forming the connection structure includes:

forming a storage connection structure penetrating through the storage structure and the substrate when forming the storage structure; forming a peripheral connection structure penetrating through the peripheral structure when the peripheral structure is formed; the electrically connected memory connection structure and the peripheral structure together form a connection structure.

It will be appreciated that, while the memory structure is being formed, a plurality of vias are formed in one side of the memory structure for use in making the connection structure, and each via will then also be filled with a conductive material, resulting in a memory connection structure in which the connection structure corresponds to a portion of the memory structure. Also, when the peripheral structure is formed, a peripheral connection structure of a portion of the connection structure corresponding to the peripheral structure is obtained, where the memory connection structure and the peripheral connection structure are electrically connected to form the connection structure together.

It should be noted that, when an isolation layer is present in the memory, the connection structure may penetrate through the isolation layer.

It can be appreciated that by forming the peripheral connection structures of the memory connection structures separately, the difficulty in etching the via holes is effectively reduced, thereby increasing the process window.

Next, an electrical lead-out structure is formed to connect with an external device.

In some embodiments, an electrical extraction structure is formed at a surface of the memory structure remote from the substrate or peripheral structure remote from the substrate; the memory is connected with an external device through the electric lead-out structure;

forming the electrical lead-out structure, comprising:

forming a through hole in the memory structure or the peripheral structure;

filling conductive materials in the through holes to form conductive plungers;

forming a rewiring layer on the surface of the storage structure away from the substrate or the surface of the peripheral structure away from the substrate;

and forming a welding pad on the rewiring layer.

In some specific embodiments, the memory structure is located above the peripheral structure.

It will be appreciated that the storage structure may be located above the peripheral structure to increase the density.

In some specific embodiments, an electrical extraction structure is formed at a surface of the memory structure remote from the substrate.

For example, as shown in fig. 7, the electrical lead-out structure 700 may be disposed on top of the memory for leading out components of the memory that need to be connected to external devices in order to be connected to the external devices. Here, the external device refers to an external circuit, an external device, an external system, or the like, which needs to be connected to the memory when the memory is used.

In practical application, a through hole 701 is formed in the semiconductor layer where the memory structure is located; the via 701 is filled with a conductive material to form a conductive plug, and the conductive plug 702 is used to conductively connect the rewiring layer 703 with the storage interconnect layer. The material of the conductive plunger 702 includes, but is not limited to, copper. The rewiring layer 703 is used to electrically connect the conductive plunger 702 to the pad 704. One end of the pad 704 is connected to the rewiring layer 703, and the other end is connected to an external device, and finally, electrical connection to the external device can be achieved through the pad. It can be appreciated that the position layout of the bonding pads can be made more flexible by the action of the rewiring layer.

According to another aspect of the present disclosure, embodiments of the present disclosure further provide a memory, including:

a substrate having a first surface and a second surface disposed opposite to each other in a thickness direction of the substrate;

a storage structure located on the first surface; the memory structure includes a memory array including a plurality of memory cells; each memory cell includes a write transistor and a read transistor, wherein a resistance state between a source and a drain of the read transistor is changed by the write transistor;

a peripheral structure located on the second surface;

and the connecting structure penetrates through the substrate and is electrically connected with the storage structure and the peripheral structure.

Wherein in some embodiments, the memory includes a plurality of memory structures stacked along a thickness direction of the substrate.

In some embodiments, the memory further comprises an isolation layer between two adjacent memory structures.

In some embodiments, the storage structure further comprises: a storage interconnect layer; the storage interconnection layer is positioned on the surface of the storage array, which is far away from the substrate, and is electrically connected with the storage array;

the peripheral structure includes: peripheral circuitry and peripheral interconnect layers; the peripheral circuit is positioned on the second surface; the peripheral interconnection layer is positioned on the surface of the peripheral circuit, which is far away from the substrate, and is electrically connected with the peripheral circuit;

the connection structure electrically connects the storage interconnect layer and the peripheral interconnect layer.

In some embodiments, the storage structure is located above the peripheral structure.

In some embodiments, the storage array comprises: a read word line, a read transistor, a write word line, a read bit line, and a write bit line stacked in the thickness direction of the substrate; wherein,

one of a source or a drain of the read transistor is connected to the read word line, and the remaining one of the source or the drain is connected to the read bit line;

one of a source or a drain of the write transistor is connected to a gate of the read transistor, the remaining one of the source or the drain is connected to the write bit line, and the gate is connected to the write gate.

In some embodiments, the memory further comprises an electrical extraction structure located at a surface of the memory structure or the peripheral structure remote from the substrate; the memory is connected with an external device through the electric lead-out structure;

the electrical extraction structure includes: a through hole in the memory structure or the peripheral structure; a conductive plunger located in the through hole; a rewiring layer located on a surface of the memory structure or the peripheral structure remote from the substrate; and a pad on the rewiring layer.

According to another aspect of the present disclosure, the embodiments of the present disclosure further provide a memory system, where the memory system includes a memory provided by the embodiments of the present disclosure and a memory controller connected to the memory and configured to control the memory.

In some embodiments, the memory system includes, but is not limited to, an internal memory.

The embodiment of the disclosure provides a memory, a manufacturing method thereof and a memory system, wherein the memory comprises: the memory structure is electrically connected with the peripheral structure through a connecting structure penetrating through the substrate. The memory structure includes a memory array including a plurality of memory cells, each memory cell including a write transistor and a read transistor, wherein a resistance state between a source and a drain of the read transistor is changed by the write transistor. On one hand, the storage structure and the peripheral structure are respectively arranged on the two sides of the substrate, so that the occupied area of the memory is effectively reduced, and the integration level of the memory is improved; on the other hand, the connection between the storage structure and the peripheral structure is realized through the connection structure penetrating through the substrate, so that the connection distance between the storage array and the peripheral circuit can be shortened, and the delay problem is effectively improved; in still another aspect, the memory cells in the memory array adopt a 2T0C architecture, it can be appreciated that the memory cells in the 2T0C architecture are easy to implement in a fully epitaxial manner, damage to the substrate can be reduced to improve the success rate of double-sided integration, and the charge retention time of the 2T0C architecture is longer than that of the capacitor in the conventional 1T1C architecture, so that the refresh frequency is lower, and further the memory power consumption is lower.

The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.

The present disclosure is not limited to the specific embodiments, and any person skilled in the art, who is within the technical scope of the present disclosure, can easily conceive of changes or substitutions, which are included in the scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (15)

1. A memory, comprising:

a substrate having a first surface and a second surface disposed opposite to each other in a thickness direction of the substrate;

a storage structure located on the first surface; the memory structure includes a memory array including a plurality of memory cells; each memory cell includes a write transistor and a read transistor, wherein a resistance state between a source and a drain of the read transistor is changed by the write transistor;

a peripheral structure located on the second surface;

and the connecting structure penetrates through the substrate and is electrically connected with the storage structure and the peripheral structure.

2. The memory of claim 1, wherein the memory comprises a plurality of memory structures arranged in a stack along a thickness direction of the substrate.

3. The memory of claim 2, further comprising an isolation layer between two adjacent memory structures.

4. The memory of claim 1, wherein the memory is configured to store, in the memory,

the storage structure further includes: a storage interconnect layer; the storage interconnection layer is positioned on the surface of the storage array, which is far away from the substrate, and is electrically connected with the storage array;

the peripheral structure includes: peripheral circuitry and peripheral interconnect layers; the peripheral circuit is positioned on the second surface; the peripheral interconnection layer is positioned on the surface of the peripheral circuit, which is far away from the substrate, and is electrically connected with the peripheral circuit;

the connection structure electrically connects the storage interconnect layer and the peripheral interconnect layer.

5. The memory of claim 1, wherein the memory structure is located above the peripheral structure.

6. The memory of claim 1, wherein the memory array comprises: a read word line, a read transistor, a write word line, a read bit line, and a write bit line stacked in the thickness direction of the substrate; wherein,

one of a source or a drain of the read transistor is connected to the read word line, and the remaining one of the source or the drain is connected to the read bit line;

one of a source or a drain of the write transistor is connected to a gate of the read transistor, the remaining one of the source or the drain is connected to the write bit line, and the gate is connected to the write word line.

7. The memory of claim 1, further comprising an electrical extraction structure located at a surface of the memory structure or the peripheral structure remote from the substrate; the memory is connected with an external device through the electric lead-out structure;

the electrical extraction structure includes: a through hole in the memory structure or the peripheral structure; a conductive plunger located in the through hole; a rewiring layer located on a surface of the memory structure or the peripheral structure remote from the substrate; and a pad on the rewiring layer.

8. A memory system comprising a memory as claimed in any one of claims 1 to 7; and

and the memory controller is connected with the memory and is used for controlling the memory.

9. A method of manufacturing a memory, comprising:

providing a substrate, wherein the substrate is provided with a first surface and a second surface which are oppositely arranged along the thickness direction of the substrate;

forming a storage structure on a first surface of the substrate; the storage structure includes: the memory structure includes a memory array including a plurality of memory cells; each memory cell includes a write transistor and a read transistor, wherein a resistance state between a source and a drain of the read transistor is changed by the write transistor;

forming a peripheral structure at a second surface of the substrate;

a connection structure is formed through the substrate and electrically connects the memory structure and the peripheral structure.

10. The method of manufacturing a memory device according to claim 9, wherein forming a memory structure on the first surface of the substrate comprises:

forming a plurality of storage structures stacked in a thickness direction of the substrate on the first surface, forming each storage structure, including:

forming a memory array;

and forming a storage interconnection layer on the surface of the storage array, which is far away from the substrate.

11. The method of manufacturing a memory of claim 10, further comprising:

an isolation layer is formed between two adjacent memory structures.

12. The method of manufacturing a memory of claim 10, wherein forming the memory array comprises:

sequentially forming a read word line, a read transistor, a write word line, a read bit line and a write bit line along the thickness direction of the substrate; wherein,

one of a source or a drain of the read transistor is connected to the read word line, and the remaining one of the source or the drain is connected to the read bit line;

one of a source or a drain of the write transistor is connected to a gate of the read transistor, the remaining one of the source or the drain is connected to the write bit line, and the gate is connected to the write word line.

13. The method of manufacturing a memory device according to claim 9, wherein,

forming the peripheral structure, comprising:

forming a peripheral circuit on a second surface of the substrate;

a peripheral interconnect layer is formed on a second surface of the substrate.

14. The method of manufacturing a memory according to claim 9, wherein forming the connection structure comprises:

after forming the memory structure and the peripheral structure, forming a connection structure penetrating the memory structure, the substrate and the peripheral structure;

or,

forming a storage connection structure penetrating through the storage structure and the substrate when forming the storage structure; forming a peripheral connection structure penetrating through the peripheral structure when forming the peripheral structure; the electrically connected memory connection structure and the peripheral structure together form the connection structure.

15. The method of manufacturing a memory according to claim 9, characterized in that the method further comprises:

forming an electrical lead-out structure on a surface of the memory structure remote from the substrate or the peripheral structure remote from the substrate; the memory is connected with an external device through the electric lead-out structure;

forming the electrical lead-out structure, comprising:

forming a through hole in the memory structure or the peripheral structure;

filling conductive materials in the through holes to form conductive plungers;

forming a rewiring layer on the surface of the storage structure away from the substrate or the surface of the peripheral structure away from the substrate;

and forming a welding pad on the rewiring layer.