CN117832170A - Preparation method of connection structure suitable for electronic packaging and connection structure - Google Patents

Preparation method of connection structure suitable for electronic packaging and connection structure Download PDF

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Publication number
CN117832170A
CN117832170A CN202410245397.4A CN202410245397A CN117832170A CN 117832170 A CN117832170 A CN 117832170A CN 202410245397 A CN202410245397 A CN 202410245397A CN 117832170 A CN117832170 A CN 117832170A
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layer
particle
connection structure
bump
model layer
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CN117832170B (en
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张驰
杜建宇
陈浪
石上阳
王玮
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Peking University
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Peking University
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Abstract

The application provides a preparation method of a connection structure suitable for electronic packaging and the connection structure, wherein the method comprises the following steps: depositing a seed layer on the surface of the connected substrate; spin-coating a photolithographic material on the surface-modified substrate; patterning the lithography material by lithography to form a bump template having a plurality of target areas; alternately depositing a hole model layer and a metal layer in each target region; the cavity model layer is characterized in that at least one particle body is arranged in a target area according to preset parameters; removing the cavity model layer and the bump templates, and forming at least one pore channel by at least one particle body in one-to-one correspondence to obtain a plurality of welding bumps with cavity structures; the preset parameters include at least one of particle size, particle shape, and particle gap. The prepared welding salient points relieve thermal stress generated in the high-temperature reflow welding process of the salient points and reduce the risk of disconnection of the micro salient points in a high-temperature environment.

Description

Preparation method of connection structure suitable for electronic packaging and connection structure
Technical Field
The present disclosure relates to the field of microelectronic packaging technology, and in particular, to a method for manufacturing a connection structure suitable for electronic packaging, and a connection structure.
Background
The bumps are an important ring in the packaging structure, provide necessary mechanical support for stacking chips and fixing assembly, and realize electrical interconnection between the chips and the adapter plate. The bump size is continuously reduced during the development process, from ball grid array solder balls to micro bumps used for flip-chip bonding, which are as small as 2 μm in diameter. The micro-bumps can be prepared on a large scale on the whole wafer by a photoetching plating method, so that the production efficiency is high and the batch packaging cost is reduced.
The bumps prepared at present are all solid metal micro-bumps for interconnection with a rigid substrate or chip. However, in the process of performing large-area or high-temperature welding on the solid bumps, the phenomenon of overlarge stress exists, and even the micro bumps in partial areas are disconnected, so that the electrical interconnection is invalid.
Disclosure of Invention
In view of the above problems, one of the objectives of the present invention is to provide a method for manufacturing a connection structure suitable for electronic packaging, so as to solve the problem that bump structures manufactured in current microelectronic packaging are solid bumps. The second objective of the present invention is to provide a connection structure suitable for electronic packaging, so as to alleviate thermal stress generated in the high-temperature reflow soldering process of the bump, and reduce the risk of disconnection of the micro bump in a high-temperature environment.
In order to achieve one of the purposes, the first aspect of the present invention provides a method for preparing a connection structure suitable for electronic packaging, which adopts the following technical scheme:
a method of making a connection structure suitable for electronic packaging, the method comprising:
preparing a connected substrate, and depositing a seed layer on the surface of the connected substrate;
spin-coating a photolithographic material on the surface-modified substrate;
patterning the lithography material by a lithography technique to form a bump template having a plurality of target areas;
alternately depositing a hole model layer and a metal layer in each target area; wherein the cavity model layer is characterized in that at least one particle body is arranged in the target area according to preset parameters;
and removing the cavity model layer and the bump templates, wherein at least one particle body corresponds to at least one pore channel one by one to obtain a plurality of welding bumps with cavity structures.
Optionally, the alternately depositing a hole model layer and a metal layer in each of the target areas includes:
the number of times the hole model layer is deposited in each alternation is greater than or equal to the number of times the metal layer is deposited in each alternation;
wherein the preset parameters include at least one of particle size, particle shape, and particle gap.
Optionally, before depositing the hole model layer and the metal layer alternately in each target area, the method includes:
and placing the bump template in a 3-mercapto-1-sodium propane sulfonate solution to obtain the bump template with a hydrophilic surface.
Optionally, the alternately depositing a hole model layer and a metal layer in each of the target areas includes:
the step of depositing the hole model layer comprises:
selecting the type of the particle;
dropping a plurality of particle bodies into the target area, and self-assembling to form a cavity model layer;
the step of depositing the metal layer comprises:
and electroplating metal in the target area to form a metal layer.
Optionally, the dropping the plurality of the particles into the target area, after self-assembling to form the hole model layer, includes:
transferring the connected substrate with the cavity model layer into an oven for sintering.
Optionally, the depositing a seed layer on the surface of the contacted substrate comprises:
depositing a polymer material on the seed layer;
the patterning of the photolithographic material by photolithographic techniques includes:
the polymeric material and the photolithographic material are patterned by photolithographic techniques.
Optionally, the removing the hole model layer and the bump template includes:
removing the hole model layer after completing the deposition of all the hole model layer and the metal layer; or,
removing the hole model layer after each alternating deposition of the hole model layer and the metal layer;
the removing the hole model layer and the bump template comprises the following steps:
and removing the part of the seed layer except the target area.
Optionally, the selecting the type of the particle body includes:
selecting at least one of spherical particles, elliptic particles and polyhedral particles according to the shape of the particle body; and/or the number of the groups of groups,
selecting a plurality of granules with the same particle size or different particle sizes according to the particle sizes of the granules; and/or the number of the groups of groups,
and selecting a plurality of particles forming the same gap or different gaps according to the gaps of the particles.
Optionally, the selecting the type of the particle body includes:
the particle bodies are silicon dioxide particles or polystyrene particles.
In order to achieve the second object, the second aspect of the present invention provides a connection structure suitable for electronic packaging, which adopts the following technical scheme:
a connection structure suitable for electronic packaging, the connection structure being prepared by the preparation method of the connection structure suitable for electronic packaging provided by the first aspect of the invention, the connection structure comprising: a seed layer configured to be deposited on a contacted substrate; the seed layer is connected with a plurality of welding convex points; wherein,
each welding bump is internally provided with a cavity structure, and the cavity structure comprises at least one pore canal;
and under the condition of a plurality of pore passages, the pore passages are regularly arranged in the welding convex points.
Compared with the prior art, the application has at least the following remarkable improvements:
according to the preparation method provided by the embodiment of the invention, the welding salient point with the cavity structure can be prepared, and the welding salient point has better tensile property due to the cavity structure, so that the thermal stress and thermal deformation of the porous salient point can be relieved in the large-area or high-temperature welding process, the effect of reducing the stress concentration degree is achieved, and the connection quality and performance of the welding salient point are improved;
the preparation method of the embodiment of the invention can realize high flexibility, high reliability and low cost electronic packaging, has more adaptability and flexibility, and can meet the packaging requirements under the conditions of large-area and high-temperature welding, thereby improving the stability of the mechanical property, the electrical property and the thermal property of the welding salient points;
according to the preparation method provided by the embodiment of the invention, when the welding salient point with the cavity structure is prepared, the shape, the size and the distribution of the cavity structure are controllable, the structural design and the performance optimization of the salient point can be realized, the diversification and the adjustability of the cavity structure are realized, and the application scene and the performance of the salient point bonding are improved;
according to the connecting structure provided by the embodiment of the invention, due to the characteristic that the cavity structures are arranged according to the preset parameters, the adjustable pore channel structures are beneficial to the uniform distribution of the stress of the salient points, so that the precision, the strength, the reliability and the electrical performance of the salient point bonding are improved.
Drawings
In order to more clearly illustrate the technical solutions of the present application, the drawings that are needed in the description of the present application will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings may be obtained according to these drawings without inventive effort to a person skilled in the art.
Fig. 1 is an overall structural view of a bump in the related art;
FIG. 2 is a schematic diagram illustrating an internal structure of a connection structure suitable for electronic packaging according to an embodiment of the present disclosure;
FIG. 3 is a flow chart illustrating steps of a method for fabricating a connection structure suitable for electronic packaging according to one embodiment of the present application;
FIG. 4 is a flow chart of a method for manufacturing a connection structure suitable for electronic packaging according to an embodiment of the present application;
fig. 5 is a flow chart of a method for preparing a connection structure suitable for electronic packaging according to the second embodiment of the present application;
fig. 6 is a flow chart of a method for manufacturing a connection structure suitable for electronic packaging according to the third embodiment of the present application.
Reference numerals illustrate:
100. a substrate to be joined; 1. welding the convex points; 2. a seed layer; 3. a photolithographic material; 4. a target area; 5. a cavity model layer; 6. a metal layer; 7. a duct; 8. a polymeric material.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
In microelectronic packages, bumps are three-dimensional conductive interconnection units between a chip and a substrate or chip. Bumps are typically first connected to the chip during packaging and then used to establish electrical and mechanical connections between the chip or substrate during packaging. During packaging, bumps may be first attached to the package substrate and then the chip may be attached to the bumps. So that the substrate 100 to be attached to be mentioned later may be a chip, a wafer, a substrate, a printed circuit board, or the like.
In addition, due to the gradual application of the flexible substrate and the flexible chip in recent years, the bump should keep stable connection without breaking or losing connection when the flexible substrate or the flexible chip is deformed such as bending, stretching, etc., so there is a higher standard requirement for the stretchability of the bump.
However, as shown in fig. 1, fig. 1 is an overall structural view of a bump in the related art, and the bump in the conventional art is typically a solid metal bump. There are various methods for preparing the bump, and there are vapor deposition, stencil printing, electroplating, etc. methods. For the common solid metal bump preparation process, the preparation method mainly comprises the steps of preparing a seed layer, spin-coating photoresist, photoetching and patterning a photoresist structure, and depositing a specific multilayer metal under a specific electroplating solution. The bump prepared by the method is of a solid and rigid structure, so that the phenomenon of overlarge stress and even partial region electrical interconnection failure can be caused in the process of large-area or high-temperature welding.
In view of the above, the present invention provides a method for preparing a connection structure suitable for electronic packaging, referring to fig. 3 in combination with fig. 4-6, fig. 3 shows a step flowchart of the method for preparing a connection structure suitable for electronic packaging; fig. 4-6 respectively illustrate block diagrams of steps of an exemplary preparation method according to some embodiments of the present disclosure. The method comprises the following steps:
s1, preparing a connected substrate 100, and depositing a seed layer 2 on the surface of the connected substrate 100;
in step S1, the specific type of the substrate 100 to be bonded, such as a chip, a wafer, a substrate, or a printed circuit board, is selected according to the requirements and design of the electronic package. A thin metal seed layer 2 may be deposited by deposition techniques on the process side of the substrate 100 being joined. The seed layer 2 may be a thin metal film of copper or gold, deposition techniques including, but not limited to, physical vapor deposition or atomic layer deposition.
S2, spin-coating a photoetching material 3 on the surface-modified connected substrate 100;
in step S2, the seed layer 2 in step S1 is deposited on the surface of the substrate 100 to modify the surface, and the seed layer 2 can enhance the adhesion of the surface of the substrate 100, thus providing a good foundation for the subsequent deposition of the metal layer 6, and then spin-coating the photoresist 3 on the seed layer 2. In some embodiments, deposition of the polymeric material 8 on the seed layer 2 may be continued after step S1 to modify its surface, followed by spin-coating the photolithographic material 3 on the polymeric material 8.
The photo-resist material 3 may be a photo-resist or other photosensitive organic material. Specifically, a layer of photoresist may be coated on the seed layer 2 or the polymer material 8, and pre-baking may be performed to uniformly distribute and fix the photoresist on the surface of the seed layer 2 or the polymer material 8.
S3, patterning the photoetching material 3 through a photoetching technology to form a bump template with a plurality of target areas 4;
in step S3, after depositing a photo-resist material 3 on the seed layer 2, the photo-resist material 3 is patterned by means of a photo-resist technique. In some embodiments, after polymeric material 8 and lithographic material 3 are sequentially deposited on seed layer 2, polymeric material 8 and lithographic material 3 are patterned by a photolithographic technique, i.e., polymeric material 8 is etched using lithographic material 3 as a mask.
The photolithography technique is to form a bump template having a plurality of target areas 4 by exposing and developing a pattern corresponding to the shape outline of a solder bump 1 to be prepared on a photolithographic material 3 by using light. The target area 4 is understood to be a hole with a specific shape and position formed by patterning during photolithography, the target area 4 determines the final position and shape of the solder bump 1, and in this embodiment, the bottom surface of the target area 4 is the seed layer 2 and the side surface is the photolithography material 3.
The photolithography technique is widely applied to the fields of semiconductors, microelectronics, nanotechnology and the like as a method for manufacturing patterns on photosensitive materials by utilizing light rays, and specific operation steps and principles can refer to the prior art.
S4, alternately depositing a cavity model layer 5 and a metal layer 6 in each target area 4; wherein the cavity model layer 5 is characterized in that at least one particle is arranged in the target area 4 according to preset parameters; wherein the preset parameters include at least one of particle size, particle shape and particle gap;
in step S4, hole model layers 5 and metal layers 6 may be alternately deposited within the target region 4. And the cavity model layer 5 may be formed of a plurality of particles in the target area 4 according to preset parameters. The plurality of granules are assembled in the target area 4 to form a desired structure, and since one granule corresponds to the formation of one duct 7, the arrangement according to the preset parameters helps to achieve the desired arrangement of the plurality of ducts 7 in the subsequent step.
In this embodiment, particles are deposited in the post-lithography apertures, the size and shape of the particles and the resulting gaps determining the distribution pattern of the cells 7. Wherein the size of each particle may be between a few micrometers and a few nanometers. The plurality of particles are arranged in the target area 4, a plurality of gaps are formed among the plurality of particles, after the cavity model layer 5 is deposited, metal solder is electroplated continuously, and the metal layer 6 can be obtained after the surface and the gaps of each particle are deposited and filled.
In some embodiments, the plurality of particles may be arranged according to a preset particle shape, and the particle shape may be rectangular, spherical, cylindrical, elliptical, polygonal, or irregular, so that the shape of the pore canal may be rectangular, spherical, cylindrical, elliptical, polygonal, or irregular, or the like. In some embodiments, the plurality of particles may be arranged according to a predetermined particle size, and the plurality of particles may be identically or differently arranged within the target area 4, so that it may be realized that the plurality of cells may be small, medium, large, or a combination thereof. In some embodiments, the plurality of particles may be arranged according to a predetermined particle gap, and the plurality of gaps formed by arranging the plurality of particles in the target area 4 may be the same or different, so that the gaps between the plurality of cells may be regular gaps, irregular gaps, or a combination thereof.
In an alternative embodiment, one particle may be deposited in total to form a solder bump having a single hole-cavity structure.
Therefore, the shape, the size and the distribution of the cavity structures in the welding convex points are controllable through the particles with preset parameters, the structural design and the performance optimization of the convex points are realized, the diversification and the adjustability of the cavity structures are realized, and the application scene and the performance of the convex point bonding are improved.
In some preferred embodiments, the plurality of spherical particles may form the same star-like gaps in the target area 4 with the same particle size, so that the plurality of spherical particles are regularly arranged in the target area 4, and thus a regularly arranged pore structure may be formed, so as to facilitate uniform stress distribution of the bumps, thereby improving accuracy, strength, reliability and electrical performance of bump bonding.
The hole pattern layer 5 and the metal layer 6 may be deposited alternately in such a way that the number of times the hole pattern layer 5 is deposited in each alternation is greater than or equal to the number of times the metal layer 6 is deposited in each alternation. Specifically, each deposition forms a metal layer 6 and a cavity model layer 5, and by repeating the steps, a stack of a plurality of layers of metal and a plurality of layers of cavity model layers 5 can be realized, and after the cavity model layer 5 is removed, the metal welding bump 1 with a cavity structure is finally formed.
In some embodiments, a layer-by-layer alternating pattern may be used in which the assembly of each layer of granules and the electroplating of the metal are alternately performed, i.e. one hole model layer and one metal layer constitute one alternating cycle, i.e. the number of times the hole model layer 5 is deposited in each alternation is equal to the number of times the metal layer 6 is deposited in each alternation, whereby the shape, thickness and uniformity of the portholes 7 may be controlled more precisely.
In some embodiments, a continuous deposition mode may be adopted, in which a certain number of hole model layers 5 may be deposited, and then a certain number of metal layers 6 may be deposited, that is, N layers of hole model layers and M layers of metal layers form an alternating period, where N is a positive integer greater than or equal to M, and neither is zero, that is, the number of times of depositing the hole model layers 5 in each alternation is greater than the number of times of depositing the metal layers 6 in each alternation, so that the deposition speed may be increased.
As an example of this implementation, a layer-by-layer alternating pattern may be employed in a cycle, i.e., after all the granules are assembled, metal plating is finally performed; or a plurality of cycles are adopted to circularly complete the assembly of all the particles and the metal plating.
As an example of the present embodiment, in the continuous deposition mode, two metal layers 6 are deposited every three hole model layers 5 are deposited, or one metal layer 6 is deposited every two hole model layers 5 are deposited. Or after alternately depositing every third time, adding a hole model layer 5; or after every fourth alternate deposition, one metal layer 6 is reduced.
It will be appreciated that one hole model layer 5 is obtained per deposition. The particle shape, particle size and particle gap in each cavity model layer 5 may be the same or different during the deposition multiple times. It will also be appreciated that the number of particles deposited once in each cavity model layer 5 may be the same or different.
It will be appreciated that one metal layer 6 is obtained per deposition. The thickness and material of each metal layer 6 in the plurality of metal layers 6 may be the same or different during the deposition process.
As a specific explanation of the present embodiment, the order of first depositing the cavity model layer 5 and the metal layer 6 may be arbitrarily selected, but finally the metal layer 6 should be deposited so as to encapsulate the subsequent vias 7 inside the solder bump 1.
As a further explanation of the present embodiment, the shape, size and position of each pellet determines the shape, size and position of each cell 7, while affecting the filling effect of the metal layer 6 and the characteristics of the cavity structure. The size of each particle determines the amount of deposition of the particle in each cycle. Wherein, each particle body can be spherical microsphere or elliptic microsphere, which is micron-sized diameter, and the distribution density can be varied from sparse to dense.
In some embodiments, one particle may be deposited, ultimately forming a single-hole cavity structure; in some embodiments, a plurality of particles may be deposited, ultimately forming a porous hole structure. In some embodiments, the number, shape, size of the granules of each hole model layer 5 in the multi-layer hole model layer 5 may be the same or different; in some embodiments, the thickness and material of each metal layer 6 of the plurality of metal layers 6 may be the same or different, and the thickness and material of each metal layer 6 may be adjusted by plating parameters and solder.
S5, removing the cavity model layer 5 and the bump templates, and forming at least one pore channel 7 by at least one particle body in one-to-one correspondence to obtain a plurality of welding bumps 1 with cavity structures.
In step S4, after the arrangement of the cavity model layer 5 and the metal layer 6 is determined, the bump templates and bump templates are removed, leaving a porous bump structure or a single-hole bump structure with metal solder as a main body. Wherein the bump template is the other part except the target area 4. In the case of depositing the photoresist material 3 on the seed layer 2, the other part is photoresist, which is removed using an organic solution. In case the polymer material 8 and the photo-resist material 3 are deposited sequentially on the seed layer 2, the other parts are photo-resist and the polymer material 8. In some embodiments, in the case of photoresist and polymeric material 8, the photoresist may be removed prior to step S4, and then step S4 may be performed within target region 4 after photoresist removal, with either dry or solution removal to remove polymeric material 8.
After removal of the photoresist or polymer material 8, the etching of each pellet is completed using an organic solution, so that the space occupied by the original pellet becomes the pore 7, forming a porous hole structure or a single-hole structure.
In this embodiment, after each alternate period is completed, the hole model layer 5 may be removed, then deposition in the next alternate period may be continued, and finally all of the hole model layer 5 may be removed in a stepwise dissolution manner. The hole model layer 5 may be removed after all the alternating cycles are completed, that is, after all the hole model layer 5 and the metal layer 6 are deposited.
Finally, the remaining portion of the seed layer 2 may be removed using an etching solution or ion beam etching method corresponding to the seed layer 2, resulting in a plurality of solder bumps 1 having a cavity structure.
Therefore, as the metal bumps provided and prepared by the invention have the adjustable porous structure, when the micro bump bonding is used between the chip and the flexible substrate or between the chip and another chip with poorer surface flatness, the porous structure is compressed, so that the bump structure can be more attached to the surface of the flexible substrate or the chip, and better electrical interconnection is realized.
Due to the adoption of the design of the porous structure in the convex points, when the packaging body using the technology is subjected to external impact or vibration load, the load can be effectively absorbed, so that the bonding is more reliable.
When the size of the bump is reduced to a micro bump of the order of tens of micrometers, it is possible to avoid a situation in which electrical interconnection of a partial region cannot be completed due to thermal deformation of the substrate during the process of soldering the chip.
Most importantly, the size, shape, arrangement and packing fraction of the granules determine the distribution, density and shape size of the cells 7. Alternate deposition allows the structure to be built layer by layer, the distribution and density of pore channels 7 of each layer can be accurately controlled in each deposition process, the pore size and shape of the porous structure can be accurately controlled, the structural design and performance optimization of the salient points can be realized, the diversification and adjustability of the hole structure are realized, and therefore the application scene and performance of the salient point bonding are improved.
In addition, the size and type of the different particles and the electroplating conditions of the metal layer 6 can be selected, and the alternate layered deposition provides high customization of the porous structure, so that the prepared solder bump 1 can be more suitable for different packaging and bonding requirements.
As a further explanation of the present embodiment, the properties of the target region 4 and the properties of the pellet themselves can be controlled to improve the self-assembly condition of the pellet. Specifically, step S4 further includes:
in step S41, the organic matter on the surface of the seed layer 2 is removed by oxygen plasma dry cleaning.
And step S42, placing the cleaned bump template in a 3-mercapto-1-propane sodium sulfonate solution to obtain the bump template with a hydrophilic surface.
In step S42, the bump template after the cleaning in step S41 may be soaked in a solution of sodium 3-mercapto-1-propane sulfonate, so that the seed layer 2 is hydrophilic. So that the seed layer 2 on the bottom surface in the target area 4 is more suitable for self-assembly of the particle bodies after cleaning and surface modification in sequence.
And/or;
s43, selecting the type of the particle body;
in step S43, the type of granules may be selected based on preset parameters based on the desired cell structure. Selecting at least one of spherical particles, elliptic particles and polyhedral particles, for example, according to the shape of the particle body; and/or selecting a plurality of granules with the same particle size or different particle sizes according to the particle sizes of the granules; and/or selecting a plurality of particles forming the same gap or different gaps according to the gaps of the particles. Selecting a plurality of granules with the same particle size or different particle sizes according to the particle sizes of the granules; and/or selecting a plurality of particles forming the same gap or different gaps according to the gaps of the particles.
In addition, the type of the particle body can be selected based on the consideration of self-assembly conditions. The self-assembly condition of the particle body is determined by the physical and chemical properties of the contact surface and the properties of the particle body. Therefore, after modifying the contact surface in step S42, if the seed layer 2 is made hydrophilic, the particle bodies may be spherical particles, and the spherical particles may be selected, and due to the surface tension, the particles may spontaneously arrange on the surface of the hydrophilic seed layer 2 to form a close-packed structure, so as to obtain the hole model layer 5 in regular arrangement.
Further, the particle bodies are silica particles or polystyrene particles.
In some embodiments, the particle may be surface modified to have hydrophilic properties to further facilitate self-assembly.
Step S44, dropping a plurality of particles into the target area 4, and self-assembling to form a cavity model layer 5;
in step S44, after the specific type of the particle is selected, the particle is then dropped onto the surface of the seed layer 2 in the target area 4, and after the moisture in the particle evaporates to dry, the particle completes its self-assembly process.
Further, step S44 includes, after:
step S45, transferring the connected substrate 100 with the hole model layer 5 into an oven for sintering.
And (3) placing the connected substrate 100 obtained in the step S44 into an oven for sintering, and setting the temperature regulation range and the baking time of the oven. During sintering, the granules soften and deform at high temperatures, so that adjacent granules form a continuous cavity model layer 5. And taking out after sintering is finished, and electroplating the metal layer 6 of the next layer.
Step S46, electroplating metal in the target area 4 to form a metal layer 6.
In step S46, electroplating may be continued in the target area 4 where the cavity model layer 5 is formed, and the metal body of the solder bump 1 is gradually formed, and the electroplating solution may be copper, gold, tin or other electroplating material. Specifically, the substrate 100 is immersed in a plating bath, the substrate 100 is used as a working electrode, and metal ions on the anode are deposited on the surface and in the gaps of the microspheres by reduction through current driving. In this embodiment, parameters of the plating such as current density, temperature, plating time, etc. may be controlled to control the rate and thickness of metal deposition.
In this embodiment, the thickness of the metal deposition should be greater than the thickness of the photoresist to ensure the formation of the bumps.
In combination with the above embodiments, the solder bump 1 prepared by the preparation method provided in the embodiments of the present application has a number of significant improvements, and improves the performance of the conventional connection structure, so as to adapt to different electronic packaging application requirements. With continued reference to fig. 2, fig. 2 is a schematic diagram illustrating an internal structure of a connection structure suitable for electronic packaging according to the present invention. The invention also provides a connection structure suitable for electronic packaging, which is prepared by the preparation method of the connection structure suitable for electronic packaging, and comprises a seed layer 2, wherein the seed layer 2 is configured to be deposited on a connected substrate 100; a plurality of welding convex points 1 are connected to the seed layer 2; wherein, each welding bump 1 is internally provided with a cavity structure, and the cavity structure comprises at least one pore canal 7; in the case of a plurality of the holes 7, the holes 7 are regularly arranged in the solder bump 1.
Specifically, the outer edge profile of the solder bump 1 may be spherical, cylindrical or other shape. The shape of the outer edge profile may be formed by high temperature reflow soldering of metallic solder. The internal structure of the solder bump 1 having a cavity structure is understood to be that at least one hole 7 is formed in the metal bump.
In some embodiments, the metal bump may have a hole 7 therein, and the hole 7 may be a hole, a void, or a cavity. The size of the pore canal 7 can be micro-scale or nano-scale, the shape can be rectangular, spherical, cylindrical, elliptic, polygonal or special-shaped, and the like, and a single pore canal 7 is arranged inside the welding convex point 1 to form a single-hole cavity structure. In some embodiments, at least two regularly arranged holes 7 can be formed in the metal bump, and the sizes and shapes of the holes 7 can be the same or different; and each pore canal 7 can be in a micro-scale or nano-scale, and is preferably in a sphere shape, and the sphere pore canals 7 are arranged in a certain sequence, mode or geometry inside the welding convex points 1 to form a porous cavity structure arranged according to preset parameters.
The shape and size of the hole 7 may be set according to the shape and size of the solder bump 1, and the present embodiment is not limited thereto.
Thus, compared with the traditional solid metal bump, the porous welding bump 1 provided by the embodiment of the invention has the pore canal 7, and the pore canal 7 can relieve the thermal stress and thermal deformation generated in the welding process of the bump, so that the stress concentration degree is reduced, the risk of micro bump disconnection in a high-temperature environment is reduced, the reliability and stability of the bump are improved, and the connection quality and performance of the bump are further improved.
The multiple pore channels 7 in the porous cavity structure are arranged according to preset parameters, namely the pore diameter, shape and distribution of the pore channels can be regulated and controlled, and the pore channels are not limited by the structural characteristics of the material of the metal solder, so that the porous cavity structure is particularly suitable for the scene requiring high precision and repeatability in the microelectronic packaging application. In addition, through the preset shoveling of the control pore channels, a plurality of pore channels 7 can be arranged in a regular arrangement, the surface area is more optimized, the uniform distribution of the pore channels 7 is beneficial to the uniform distribution of stress of the salient points, the thermal stress and the thermal fatigue of the salient points are reduced, and the bonding reliability is improved.
In summary, the metal bump of the embodiment of the invention has better stretchability due to the special single-hole structure or the multi-hole structure, and maintains stable connection without breaking or losing connection when the flexible substrate and the flexible chip adapt to deformation such as bending, stretching and the like, thereby meeting the special application scene of the flexible electronic device.
Embodiments of the present invention will be fully described below with reference to the accompanying drawings.
Embodiment one:
with continued reference to fig. 4, a method for preparing a connection structure suitable for electronic packaging includes:
firstly, a layer of copper seed layer 2 film is deposited on the technological surface of the chip through a physical vapor deposition technology. Photoresist is coated on the seed layer 2 in a spin mode, and then the photoresist is patterned through a photoetching technology to obtain a bump template. And removing organic matters on the surface of the seed layer 2 by using an oxygen plasma dry cleaning mode. After the completion of the washing, it was immersed in 6ml of a sodium 3-mercapto-1-propanesulfonate solution for 2 hours to make the seed layer 2 hydrophilic. And then, dripping the polystyrene particles on the surface of the seed layer 2 in the target area 4 of the bump template, and completing the self-assembly process of the polystyrene particles in the target area 4 after the water of the polystyrene particles is automatically evaporated to be dry. Then placing the mixture into an oven for sintering, wherein the temperature regulation range of the oven is set at 100-120 ℃, and the baking time is set at 15-30 min. Transferring the sintered metal into electroplating solution after sintering, and electroplating in a three-electrode system (counter electrode: copper, reference electrode: silver chloride, working electrode: bump template) to form a first layer of metal; the self-assembly process described above is then continued in the holes and the electroplating of the second metal layer 6 is continued, and so on, alternately deposited to the desired hole model layer 5 and metal layer 6.
After the preparation of the metal layer 6 is completed, the photoresist is removed using an organic solution, and the etching of the polystyrene particles is completed, thereby forming the solder bump 1 having a porous hole structure. The remaining portion of the seed layer 2 is then removed using a corresponding etching solution or ion beam etching method of the seed layer 2.
Embodiment two:
with continued reference to fig. 5, a method for preparing a connection structure suitable for electronic packaging includes:
firstly, a copper seed layer 2 film is formed on the technological surface of the chip through an atomic layer deposition technology. A layer of organic polymer material 8 is grown on the wafer, followed by spin coating of a photoresist, after which the photoresist is patterned by means of a photolithographic technique, the polymer material 8 is etched using the photoresist as a mask, and the photoresist is removed, resulting in a bump template. And removing organic matters on the surface of the seed layer 2 by using an oxygen plasma dry cleaning mode. After the completion of the washing, it was immersed in 6ml of a sodium 3-mercapto-1-propanesulfonate solution for 2 hours to make the seed layer 2 hydrophilic. And then, the silicon dioxide particles are dripped on the surface of the seed layer 2 in the target area 4 of the bump template, and after the moisture in the silicon dioxide particles is automatically evaporated to be dry, the self-assembly process of the silicon dioxide particles is completed in the target area 4. Then placing the mixture into an oven for sintering, wherein the temperature regulation range of the oven is set at 100-120 ℃, and the baking time is set at 15-30 min. Transferring the sintered metal into electroplating solution after sintering, and electroplating in a three-electrode system (counter electrode: copper, reference electrode: silver chloride, working electrode: bump template) to form a first layer of metal; the self-assembly process described above is then continued in the holes and the electroplating of the second metal layer 6 is continued, and so on, alternately deposited to the desired hole model layer 5 and metal layer 6.
After the preparation of the metal layer 6 is completed, the polymer material 8 is removed using a dry removal technique, and the etching of the silicon dioxide particles is completed, thereby forming the solder bump 1 having a porous cavity structure. The remaining portion of the seed layer 2 is then removed using a corresponding etching solution or ion beam etching method of the seed layer 2.
Embodiment III:
with continued reference to fig. 6, a method for preparing a connection structure suitable for electronic packaging includes:
firstly, a layer of copper seed layer 2 film is deposited on the process surface of a wafer through a physical vapor deposition technology. Spin-coating photoresist on the wafer, and then patterning the photoresist by a photolithography technique to obtain a bump template. And removing organic matters on the surface of the seed layer 2 by using an oxygen plasma dry cleaning mode. After the completion of the washing, it was immersed in 6ml of a sodium 3-mercapto-1-propanesulfonate solution for 2 hours to make the seed layer 2 hydrophilic. And then, dripping the polystyrene particles on the surface of the seed layer 2 in the target area 4 of the bump template, and completing the self-assembly process of the polystyrene particles in the target area 4 after the water of the polystyrene particles is automatically evaporated to be dry. Then placing the mixture into an oven for sintering, wherein the temperature regulation range of the oven is set at 100-120 ℃, and the baking time is set at 15-30 min. After sintering, the metal layer is transferred into electroplating solution, and electroplating is carried out in a three-electrode system (counter electrode: copper, reference electrode: silver chloride, working electrode: bump template) to form a metal layer 6.
After the preparation of the metal layer 6 is completed, the photoresist is removed using an organic solution, and the etching of the polystyrene particles is completed, thereby forming the solder bump 1 having a porous hole structure. The remaining portion of the seed layer 2 is then removed using a corresponding etching solution or ion beam etching method of the seed layer 2.
It should be noted that, in the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described as different from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It should also be noted that, in the present document, the terms "upper", "lower", "left", "right", "inner", "outer", etc. indicate an orientation or a positional relationship based on that shown in the drawings, and are merely for convenience of describing the present invention and simplifying the description, and do not indicate or imply that the apparatus or element to be referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present invention. Moreover, relational terms such as "first" and "second" may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions, or order, and without necessarily being construed as indicating or implying any relative importance. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal.
The above description is provided for describing in detail a method for manufacturing a connection structure suitable for electronic packaging and a connection structure, and specific examples are applied to illustrate the principles and embodiments of the present application, and the description of the above examples is only for aiding in understanding the present application, and the disclosure should not be construed as limiting the present application. Also, various modifications in the details and application scope may be made by those skilled in the art in light of this disclosure, and all such modifications and variations are not required to be exhaustive or are intended to be within the scope of the disclosure.

Claims (10)

1. A method of making a connection structure suitable for use in electronic packaging, the method comprising:
preparing a connected substrate, and depositing a seed layer on the surface of the connected substrate;
spin-coating a photolithographic material on the surface-modified substrate;
patterning the lithography material by a lithography technique to form a bump template having a plurality of target areas;
alternately depositing a hole model layer and a metal layer in each target area; wherein the cavity model layer is characterized in that at least one particle body is arranged in the target area according to preset parameters;
removing the cavity model layer and the bump templates, wherein at least one particle body corresponds to at least one pore channel one by one to obtain a plurality of welding bumps with cavity structures;
wherein the preset parameters include at least one of particle size, particle shape, and particle gap.
2. The method of manufacturing a connection structure for electronic packaging according to claim 1, wherein alternately depositing a hole model layer and a metal layer in each of the target areas comprises:
the number of times the hole model layer is deposited in each alternation is greater than or equal to the number of times the metal layer is deposited in each alternation.
3. The method of manufacturing a connection structure for electronic packaging according to claim 1, wherein before alternately depositing a hole model layer and a metal layer in each of the target areas, the method comprises:
and placing the bump template in a 3-mercapto-1-sodium propane sulfonate solution to obtain the bump template with a hydrophilic surface.
4. A method of fabricating a connection structure for electronic packaging according to any one of claims 1-3, wherein said alternately depositing a hole model layer and a metal layer in each of said target areas comprises:
the step of depositing the hole model layer comprises:
selecting the type of the particle;
dropping a plurality of particle bodies into the target area, and self-assembling to form a cavity model layer;
the step of depositing the metal layer comprises:
and electroplating metal in the target area to form a metal layer.
5. The method for manufacturing a connection structure for electronic packaging according to claim 4, wherein the dropping the plurality of particles into the target region, after self-assembling, comprises:
transferring the connected substrate with the cavity model layer into an oven for sintering.
6. The method of claim 1, wherein the depositing a seed layer on the surface of the substrate comprises:
depositing a polymer material on the seed layer;
the patterning of the photolithographic material by photolithographic techniques includes:
the polymeric material and the photolithographic material are patterned by photolithographic techniques.
7. The method for manufacturing a connection structure for electronic packaging according to claim 1 or 6, wherein the removing the hole model layer and the bump template comprises:
removing the hole model layer after completing the deposition of all the hole model layer and the metal layer; or,
removing the hole model layer after each alternating deposition of the hole model layer and the metal layer;
the removing the hole model layer and the bump template comprises the following steps:
and removing the part of the seed layer except the target area.
8. The method of claim 4, wherein selecting the type of the particle comprises:
selecting at least one of spherical particles, elliptic particles and polyhedral particles according to the shape of the particle body; and/or the number of the groups of groups,
selecting a plurality of granules with the same particle size or different particle sizes according to the particle sizes of the granules; and/or the number of the groups of groups,
and selecting a plurality of particles forming the same gap or different gaps according to the gaps of the particles.
9. The method of claim 4, wherein selecting the type of the particle comprises:
the particle bodies are silicon dioxide particles or polystyrene particles.
10. A connection structure suitable for electronic packaging, characterized in that the connection structure is prepared by the preparation method of the connection structure suitable for electronic packaging according to any one of claims 1 to 9, the connection structure comprising: a seed layer configured to be deposited on a contacted substrate; the seed layer is connected with a plurality of welding convex points; wherein,
each welding bump is internally provided with a cavity structure, and the cavity structure comprises at least one pore canal;
and under the condition of a plurality of pore passages, arranging the pore passages in the welding convex points according to preset parameters.
CN202410245397.4A 2024-03-05 2024-03-05 Preparation method of connection structure suitable for electronic packaging and connection structure Active CN117832170B (en)

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CN114551389A (en) * 2020-11-25 2022-05-27 英特尔公司 Porous FLI bumps for reducing bump thickness variation sensitivity for bump pitch scaling
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JP2003174055A (en) * 2001-12-06 2003-06-20 Asahi Kasei Corp Fine pattern connection circuit part and method for forming the same
KR20120112172A (en) * 2011-03-30 2012-10-11 도쿄엘렉트론가부시키가이샤 Method for manufacturing semiconductor device
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