CN117807932A - Automatic clock switching logic circuit - Google Patents
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Abstract
The invention discloses an automatic clock switching logic circuit, which relates to the technical field of digital circuit logic design and aims to solve the problem that a chip cannot be started due to a main clock fault. The device comprises a main clock, a standby clock, a reference clock, a clock detection device and a clock switching device; the input end of the clock detection device is connected with the main clock and the reference clock; the output end of the clock detection device is connected with the first end of the clock switching device; the second end of the clock switching device is connected with the master clock, and the third end of the clock switching device is connected with the reference clock; the second end receives the periodic signal input by the main clock, and the third end receives the periodic signal input by the reference clock; when the chip executes starting work, the clock detection device detects the fault condition of the main clock based on the periodic signal input by the main clock and the periodic signal input by the reference clock; the clock switching device switches between the main clock and the standby clock based on the level input from the clock detecting device. The invention is used for automatically identifying and switching the faults of the master clock.
Description
Technical Field
The invention relates to the technical field of digital circuit logic design, in particular to an automatic clock switching logic circuit.
Background
With the development of the integrated circuit industry, the required integration level of the chip is higher and higher. When the chip starts to work, a master clock is needed, and after the chip works normally, different clock sources are selected through software control.
In the current chip system design, the clock design and the process problems have defects, but the clock quality is rarely monitored in the system, and the clock fault condition can occur, although the existing system designs the switchable clock, the identification and the automatic switching of the clock fault are not supported, and the clock source is required to be manually switched, so that when the main clock of the chip in the prior art is in fault, other clock sources cannot be automatically switched, and the system cannot be started normally.
Disclosure of Invention
The invention aims to provide an automatic clock switching logic circuit which is used for solving the problem that a chip cannot be started normally due to a main clock fault in the traditional chip system.
In order to achieve the above object, the present invention provides the following technical solutions:
a clock automatic switching logic circuit, comprising: the device comprises a main clock, a standby clock, a reference clock, a clock detection device and a clock switching device;
the input end of the clock detection device is connected with the master clock and the reference clock; the output end of the clock detection device is connected with the first end of the clock switching device; the second end of the clock switching device is connected with the master clock, and the third end of the clock switching device is connected with the reference clock; the second end receives the periodic signal input by the main clock, and the third end receives the periodic signal input by the reference clock;
when the chip executes starting work, the clock detection device detects the fault condition of the main clock based on the periodic signal input by the main clock and the periodic signal input by the reference clock; the clock switching device is used for switching the main clock and the standby clock based on the level input by the clock detection device.
Optionally, when the clock detection device outputs a high level, the clock switching device switches the master clock to the standby clock; when the clock detection device outputs low level, the clock switching device controls the master clock to execute the starting work of the chip; when the output of the clock detection device is turned from high level to low level, the clock switching device switches the standby clock back to the main clock.
Optionally, when the number of cycles of the master clock does not meet the cycle condition of the reference clock, the clock detection device outputs a high level, and the clock switching device switches the master clock to the standby clock.
Optionally, when the number of the periods of the master clock meets the period condition of the reference clock, the clock detection device outputs a low level, and the clock switching device controls the master clock to work.
Optionally, the circuit further comprises a chip starter; the input end of the chip starter is connected with the output end of the clock switching device; the chip starter is used for controlling the chip to start based on the output of the clock switching device.
Optionally, the clock detection device comprises a frequency divider, a counter, a comparator and an encoder;
the input end of the frequency divider is connected with the master clock, and the output end of the frequency divider is connected with the input end of the counter; the output end of the counter is connected with the comparator; the frequency divider is used for dividing the frequency of the main clock and obtaining the divided period of the main clock; the counter is used for counting the number of the divided periods of the main clock.
Optionally, the clock detection device further comprises an encoder; the input end of the encoder is connected with the output end of the comparator; the comparator is used for judging whether the number of the periods is between the lower limit of the preset detection window and the upper limit of the preset detection window;
when the number of the periods falls between the lower limit of the preset detection window and the upper limit of the preset detection window, the comparator controls the encoder to output a low level; and when the number of the periods does not fall between the lower limit of the preset detection window and the upper limit of the preset detection window, the comparator controls the encoder to output a high level.
Optionally, the output end of the encoder is connected with the clock switching device; when the encoder outputs a low level, the clock switching device controls the master clock to work.
Optionally, when the encoder outputs a high level, the clock switching device switches the master clock to the standby clock.
Optionally, the master clock is a built-in clock of the chip; the standby clock is an external clock of the chip.
Compared with the prior art, the clock automatic switching logic circuit provided by the invention comprises: the device comprises a main clock, a standby clock, a reference clock, a clock detection device and a clock switching device; the input end of the clock detection device is connected with the master clock and the reference clock; the output end of the clock detection device is connected with the first end of the clock switching device; the second end of the clock switching device is connected with the master clock, and the third end of the clock switching device is connected with the reference clock; the second end receives the periodic signal input by the main clock, and the third end receives the periodic signal input by the reference clock; when the chip executes starting work, the clock detection device detects the fault condition of the main clock based on the periodic signal input by the main clock and the periodic signal input by the reference clock; the clock switching device is used for switching the main clock and the standby clock based on the level input by the clock detection device. According to the invention, the clock detection device, the clock switching device and the reference clock are added, the clock detection device is used for detecting the periodic signal of the main clock used when the chip is started based on the periodic signal of the reference clock, and the clock detection device is used for sending out the level corresponding to the fault condition based on the fault condition of the main clock, so that the clock switching device is used for switching the main clock and the standby clock based on the received level, the automatic identification and switching of the fault of the main clock are achieved, the chip can be started normally, and the problem that the chip cannot be started normally due to the fault of the main clock is solved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:
fig. 1 is a schematic diagram of an automatic clock switching logic circuit according to the present invention.
Detailed Description
In order to clearly describe the technical solution of the embodiments of the present invention, in the embodiments of the present invention, the words "first", "second", etc. are used to distinguish the same item or similar items having substantially the same function and effect. For example, the first threshold and the second threshold are merely for distinguishing between different thresholds, and are not limited in order. It will be appreciated by those of skill in the art that the words "first," "second," and the like do not limit the amount and order of execution, and that the words "first," "second," and the like do not necessarily differ.
In the present invention, the words "exemplary" or "such as" are used to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "for example" should not be construed as preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "such as" is intended to present related concepts in a concrete fashion.
In the present invention, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b or c may represent: a, b, c, a and b, a and c, b and c, or a, b and c, wherein a, b, c can be single or multiple.
With the development of integrated circuit industry, cost control is higher and higher, and functional requirements of hardware matching are integrated into a chip, so that the chip integration level is higher and higher. Under the background, the clock crystal function of the single board is integrated into the chip to realize, and an external clock crystal pin is reserved for meeting the requirement of higher precision.
The chip is started to work by using an internal clock, and software can control and select different clock sources (internal or external) after normal work, so that the clock sources are switched by the software in the prior art: when the system is in a working state after the system is successfully started, the multi-clock path is controlled through software operation to perform clock switching, and software operation after the system is started is required for the existing clock switching.
However, the built-in clock has defects (such as overlarge frequency deviation and even no work) due to design and process problems, and the built-in clock cannot be used for starting in the process that the system needs to be started, so that the chip cannot be started.
Based on the above-mentioned problems, the present invention provides a clock automatic switching logic circuit capable of automatically identifying a clock state when a chip system is started and automatically switching a standby clock when an abnormal state is identified, and the technical scheme of the present application will be described with reference to the accompanying drawings:
as shown in fig. 1, the present invention provides an automatic clock switching logic circuit, comprising: the device comprises a main clock, a standby clock, a reference clock, a clock detection device and a clock switching device;
the input end of the clock detection device is connected with the master clock and the reference clock; the output end of the clock detection device is connected with the first end of the clock switching device; the second end of the clock switching device is connected with the master clock, and the third end of the clock switching device is connected with the reference clock; the second end receives the periodic signal input by the main clock, and the third end receives the periodic signal input by the reference clock;
when the chip executes starting work, the clock detection device detects the fault condition of the main clock based on the periodic signal input by the main clock and the periodic signal input by the reference clock; the clock switching device is used for switching the main clock and the standby clock based on the level input by the clock detection device.
Specifically, the master clock is the clock used by the chip to perform the start-up operation, and the frequency and phase of the master clock signal are usually called the system clock and are determined by the design requirements of the chip. The standby clock is a standby clock when the chip executes starting operation, and when the main clock fails, the normal starting of the chip system can be ensured through the standby clock. Meanwhile, the reference clock is a clock signal for synchronous data transmission, is one of the most important clock signals in the whole system, is usually provided by an external clock source, and is usually used with a central frequency point of 10 MHz-30 MHz.
The clock detection device (Clock Failure Detector, CFD) is a detection device for detecting the state of the master clock in real time and detecting whether the master clock fails in real time, a detection threshold can be set for the clock detection device based on the design requirement of the chip, and the clock detection device (Clock Failure Detector, CFD) judges whether the state of the master clock meets the detection threshold and outputs whether the master clock fails. The clock switching device is a device for controlling the switching of the main clock and the standby clock.
The invention connects the input end of the clock detection device with the main clock and the reference clock, the output end of the clock detection device is connected with the first end of the clock switching device, the second end of the clock switching device is connected with the main clock, the third end of the clock switching device is connected with the reference clock, the second end receives the periodic signal input by the main clock, and the third end receives the periodic signal input by the reference clock. When the chip executes starting work, a clock detection device (Clock Failure Detector, CFD) detects the fault condition of the main clock based on the period signal input by the main clock and the period signal input by the reference clock, outputs the corresponding level, outputs the level condition of the main clock to a clock switching device, and switches the main clock and the standby clock through the clock switching device.
As an alternative embodiment, when the clock detection device outputs a high level, the clock switching device switches the master clock to the standby clock; when the clock detection device outputs low level, the clock switching device controls the master clock to execute the starting work of the chip; when the output of the clock detection device is turned from high level to low level, the clock switching device switches the standby clock back to the main clock.
Specifically, when the system is started, the clock detection device (Clock Failure Detector, CFD) uses the reference clock to dynamically detect whether the master clock is abnormal: when the clock detection device (Clock Failure Detector, CFD) detects that the main clock fails, a high level is output, and at the moment, the clock switching device switches the main clock into the standby clock and controls the standby clock to execute the starting work of the chip so as to enable the chip to start normally; when the clock detection device (ClockFailure Detector, CFD) detects that the main clock is not invalid, a low level is output, and at the moment, the clock switching device controls the main clock to execute the starting work of the chip, so that the chip is started normally.
When the master clock is initially disabled, the clock detection device (ClockFailure Detector, CFD) initially detects that the master clock is disabled, when the master clock is disabled again after the failure of the master clock is repaired, the clock detection device (Clock Failure Detector, CFD) can detect that the master clock is not disabled again, at this time, the output of the clock detection device (Clock Failure Detector, CFD) is turned from high level to low level, the clock switching device switches the standby clock back to the master clock, and the chip is started normally by executing the starting work of the master clock. Therefore, the invention does not need software operation, but ensures that the internal master clock of the chip is abnormally and automatically switched to the external standby clock by the automatic detection and automatic switching of the logic of the system, and ensures that the chip can be started normally.
Meanwhile, after the chip system is successfully started, when the system is in a working state, the software can be flexibly configured, any clock can be detected through the software, and meanwhile, the switching of any clock can be performed through the software control of multiple clock paths.
As an alternative embodiment, when the number of cycles of the master clock does not meet the cycle condition of the reference clock, the clock detection device outputs a high level, and the clock switching device switches the master clock to the standby clock.
Specifically, if the clock detection means (ClockFailure Detector, CFD) counts using the 2048 divided clock of the master clock 1/2, when the reference clock is 32KHz and the master clock is 20MHz, the period after the frequency division of the master clock 2048 is 102us; when the reference clock period is 31us and the number of periods counted by the clock detection device (Clock Failure Detector, CFD) is 3, the number of periods of the main clock meets the period condition of the reference clock, the main clock is considered to be not invalid, at the moment, the clock detection device (Clock Failure Detector, CFD) outputs a low level, and at the moment, the clock switching device controls the main clock to execute the starting work of the chip, so that the chip is started normally.
Meanwhile, since the master clock and the reference clock have precision problems, the number of the periods counted by the clock detection device (Clock Failure Detector, CFD) can be set to an upper limit and a lower limit according to the precision, and the number of the periods counted by the clock detection device (ClockFailure Detector, CFD) exceeds a preset upper limit or does not reach a preset lower limit, so that the number of the periods of the master clock does not meet the period condition of the reference clock, and the master clock is considered to be invalid. The number of cycles counted by the clock detection device (Clock Failure Detector, CFD) is set to an upper limit and a lower limit according to the accuracy, and the master clock is considered not to be disabled only within the upper limit and the lower limit, so that a user can flexibly set the upper limit and the lower limit in the clock detection device (Clock Failure Detector, CFD) based on the design requirement of the chip.
As an optional implementation manner, when the number of cycles of the master clock meets the cycle condition of the reference clock, the clock detection device outputs a low level, and the clock switching device controls the master clock to work.
Specifically, if the number of cycles of the master clock counted by the clock detection device (Clock Failure Detector, CFD) is within a preset lower limit and upper limit, it means that the number of cycles of the master clock satisfies the cycle condition of the reference clock, for example, the clock detection device (ClockFailure Detector, CFD) counts using the 2048-divided clock of 1/2 of the master clock, and when the reference clock is 32KHz and the master clock is 20MHz, the cycle after the 2048-division of the master clock is 102us; when the reference clock period is 31us and the number of periods counted by the clock detection device (Clock Failure Detector, CFD) is 3, the number of periods of the main clock meets the period condition of the reference clock, the main clock is considered to be not invalid, at the moment, the clock detection device (Clock Failure Detector, CFD) outputs a low level, and at the moment, the clock switching device controls the main clock to execute the starting work of the chip, so that the chip is started normally.
As an alternative embodiment, the circuit further comprises a chip initiator; the input end of the chip starter is connected with the output end of the clock switching device; the chip starter is used for controlling the chip to start based on the output of the clock switching device.
Specifically, the clock automatic switching logic circuit of the invention further comprises a chip starter, the input end of the chip starter is connected with the output end of the clock switching device, if the clock detection device (Clock Failure Detector, CFD) detects that the main clock is normal, the clock switching device does not need to switch the standby clock, the main clock signal is directly transmitted to the following chip starter, and the chip starter can be designed based on the requirement of a user and can be used as any module required by chip design.
Meanwhile, if the clock detection device (Clock Failure Detector, CFD) detects that the main clock is abnormal, the clock switching device automatically switches to the standby clock, and the standby clock signal is transmitted to the chip starter at the back, so that the chip starter can be designed based on the user requirement and can be used as any module required by the chip design, and the universality of the clock automatic switching logic circuit is greatly improved.
And after the chip system is started by the selected clock, the clock can be continuously switched by the software later, and the clock is used as a clock switching scheme for abnormal occurrence in the working process of the chip. Therefore, the clock automatic switching logic circuit can realize clock switching when the chip works abnormally and clock switching when the chip starts abnormally.
As an alternative embodiment, the clock detection device includes a frequency divider, a counter, a comparator, and an encoder;
the input end of the frequency divider is connected with the master clock, and the output end of the frequency divider is connected with the input end of the counter; the output end of the counter is connected with the comparator; the frequency divider is used for dividing the frequency of the main clock and obtaining the divided period of the main clock; the counter is used for counting the number of the divided periods of the main clock.
Specifically, the frequency divider divides and removes the ac signal according to a preset requirement, and in the digital circuit, the frequency divider is used for performing frequency division operation on a clock with a higher frequency to obtain a signal with a lower frequency. The counting is the simplest basic operation, the counter is a logic circuit for realizing the operation, and the counter is mainly used for counting the number of pulses in a digital system so as to realize the functions of measurement, counting and control. The comparison of two or more data items to determine whether they are equal or to determine the magnitude relationship and the order of arrangement between them is referred to as a comparison, and a circuit or device capable of performing such a comparison function is referred to as a comparator, which is a circuit comparing an analog voltage signal with a reference voltage, the two inputs of the comparator being analog signals, the output being binary signals 0 or 1, the output of which remains constant when the difference between the input voltages increases or decreases and the sign does not change. An encoder (encoder) is a device that converts an electrical pulse signal into a corresponding digital signal.
The clock detection device (ClockFailure Detector, CFD) comprises a frequency divider, a counter, a comparator and an encoder, wherein the input end of the frequency divider is connected with the main clock, the output end of the frequency divider is connected with the input end of the counter, the output end of the counter is connected with the comparator, the frequency divider is used for dividing the main clock and obtaining the divided period of the main clock, and the counter is used for counting the number of the divided period of the main clock.
For example, the clock detection device (Clock Failure Detector, CFD) counts using the 2048 divided clock of the master clock 1/2. The counter is cleared at the beginning of each master clock cycle (i.e., at the end of the previous cycle). At the end of each main clock cycle, a counter (CFDCNT) counts and stores the count value in a sampling counter (CFDCNTLOCK) at this time, indicating that the detection is ended. The cycle is repeated until the value in CFDCNTLOCK is greater than the value of the upper detection window limit (cfdwordop) or the value in CFDCNTLOCK is less than the value of the lower detection window limit (cfdwordow). At this time, the CFD outputs a Clock Cycle fail (Clk-fail) hardware signal to the Clock switch, which switches to the reference Clock output if the Clk-fail output is high, otherwise, to the master Clock output.
In particular, the 2048 divider is a counter composed of 11-bit registers, and each time the output is turned over to 1024, the CFDCNT counts in the period of 2048 division of the main clock, and at the end of each main clock period, the count value is stored in the CFDCNTLOCK; CFDWORDTOP is the upper detection window limit and CFDWORDLOW is the lower detection window limit. A Comparator (COMPARE) COMPAREs CFDCNTLOCK with cfdwordop and CFDWORDLOW and converts the comparison result into a Clk-fail signal, if the Clk-fail output is high, the master clock fails; for example, the reference clock is 32KHz, and the master clock is 20MHz; the period after the frequency division of the master clock 2048 is 102us; the reference clock period is 31us, the normal CFDCNT count is 3, but the precision problem exists in both the main clock and the reference clock, so CFDWORDTOP and CFDWORDLOW can set an upper limit and a lower limit according to the precision, and only within the range, the clock is considered not to be invalid.
As an alternative embodiment, the clock detection apparatus further comprises an encoder; the input end of the encoder is connected with the output end of the comparator; the comparator is used for judging whether the number of the periods is between the lower limit of the preset detection window and the upper limit of the preset detection window;
when the number of the periods falls between the lower limit of the preset detection window and the upper limit of the preset detection window, the comparator controls the encoder to output a low level; and when the number of the periods does not fall between the lower limit of the preset detection window and the upper limit of the preset detection window, the comparator controls the encoder to output a high level.
Specifically, the input end of the encoder (encoder) is connected with the output end of the Comparator (COMPARE); the Comparator (COMPARE) is used for judging whether the number of the periods is between a preset detection window lower limit and a preset detection window upper limit; when the number of the periods falls between the lower limit of the preset detection window and the upper limit of the preset detection window, the comparator controls the encoder to output a low level, and at the moment, the clock switching device controls the master clock to execute the starting work of the chip, so that the chip is started normally; when the period number does not fall between the lower limit of the preset detection window and the upper limit of the preset detection window, the comparator controls the encoder to output high level, and at the moment, the clock switching device switches the main clock into the standby clock and controls the standby clock to execute the starting work of the chip, so that the chip is started normally.
As an alternative embodiment, the output end of the encoder is connected with the clock switching device; when the encoder outputs a low level, the clock switching device controls the master clock to work.
Specifically, an output terminal of an encoder (encoder) is connected to the clock switching device. When the encoder outputs low level, the clock switching device controls the master clock to work, namely, the clock switching device controls the master clock to execute the starting work of the chip, so that the chip is started normally.
As an alternative embodiment, the clock switching means switches the master clock to the standby clock when the encoder outputs a high level.
Specifically, when the encoder outputs a high level, the clock switching device switches the master clock to the standby clock, that is, the clock switching device switches the master clock to the standby clock, and controls the standby clock to execute the start-up work of the chip, so that the chip is started normally.
As an alternative embodiment, the master clock is a built-in clock of the chip; the standby clock is an external clock of the chip.
Specifically, the clock crystal function of the single board is integrated into the chip, so that an external clock crystal pin is reserved for meeting the requirement of higher precision, therefore, a main clock used for starting the chip is an internal clock, after normal operation, software can control and select different clock sources (internal or external), when the internal crystal is abnormal, the clock is automatically switched to a standby clock, namely the external clock, the chip can start the operation normally, and the problem that the chip cannot start normally due to the failure of the internal clock is solved. In addition, the detection circuit does not need a controller, a frequency dividing circuit and the like, and the circuit structure is simpler.
Although the invention is described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed invention, from a study of the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
Although the invention has been described in connection with specific features and embodiments thereof, it will be apparent that various modifications and combinations can be made without departing from the spirit and scope of the invention. Accordingly, the specification and drawings are merely exemplary illustrations of the present invention as defined in the appended claims and are considered to cover any and all modifications, variations, combinations, or equivalents that fall within the scope of the invention. It will be apparent to those skilled in the art that various modifications and variations can be made to the present invention without departing from the spirit or scope of the invention. Thus, it is intended that the present invention also include such modifications and alterations insofar as they come within the scope of the appended claims or the equivalents thereof.
Claims (10)
1. An automatic clock switching logic circuit, comprising: the device comprises a main clock, a standby clock, a reference clock, a clock detection device and a clock switching device;
the input end of the clock detection device is connected with the master clock and the reference clock; the output end of the clock detection device is connected with the first end of the clock switching device; the second end of the clock switching device is connected with the master clock, and the third end of the clock switching device is connected with the reference clock; the second end receives the periodic signal input by the main clock, and the third end receives the periodic signal input by the reference clock;
when the chip executes starting work, the clock detection device detects the fault condition of the main clock based on the periodic signal input by the main clock and the periodic signal input by the reference clock; the clock switching device is used for switching the main clock and the standby clock based on the level input by the clock detection device.
2. The automatic clock switching logic circuit according to claim 1, wherein said clock switching means switches said master clock to said standby clock when said clock detection means outputs a high level; when the clock detection device outputs low level, the clock switching device controls the master clock to execute the starting work of the chip; when the output of the clock detection device is turned from high level to low level, the clock switching device switches the standby clock back to the main clock.
3. The automatic clock switching logic circuit according to claim 1, wherein the clock detection means outputs a high level when the number of cycles of the master clock does not satisfy the cycle condition of the reference clock, and the clock switching means switches the master clock to the standby clock.
4. The automatic clock switching logic circuit according to claim 1, wherein the clock detection means outputs a low level when the number of cycles of the master clock satisfies the cycle condition of the reference clock, and the clock switching means controls the master clock to operate.
5. The automatic clock switching logic of claim 1, wherein the circuit further comprises a chip initiator; the input end of the chip starter is connected with the output end of the clock switching device; the chip starter is used for controlling the chip to start based on the output of the clock switching device.
6. The automatic clock switching logic of claim 1, wherein the clock detection means comprises a frequency divider, a counter, a comparator, and an encoder;
the input end of the frequency divider is connected with the master clock, and the output end of the frequency divider is connected with the input end of the counter; the output end of the counter is connected with the comparator; the frequency divider is used for dividing the frequency of the main clock and obtaining the divided period of the main clock; the counter is used for counting the number of the divided periods of the main clock.
7. The automatic clock switching logic of claim 6, wherein the clock detection means further comprises an encoder; the input end of the encoder is connected with the output end of the comparator; the comparator is used for judging whether the number of the periods is between the lower limit of the preset detection window and the upper limit of the preset detection window;
when the number of the periods falls between the lower limit of the preset detection window and the upper limit of the preset detection window, the comparator controls the encoder to output a low level; and when the number of the periods does not fall between the lower limit of the preset detection window and the upper limit of the preset detection window, the comparator controls the encoder to output a high level.
8. The automatic clock switching logic of claim 7, wherein the output of the encoder is coupled to the clock switching device; when the encoder outputs a low level, the clock switching device controls the master clock to work.
9. The automatic clock switching logic of claim 8, wherein the clock switching means switches the master clock to the standby clock when the encoder outputs a high level.
10. The automatic clock switching logic circuit of claim 1, wherein the master clock is a built-in clock of the chip; the standby clock is an external clock of the chip.
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| CN202311712753.0A CN117807932A (en) | 2023-12-13 | 2023-12-13 | Automatic clock switching logic circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN118393968A (en) * | 2024-06-24 | 2024-07-26 | 杭州胜金微电子有限公司 | Clock detection and control circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN118393968A (en) * | 2024-06-24 | 2024-07-26 | 杭州胜金微电子有限公司 | Clock detection and control circuit |
| CN118393968B (en) * | 2024-06-24 | 2024-09-13 | 杭州胜金微电子有限公司 | Clock detection and control circuit |
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