CN117807930A

CN117807930A - Chip simulation method, device and equipment

Info

Publication number: CN117807930A
Application number: CN202311855630.2A
Authority: CN
Inventors: 赵海丞; 巩冬梅
Original assignee: Spreadtrum Communications Shanghai Co Ltd
Current assignee: Spreadtrum Communications Shanghai Co Ltd
Priority date: 2023-12-28
Filing date: 2023-12-28
Publication date: 2024-04-02

Abstract

The embodiment of the application provides a chip simulation method, device and equipment, wherein the method comprises the following steps: determining a simulation model corresponding to a target chip, wherein the target chip comprises a plurality of functional modules, and the simulation model comprises sub-simulation models corresponding to each functional module; for any sub-simulation model, initial data is read from a read storage space corresponding to the sub-simulation model; processing the initial data through the combination logic corresponding to the sub-simulation model to obtain target data, and writing the target data into a writing storage space corresponding to the sub-simulation model; and after the total time delay corresponding to the sub-simulation model, informing the next sub-simulation model of the sub-simulation model to read the target data in the write storage space. According to the method, the pipeline structure of each functional module in the software simulation of the target chip can be realized through the simulation model, so that the writing and modification processes of the combinational logic in the pipeline structure are simplified, and the efficiency of the chip software simulation is improved.

Description

Chip simulation method, device and equipment

Technical Field

The embodiment of the application relates to the technical field of computers, in particular to a chip simulation method, a device and equipment.

Background

In chip (e.g., computationally accelerated chip) design, the performance and efficiency of the chip may be improved by software simulation of the chip. In software simulation of a chip, functional modules (e.g., computing modules) in the chip are typically designed in a pipeline structure to improve data throughput, improve computing unit utilization, and reduce overall computation delay.

In the related art, a designer obtains in advance the correspondence between each function in each functional module and each stage of pipeline, writes the combinational logic of each stage of pipeline in each functional module according to the correspondence, and designs the pipeline structure of each functional module based on the combinational logic of each stage of pipeline.

However, the method in the related art is complicated in writing the combinational logic of each stage of pipeline in each functional module, and when the pipeline stage number or time delay in the functional module changes, the combinational logic of each stage of pipeline needs to be rewritten, so that the efficiency of the chip software simulation is low.

Disclosure of Invention

The embodiment of the application provides a chip simulation method, device and equipment, which are used for solving the problem of low efficiency of chip software simulation in the related technology.

In a first aspect, an embodiment of the present application provides a chip simulation method, including:

determining a simulation model corresponding to a target chip, wherein the target chip comprises a plurality of functional modules, and the simulation model comprises sub-simulation models corresponding to each functional module;

for any sub-simulation model, initial data is read from a read storage space corresponding to the sub-simulation model;

processing the initial data through combinational logic corresponding to the sub-simulation model to obtain target data, and writing the target data into a writing storage space corresponding to the sub-simulation model;

and after the total time delay corresponding to the sub-simulation model, notifying the next sub-simulation model of the sub-simulation model to read the target data in the write storage space.

In one possible implementation manner, the reading initial data from the read storage space corresponding to the sub-simulation model includes:

after the reading cooperative program corresponding to the sub-simulation model is awakened, judging whether the initial data exists in the reading storage space or not;

if yes, reading the initial data in the read storage space through the read cooperative program;

if not, suspending the reading auxiliary program, and waking up the reading auxiliary program after a preset time period until the initial data exists in the reading storage space, and reading the initial data in the reading storage space through the reading auxiliary program.

In one possible implementation manner, after the initial data is read in the read storage space through the read co-program, the method further includes:

adding 1 to the writable space of the read storage space; the method comprises the steps of,

the readable space of the read storage space is decremented by 1.

In one possible implementation manner, writing the target data into a write storage space corresponding to the sub-simulation model includes:

after the write cooperative program corresponding to the sub-simulation model is awakened, judging whether the available space exists in the write storage space or not;

if yes, writing the target data into the writing storage space through the writing cooperative program;

if not, suspending the write auxiliary program, and waking up the write auxiliary program after a preset time period until the available space exists in the write storage space, and writing the target data into the write storage space through the write auxiliary program.

In one possible implementation manner, after the target data is written into the write storage space through the write cooperative, the method further includes:

subtracting 1 from the writable space of the write storage space; the method comprises the steps of,

and adding 1 to the readable space of the write storage space.

In one possible implementation manner, after the total delay corresponding to the sub-simulation model, notifying the next sub-simulation model of the sub-simulation model to read the target data in the write storage space includes:

Determining the total time delay corresponding to the sub-simulation model, wherein the total time delay is the time delay of a functional module corresponding to the sub-simulation model;

waiting for the total time delay, and after the total time delay, determining a next sub-simulation model of the sub-simulation model;

sending a read notification message to the next sub-simulation model, wherein the read notification message is used for indicating the next sub-simulation model to read the target data in a read storage space of the sub-simulation model; and the read storage space of the next sub-simulation model is the same as the write storage space of the sub-simulation model.

In a possible implementation manner, the size of the write memory space is the same as the pipeline stage number of the functional module corresponding to the sub-simulation model.

In a second aspect, an embodiment of the present application provides a chip emulation apparatus, including:

the determining module is used for determining a simulation model corresponding to a target chip, wherein the target chip comprises a plurality of functional modules, and the simulation model comprises sub-simulation models corresponding to each functional module;

the reading module is used for reading initial data from a reading storage space corresponding to any sub-simulation model;

The processing module is used for processing the initial data through the combination logic corresponding to the sub-simulation model to obtain target data;

the writing module is used for writing the target data into a writing storage space corresponding to the sub-simulation model;

and the notification module is used for notifying the next sub-simulation model of the sub-simulation model to read the target data in the write storage space after the total time delay corresponding to the sub-simulation model.

In one possible implementation, the reading module is specifically configured to:

In a possible implementation manner, after the initial data is read in the read storage space through the read co-program, the reading module is specifically further configured to:

the readable space of the read storage space is decremented by 1.

In one possible implementation manner, the writing module is specifically configured to:

In one possible implementation manner, after the target data is written into the write storage space through the write cooperative, the writing module is specifically further configured to:

and adding 1 to the readable space of the write storage space.

In one possible implementation manner, the notification module is specifically configured to:

In a third aspect, the present application provides a chip having a computer program stored thereon, which, when executed by the chip, implements the method according to any of the first aspects.

In a fourth aspect, the present application provides a chip module having a computer program stored thereon, which, when executed by the chip module, implements a method according to any of the first aspects.

In a fifth aspect, an embodiment of the present application provides a chip emulation device, including:

at least one processor; and

A memory communicatively coupled to the at least one processor; wherein,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of the first aspects.

In a sixth aspect, embodiments of the present application provide a computer-readable storage medium having stored therein computer-executable instructions for performing the method of any one of the first aspects when the computer-executable instructions are executed by a processor.

In a seventh aspect, embodiments of the present application provide a computer program product comprising a computer program which, when executed by a processor, implements the method of any of the first aspects.

The chip simulation method, the device and the equipment provided by the embodiment of the application can determine the simulation model corresponding to the target chip, wherein the target chip comprises a plurality of functional modules, and the simulation model comprises sub-simulation models corresponding to each functional module; for any sub-simulation model in the simulation models, initial data can be read from a read storage space corresponding to the sub-simulation model; processing the initial data through the combination logic corresponding to the sub-simulation model to obtain target data, and writing the target data into a writing storage space corresponding to the sub-simulation model; and after the total time delay corresponding to the sub-simulation model, notifying the next sub-simulation model of the sub-simulation model to read target data in the write storage space. According to the method, the pipeline structure of each functional module in the software simulation of the target chip can be realized through the simulation model, so that the writing and modification processes of the combinational logic in the pipeline structure are simplified, and the efficiency of the chip software simulation is improved.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

Fig. 1 is a schematic diagram of a pipeline structure of a chip in the related art according to an embodiment of the present application;

FIG. 2 is a schematic structural diagram of a simulation model according to an embodiment of the present disclosure;

fig. 3 is a schematic flow chart of a chip simulation method according to an embodiment of the present application;

FIG. 4 is a flowchart of another chip simulation method according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a specific working process of a simulation model in a chip simulation process according to an embodiment of the present application;

FIG. 6 is a schematic timing diagram of simulation model implementation when each functional module continuously reads data according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a chip simulation device according to an embodiment of the present application;

fig. 8 is a schematic structural diagram of a chip simulation device according to an embodiment of the present application.

Specific embodiments thereof have been shown by way of example in the drawings and will herein be described in more detail. These drawings and the written description are not intended to limit the scope of the inventive concepts in any way, but to illustrate the concepts of the present application to those skilled in the art by reference to specific embodiments.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples are not representative of all implementations consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with some aspects of the present application as detailed in the accompanying claims.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

It should be noted that, the data (including, but not limited to, data for analysis, stored data, displayed data, etc.) referred to in the present application are all information and data authorized by the user or fully authorized by each party, and the collection, use and processing of the related data need to comply with the related laws and regulations and standards, and provide corresponding operation entries for the user to select authorization or rejection.

In the following, terms related to embodiments of the present application are explained.

C System (System C): an open source C++ class library for hardware and system-level design provides various simulation, verification, and debugging tools that help designers build hardware models and system-level models at a higher level of abstraction. System C can be used in a variety of applications, for example, system C can be used in applications such as semiconductor chip design, embedded System design, and communication network design.

In System C, the System time is divided into time of day and instant. The operation of the system is first divided into discrete time steps, each time step being called a moment, each moment being further divided into countless delta instants, each delta instant being further subdivided into an execute (eval) phase, an update (update) phase and a notification (notify) phase.

The operating flow of System C is as follows: (1) Environment initialization. (2) Starting running from the current time t, and in an execution (eval) stage of the time t, recovering the cooperative programs to be executed at the time t one by one. (3) In the update (update) phase at time t, the values/states of the System C port and the signals are updated. (4) And (3) notifying the events occurring in the steps (2) - (3) at the notification (notify) stage of the time t, and adding the coroutines waiting for the corresponding events into a coroutine queue to be executed according to the preset recovery time. (5) Acquiring the latest to-be-executed coroutine from a coroutine queue to be executed, if the recovery time of the coroutine is still within the time t (namely, the recovery time is t+ndelta), updating t into t+ndelta, and repeating the steps (2) - (5); if the recovery time of the coroutine is more than or equal to t+1 (i.e. the recovery time is t+n), updating t to t+n and repeating the steps (2) - (5); if there is no coroutine to be executed, the operation is ended.

In order to improve the performance and efficiency of a chip (e.g., a compute acceleration chip), functional modules in the chip are typically designed as a pipeline structure. In the related art, a designer obtains in advance the correspondence between each function in each functional module in a chip and each stage of pipeline, writes the combinational logic of each stage of pipeline in each functional module according to the correspondence, and designs the pipeline structure of each functional module based on the combinational logic of each stage of pipeline.

For ease of understanding, the pipeline structure of each computing module of the chip in the related art will be described with reference to fig. 1.

Fig. 1 is a schematic diagram of a pipeline structure of a chip in the related art according to an embodiment of the present application. Referring to fig. 1, the pipeline structure of the chip includes 3 functional modules, namely a functional module a, a functional module B and a functional module C, wherein:

the functional module A is a 3-stage pipeline, and 3 triggers (flip-flop) are arranged in the functional module A; the functional module B is a 2-stage pipeline, and 2 triggers (flip-flop) are arranged in the functional module B; the functional module C is a 1-stage pipeline, and 1 trigger (flip-flop) is arranged in the functional module C.

Total time delay of each functional module: representing the time delay from the first input data entering the first stage pipeline of each functional module to the first output data exiting the last stage pipeline of each functional module. The total delay of function module a is 3 clock cycles, the total delay of function module B is 2 clock cycles, and the total delay of function module C is 2 clock cycles.

Referring to fig. 1, each trigger in each functional module can implement independent enabling and gradual back pressure.

Independently enable: indicating that each flip-flop has an independent enable signal (typically EN or ENA) for turning on or off the function. When the enable signal is high level, the function is started; when the enable signal is low, the function is turned off.

Step-by-step back pressure: in a logic circuit composed of multiple stages, each stage has a control signal for suspending the operation of the previous stage. When the stage cannot complete the task, the control signal can be set and reversely transferred to the previous stage of the stage, so that the previous stage is suspended, and errors caused by data coverage in the whole circuit are prevented.

However, referring to fig. 1, the combinational logic of each stage of pipeline in each functional module in the related art is complex, and when the number of pipeline stages or the time delay in the functional module changes, the combinational logic of each stage of pipeline needs to be rewritten, resulting in lower efficiency of chip software simulation. Therefore, in the electronic system level design, for a functional module including a pipeline, a simulation model that is simple, convenient, high in abstraction level, and easy to implement is needed to improve the efficiency of chip software simulation on the basis of ensuring accurate functions and timing.

In view of this, the embodiment of the present application provides a chip simulation method, which may determine a simulation model corresponding to a target chip, where the target chip includes a plurality of functional modules, and the simulation model includes a sub-simulation model corresponding to each functional module; for any sub-simulation model in the simulation models, initial data can be read from a read storage space corresponding to the sub-simulation model; processing the initial data through the combination logic corresponding to the sub-simulation model to obtain target data, and writing the target data into a writing storage space corresponding to the sub-simulation model; and after the total time delay corresponding to the sub-simulation model, notifying the next sub-simulation model of the sub-simulation model to read target data in the write storage space. According to the method, the pipeline structure of each functional module in the software simulation of the target chip can be realized through the simulation model, the writing and modifying processes of the combinational logic in the pipeline structure are simplified, and the efficiency of the chip software simulation is improved.

In order to facilitate understanding, the structure of the simulation model provided in the embodiment of the present application will be described below with reference to fig. 2.

Fig. 2 is a schematic structural diagram of a simulation model according to an embodiment of the present application. Referring to fig. 2, the simulation model includes a target chip and a simulation model corresponding to the target chip, the target chip includes 3 functional modules, and the simulation model includes a sub-simulation model corresponding to each functional module. The sub-simulation model A simulates a 3-stage pipeline of the functional module A and total time delay of 3 clock cycles corresponding to the functional module A, the sub-simulation model B simulates a 2-stage pipeline of the functional module B and total time delay of 2 clock cycles corresponding to the functional module B, and the sub-simulation model C simulates a 1-stage pipeline of the functional module C and total time delay of 1 clock cycle corresponding to the functional module C.

Each sub-simulation model may correspond to a read memory space and a write memory space. For any sub-simulation model, the sub-simulation model can read initial data from a read storage space corresponding to the sub-simulation model, and process the initial data through combinational logic corresponding to the sub-simulation model to obtain target data. The sub-simulation model can also write the target data into a write storage space corresponding to the sub-simulation model.

The write memory space corresponding to the sub-simulation model may be the read memory space corresponding to the next sub-simulation model of the sub-simulation model. For example, the write memory space a corresponding to the sub-simulation model a is the read memory space B of the next sub-simulation model B of the sub-simulation model a.

The chip simulation method, the device and the equipment provided by the embodiment of the application can be used in the software simulation process of a chip (such as a calculation acceleration chip). It should be noted that, the chip simulation method, the device and the equipment provided in the embodiments of the present application may be used in the field of computer technology, and may also be used in any field other than the field of computer technology.

The method shown in the present application will be described below by way of specific examples. It should be noted that the following embodiments may exist alone or in combination with each other, and for the same or similar content, the description will not be repeated in different embodiments.

Fig. 3 is a flow chart of a chip simulation method according to an embodiment of the present application. Referring to fig. 3, the method may include:

the execution body of the embodiment of the application can be chip simulation equipment, or can be a chip, a chip module, a chip simulation device or the like arranged in the chip simulation equipment. The chip simulation device can be realized by software or a combination of software and hardware.

S301, determining a simulation model corresponding to the target chip.

The target chip can comprise a plurality of functional modules, and the simulation model comprises a sub-simulation model corresponding to each functional module.

For example, in fig. 1, the target chip may include 3 functional modules, and 3 sub-simulation models are included in the simulation models, where functional module a corresponds to sub-simulation model a, functional module B corresponds to sub-simulation model B, and functional module C corresponds to sub-simulation model C.

Alternatively, the simulation model may be implemented based on an existing open source library. For example, the simulation model may be implemented based on a common method of System C.

S302, for any sub-simulation model, initial data are read from a read storage space corresponding to the sub-simulation model.

Alternatively, the size of the read storage space may be the same as the pipeline number of the functional module corresponding to the sub-simulation model. The read memory space may be constructed by at least one fifo (First Input First Output, fifo), and may include M fifos, M being a positive integer, assuming that the pipeline stages of the functional modules corresponding to the sub-simulation model are M stages.

S303, processing the initial data through the combination logic corresponding to the sub-simulation model to obtain target data, and writing the target data into a writing storage space corresponding to the sub-simulation model.

Optionally, the size of the write storage space is the same as the pipeline stage number of the functional module corresponding to the sub-simulation model. The write memory space may be constructed by at least one fifo (First Input First Output, fifo), and may include M fifos, M being a positive integer, assuming that the pipeline stages of the functional modules corresponding to the sub-simulation model are M stages.

Optionally, assuming that the pipeline stage number of the functional module a corresponding to the sub-simulation model a is M stages, where M is a positive integer, the functional logic of each stage of the M stage pipeline of the functional module a may be combined together to determine an equivalent logic corresponding to the simulation model a. The input of the combinational logic is consistent with the input of the first stage pipeline of the functional module A, and the output of the combinational logic is consistent with the output of the last stage pipeline of the functional module A. In the sub-simulation model A, the pipeline stages and the functional logic are decoupled, all the functional logic in the functional module A can be written together after being combined, for the intermediate process between the first-stage pipeline and the M-stage pipeline, the combination logic does not need to be written in sequence according to the pipeline sequence, and the corresponding relation between each function and each stage of pipeline does not need to be determined in advance, so that redundant details which are not concerned when the chip system-level simulation is introduced are avoided, the writing and modifying process of the combination logic is simpler and more convenient when the pipeline structure of the functional module A is simulated, and the development and maintenance cost of the combination logic is reduced.

Optionally, the initial data may be read from the write storage space corresponding to the sub-simulation model by a preset write (write) method.

S304, after the total time delay corresponding to the sub-simulation model, notifying the next sub-simulation model of the sub-simulation model to read target data in the write storage space.

Assuming that the total time delay corresponding to the sub-simulation model is x, if the sub-simulation model writes the target data into the write storage space corresponding to the sub-simulation model at the time t, notifying the next sub-simulation model of the sub-simulation model to read the target data in the write storage space at the time t+x.

According to the chip simulation method provided by the embodiment of the application, the pipeline structure of each functional module in the software simulation of the target chip can be realized through the simulation model, the writing and modifying processes of the combinational logic in the pipeline structure are simplified, the development and maintenance cost in the chip software simulation process is reduced, and the efficiency of the chip software simulation is improved.

Fig. 4 is a flow chart of another chip simulation method according to an embodiment of the present application. Referring to fig. 4, the method may include:

S401, determining a simulation model corresponding to the target chip.

Note that, the specific execution process of S401 may refer to the specific execution process of S301, and will not be described herein.

Optionally, for any sub-simulation model, the following steps S402 to S404 may be referred to and executed to read initial data from the read storage space corresponding to the sub-simulation model.

S402, judging whether initial data exists in the read storage space after the read protocol corresponding to the sub-simulation model is awakened.

If yes, go to step S403;

if not, step S404 is performed.

S403, reading initial data in a read storage space through a read protocol.

Optionally, the initial data may be read from the read storage space corresponding to the sub-simulation model by a preset read method.

S404, suspending the reading co-procedure, and waking up the reading co-procedure after a preset time period until the initial data exists in the reading storage space, and reading the initial data in the reading storage space through the reading co-procedure.

The preset duration may be, for example, one clock cycle.

After the initial data is read in the read memory space by the read co-program, the method may further include step S405:

s405, adding 1 to the writable space of the read storage space, and subtracting 1 from the readable space of the read storage space.

S406, processing the initial data through combinational logic corresponding to the sub-simulation model to obtain target data.

Note that, the specific execution process of S406 may refer to the specific execution process of S303, and will not be described herein.

Alternatively, for any one sub-simulation model, steps S407 to S409 may be referred to and executed as shown below, so as to write target data into the write storage space corresponding to the sub-simulation model.

S407, judging whether available space exists in the write storage space after the write cooperative program corresponding to the sub-simulation model is awakened.

If yes, go to step S408;

if not, step S409 is performed.

S408, writing target data into the write storage space through the write cooperative program.

Optionally, the target data may be written into the write storage space corresponding to the sub-simulation model by a preset write (read) method.

S409, suspending the write auxiliary program, and waking up the write auxiliary program after a preset time period until the available space exists in the write storage space, and writing target data into the write storage space through the write auxiliary program.

S410, subtracting 1 from the writable space of the write storage space, and adding 1 to the readable space of the write storage space.

S411, determining the total time delay corresponding to the sub-simulation model.

The total time delay can be the time delay of the functional module corresponding to the sub-simulation model. For example, in fig. 2, the total delay for sub-simulation model a is 3 clock cycles.

S412, waiting for the total time delay, and after the total time delay, determining the next sub-simulation model of the sub-simulation model.

For example, assuming that in fig. 2, the total delay corresponding to the sub-simulation model B is 2 clock cycles, after 2 clock cycles, the sub-simulation model C following the sub-simulation model B is notified to notify the sub-simulation model C to read data from the read storage space of the sub-simulation model B.

S413, sending a read notification message to the next sub-simulation model.

The read notification message may be used to instruct the next sub-simulation model to read the target data in the read storage space of the sub-simulation model; the read storage space of the next sub-simulation model is the same as the write storage space of the sub-simulation model.

For example, in FIG. 2, the next sub-simulation model of sub-simulation model A is B, and the read memory space of sub-simulation model A is the same as the write memory space of sub-simulation model B.

According to the chip simulation method provided by the embodiment of the application, the pipeline structure of each functional module in the software simulation of the target chip can be realized through the simulation model, the writing and modifying processes of the combinational logic in the pipeline structure are simplified, and the efficiency of the chip software simulation is improved.

In order to facilitate understanding of the chip simulation method provided in the embodiments of the present application, a specific working process of a simulation model in a chip simulation process is described below with reference to fig. 5.

Fig. 5 is a schematic diagram of a specific working process of a simulation model in a chip simulation process according to an embodiment of the present application. Referring to fig. 5, the simulation model includes a target chip and simulation models corresponding to the target chip, the target chip includes 3 functional modules, and the simulation models include sub-simulation models corresponding to each functional module.

Each sub-simulation model corresponds to a read storage space and a write storage space respectively. 5 processing modules can be included in each sub-simulation model: the device comprises a reading processing module, a combination logic processing module, a writing processing module, a waiting processing module and a judging processing module. The processing functions of each processing module will be described below.

1. Read processing module (read)

And the read processing module (read) is used for reading the initial data from the read storage space of each sub-simulation model. The read storage space may be fifo, and illustratively, the port type of fifo may be the port type of System C.

For any sub-simulation model, the read processing module (read) may be specifically configured to: assuming that a read method is operated at the moment t, reading initial data from a read storage space (fifo) corresponding to the sub-simulation model through a read cooperative program in an execution (eval) stage at the moment t; a writable space +1 of the read storage space (fifo) and a readable space-1 of the read storage space (fifo) are to be read in an update (update) phase at time t; in the notification (notify) phase at time t, a read event (fifo_read) for reading the memory space is immediately notified, and the coroutine waiting on the read event is awakened in the execution (eval) phase at time t+Δ.

The read processing module (read) may be further configured to, in an execution (eval) stage at time t, if no data is found to be readable (a readable space of the read storage space < =0) when the data is read from the read storage space (fifo) by the read co-procedure, suspend the read co-procedure until there is initial data writing in the read storage space (fifo), so that when there is initial data in the read storage space (fifo), read the initial data in the read storage space by the read co-procedure.

2. Combinational logic processing module

And the combinational logic processing module is used for processing the initial data read by the read processing module through combinational logic to obtain target data.

3. Write processing module (write)

And the write processing module (write) is used for writing target data into the write storage space of each sub-simulation model through a write cooperative program. The write memory space may be fifo, and illustratively, the port type of fifo may be the port type of System C.

For any sub-simulation model, assuming that the write method is running at time t, the write processing module (write) may be specifically configured to: writing data in a write memory space (fifo) corresponding to the simulation model of the write protocol Cheng Xiangzi in an execution (eval) stage at the time t; writable space-1 to be written to memory space (fifo) at update (update) stage at time t; if the total time delay corresponding to the sub simulation model is x, a write memory space update (fifo_write_update) event is delayed by x times for notification in a notification (notify) stage at time t. At the execution (eval) phase at time t+x, waiting for a coroutine on a write memory update (fifo_write_update) event to be awakened; the update (update) phase at time t+x will write the readable space +1 of the memory space (fifo); immediately notifying a write event (fifo_write) for writing a memory space in a notification (notify) stage at time t+x; during the execution (eval) phase at time t+x+Δ, the protocol Cheng Hui waiting on the write event is awakened.

The write processing module (write) may be further configured to, in an execution (eval) phase at time t, if no writable space (writable space < =0 of the write storage space) is found when writing target data into the write storage space (fifo) by the write cooperative distance, suspend the write cooperative distance until the write storage space (fifo) has data to be read out, and write the target data into the write storage space (fifo) by the write cooperative distance when the write storage space (fifo) has available space.

4. Waiting processing module (wait)

If the current sub-simulation model is used for simulating an M-stage pipeline of the functional module, and the longest clock period required by each stage pipeline in the M-stage pipeline is n, when the wait (n) method is operated at the moment t, the waiting processing module suspends the current cooperative program at the moment t, and continues to execute after the current cooperative program is awakened at the execution (eval) stage at the moment t+n. The current coroutines may include a read coroutine, a combinational logic processing coroutine, and a write coroutine.

5. Judgment processing module

The judging and processing module can be used for realizing the pipeline time sequence of the step-by-step back pressure of each sub-simulation model in the simulation model. The judging and processing module is specifically configured to judge whether a writable space of the writing storage space is full (writable space of the writing storage space < = 0); if the storage space is not fully written, writing target data into the storage space through a write cooperative program; if the write is full, suspending the write-assist, and writing target data into the write-assist through the write-assist until the available space exists in the write-memory space.

In the embodiment of the application, the pipeline structure of each functional module in the target chip can be simulated through one simulation model, the sub-model is not required to be divided according to different flow levels in the functional module, and the method is beneficial to simplifying the writing and modifying processes of the combinational logic in the pipeline structure.

Referring to fig. 5, 3 timing characteristic parameters shown below may be configured for the sub-simulation model corresponding to each functional module:

(1) Write memory space (fifo size) size for each sub-simulation model: the size of the write memory space is the same as the pipeline stage number of the functional module corresponding to the sub-simulation model. For example, sub-simulation model A has a 3-stage pipeline, and then the available write memory space for sub-simulation model A is 3.

(2) The write processing module (write) of each sub-simulation model informs the total latency of the write event: the write processing module informs the total time delay of the write event, which is the total time delay of the corresponding functional module of each sub-simulation model. For example, if the total delay of the sub-simulation model C is 2 clock cycles, the write processing module of the sub-simulation model C notifies that the total delay of the write event is 2 clock cycles.

(3) Latency (n) of the wait processing module (wait) of each sub-simulation model: the latency (n) of the wait processing module (wait) may be the longest clock period required for each stage of pipeline in each sub-simulation model. For example, there is a 1-stage pipeline in the sub-simulation model C, where the longest clock period required by the pipeline is 2 clock periods, and the latency (n) of the wait processing module (wait) of the sub-simulation model C is 2 clock periods.

According to the simulation model provided by the embodiment of the application, through the 3 time sequence characteristic parameters, the pipeline time sequence of each stage of pipeline independent enabling and step-by-step back pressure in the functional module can be accurately simulated. In addition, in the chip simulation process, the number of stages or time delay of each sub-simulation pipeline can be flexibly adjusted by modifying the 3 time sequence characteristic parameters, so that the code development and maintenance cost of the chip simulation process is reduced.

In order to facilitate understanding of pipeline timing of pipeline independent enabling and stage-by-stage back pressure in the simulation model simulation functional module, the timing of simulation model implementation in the exemplary scenario of continuous data reading by the functional module a shown in fig. 5 will be described below with reference to fig. 6.

Fig. 6 is a schematic timing diagram of simulation model implementation when each functional module continuously reads data according to an embodiment of the present application. Please refer to fig. 6, which includes 3 functional modules: the process of reading data at time 0 to time 7 by the 3 functional modules will be described below.

Functional module a: at time 0, the functional module a reads the data d0, and since the functional module a is a 3-stage pipeline and each stage pipeline requires 1 clock cycle, the data d0 is to be sequentially processed by the 3-stage pipeline in the functional module a and then transferred to the functional module B at time 3. At time 1, since the stage 1 pipeline in functional module a passes data d0 to the stage 2 pipeline in functional module a, the stage 1 pipeline in functional module a has available space and the stage 1 pipeline in functional module a can continue to read data d1. The process of reading data by the functional module a at time 2 to time 5 may refer to the process of reading data at time 1, and will not be described herein.

Functional module B: because the functional module B needs to read the output data of the 3 rd-stage pipeline of the functional module A, the 3 rd-stage pipeline of the functional module A does not output the data between the time 0 and the time 2, the functional module B has no readable data, and the reading cooperative procedure of the functional module B is suspended. At time 3, the data d0 may be output from the 3 rd stage pipeline of the functional module a, and then the functional module B reads the data d0, and since the functional module B is a 2 stage pipeline and each stage pipeline needs 1 clock cycle, the data d0 is to be sequentially processed by the 2 stage pipeline in the functional module B and then transferred to the functional module C at time 5. At time 4, since the stage 1 pipeline in functional module B passes data d0 to the stage 2 pipeline in functional module B, the stage 1 pipeline in functional module B has available space and the stage 1 pipeline in functional module B can continue to read data d1. The process of reading data by the functional module B at time 5 may refer to the process of reading data at time 4, which will not be described herein.

Functional module C: because the functional module C needs to read the output data of the 2 nd stage pipeline of the functional module B, between time 0 and time 4, the 2 nd stage pipeline of the functional module B does not output data, and the functional module C has no readable data, and the read co-procedure of the functional module C is suspended. At time 5, functional module C reads data d0, and since functional module C is a 1-stage pipeline and the pipeline requires 2 clock cycles, data d0 is output at time 6 after processing through the 1-stage pipeline in functional module C.

At time 6, since the function module C is still processing the data d0, the function module C will no longer read the data d1 from the function module B. Since there is no data read out in the functional module B, there is no space available in the functional module B, and the read co-operation of the functional module B is suspended. Since the function module B does not read the data d3 from the function module a, no data is read from the function module a, and no space is available in the function module a, the read co-procedure of the function module a is suspended.

At time 7, since the function module C outputs the data d0, the function module C can continue to read the data d1 from the function module B, and the read cooperation of the function module B and the function module a is sequentially restored, so that the subsequent data will be continuously read.

According to the chip simulation method, in the chip simulation process of the target chip, the independently enabled and step-by-step back pressure assembly line time sequence can be accurately simulated through the simulation model.

Fig. 7 is a schematic structural diagram of a chip simulation device according to an embodiment of the present application. The chip simulation device can be a chip or a chip module. Referring to fig. 7, the chip simulation apparatus 10 may include:

a determining module 11, configured to determine a simulation model corresponding to a target chip, where the target chip includes a plurality of functional modules, and the simulation model includes a sub-simulation model corresponding to each functional module;

The reading module 12 is configured to, for any one sub-simulation model, read initial data from a read storage space corresponding to the sub-simulation model;

the processing module 13 is configured to process the initial data through combinational logic corresponding to the sub-simulation model to obtain target data;

the writing module 14 is configured to write the target data into a write storage space corresponding to the sub-simulation model;

and the notification module 15 is configured to notify a next sub-simulation model of the sub-simulation model to read the target data in the write storage space after the total delay corresponding to the sub-simulation model.

The chip simulation device provided by the embodiment of the application can execute the technical scheme shown in the embodiment of the method, and the implementation principle and the beneficial effects are similar, and are not repeated here.

In one possible implementation, the reading module 12 is specifically configured to:

In a possible implementation, after the initial data is read in the read memory space by the read co-program, the reading module 12 is specifically further configured to:

the readable space of the read storage space is decremented by 1.

In one possible implementation, the writing module 14 is specifically configured to:

In one possible implementation, after the target data is written into the write memory space through the write-assist, the writing module 14 is specifically further configured to:

and adding 1 to the readable space of the write storage space.

In one possible implementation, the notification module 15 is specifically configured to:

Fig. 8 is a schematic structural diagram of a chip simulation device according to an embodiment of the present application. Referring to fig. 8, the chip emulation device 20 may include: a memory 21, and a processor 22. The memory 21, the processor 22, are illustratively interconnected by a bus 23.

The memory 21 is used for storing program instructions;

the processor 22 is configured to execute the program instructions stored in the memory, so as to cause the chip emulation device 20 to perform the method shown in the above-described method embodiment.

It is understood that the chip emulation device can include at least one processor and a memory communicatively coupled to the at least one processor. The memory stores instructions executable by the at least one processor to enable the at least one processor to perform the methods described in the embodiments above.

The chip simulation device provided in the embodiment of the present application may execute the technical solution shown in the embodiment of the method, and its implementation principle and beneficial effects are similar, and will not be described in detail here.

Embodiments of the present application provide a computer readable storage medium having stored therein computer executable instructions for implementing the above-described chip emulation method when the computer executable instructions are executed by a processor.

Embodiments of the present application may also provide a computer program product, including a computer program, which when executed by a processor, may implement the above-described chip emulation method.

All or part of the steps for implementing the method embodiments described above may be performed by hardware associated with program instructions. The foregoing program may be stored in a readable memory. The program, when executed, performs steps including the method embodiments described above; and the aforementioned memory (storage medium) includes: read-only memory (ROM), random-access memory (Random Access Memory, RAM), flash memory, hard disk, solid state disk, magnetic tape, floppy disk (floppy disk), optical disk (optical disk), and any combination thereof.

Embodiments of the present application are described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processing unit of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processing unit of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

It will be apparent to those skilled in the art that various modifications and variations can be made to the embodiments of the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the embodiments of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to encompass such modifications and variations.

In the present application, the term "include" and variations thereof may refer to non-limiting inclusion; the term "or" and variations thereof may refer to "and/or". The terms "first," "second," and the like in this application are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. In the present application, "plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship.

Claims

1. A chip simulation method, comprising:

2. The method of claim 1, wherein reading initial data from a read memory space corresponding to the sub-simulation model comprises:

3. The method of claim 2, further comprising, after reading the initial data in the read memory space by the read co-program:

the readable space of the read storage space is decremented by 1.

4. A method according to any one of claims 1-3, wherein writing the target data into a write memory space corresponding to the sub-simulation model comprises:

5. The method of claim 4, further comprising, after writing the target data into the write memory space by the write-assist:

And adding 1 to the readable space of the write storage space.

6. The method of any of claims 1-5, wherein notifying a next sub-simulation model of the sub-simulation model to read the target data in the write memory space after a total time delay corresponding to the sub-simulation model comprises:

7. The method of any of claims 1-6, wherein the write memory space is the same size as the pipeline stages of the functional modules corresponding to the sub-simulation model.

8. A chip emulation device, said device comprising:

9. A chip emulation apparatus, comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1 to 7.

10. A computer readable storage medium having stored therein computer executable instructions for implementing the method of any of claims 1 to 7 when the computer executable instructions are executed by a processor.

11. A computer program product comprising a computer program which, when executed by a processor, implements the method of any one of claims 1 to 7.