CN109753415B - Processor verification system and processor verification method based on same - Google Patents
Processor verification system and processor verification method based on same Download PDFInfo
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Abstract
The invention provides a processor verification system and a processor verification method based on the same, wherein the system comprises a simulation system, a verification system and a verification module, wherein the simulation system is used for receiving a program to be tested and simulating the program; the reference model is used for receiving a program to be tested; the checkpoint manager is used for saving and restoring the simulation state of the simulation system; the monitor is used for monitoring the simulation state of the simulation system and starting the check point manager when the simulation state of the simulation system meets a preset condition so that the check point manager saves and restores the simulation state of the simulation system; and the comparator is used for comparing the value of the simulation state of the simulation system with the simulation expected value generated by the reference model. When the processor has asynchronous interruption, the current state of the asynchronous interruption is saved by starting the check point manager, and the simulation state of the simulation system is recovered, so that comparison of expected values of reference models is facilitated, the efficiency of processor function verification is improved, and meanwhile, complete verification of the processor function is completed.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a processor verification system and a processor verification method based on the processor verification system.
Background
The processor module in the integrated circuit design and development is large in size and high in complexity. Before the integrated circuit is produced and manufactured, the correctness of the designed circuit hardware needs to be verified, the functional verification is to ensure that the behavior of the circuit to be tested is consistent with the functional design specification, and the realization mode comprises the functional verification of a processor.
In the process of implementing the invention, the inventor finds that at least the following technical problems exist in the prior art:
the processor function verification cannot efficiently support the asynchronous interrupt behavior of the processor, difficulty is caused to the establishment and comparison of the expected value of the reference model, the efficiency of the processor function verification is reduced, and the complete verification of the processor function in a short iteration cycle is difficult at the later stage of the verification.
Disclosure of Invention
The processor verification system and the processor verification method based on the processor verification system realize complete verification of processor functions and improve the efficiency of processor function verification.
In a first aspect, the present invention provides a processor verification system, comprising:
the system comprises a simulation system, a reference model, a check point manager, a monitor and a comparator;
the simulation system is used for receiving the program to be tested and carrying out simulation;
the reference model is used for receiving a program to be tested;
the checkpoint manager is used for saving and restoring the simulation state of the simulation system;
the monitor is used for monitoring the simulation state of the simulation system and starting the check point manager when the simulation state of the simulation system meets a preset condition so that the check point manager saves and restores the simulation state of the simulation system;
the comparator is used for comparing the value of the simulation state of the simulation system with the simulation expected value generated by the reference model.
Optionally, the simulation system includes a processor to be tested;
the monitor is specifically configured to detect a simulation state of the processor under test in the simulation system.
Optionally, the processor to be tested is further configured to control the reference model to update the corresponding state, and generate a simulation expected value;
the corresponding state is the same state as the state of the processor under test.
In a second aspect, an embodiment of the present invention further provides a processor verification method based on the processor verification system, including:
reading and executing a program to be tested by the simulation system and the reference model, and checking the simulation state of the simulation system by the monitor;
when the monitor generates asynchronous interruption in a processor to be tested in the simulation system, the processor to be tested processes the asynchronous interruption;
and the checkpoint manager saves the simulation state of the simulation system and restores the simulation state of the simulation system to be consistent with the simulation state of the reference model.
Optionally, the method further includes:
and when the simulation state of the simulation system does not meet the preset condition, the comparator reads the value of the simulation state of the simulation system and compares the value of the simulation state of the simulation system with the simulation expected value generated by the reference model.
Optionally, the method further includes:
and when the comparator monitors that the execution of the program to be tested is finished, the monitor sends a notification of updating the state to the reference model.
Optionally, when the monitor generates an asynchronous interrupt to the processor to be tested in the simulation system, the method further includes:
the comparator stops comparing the values of the simulation states of the simulation system with the simulated expected values generated by the reference model.
In a third aspect, an embodiment of the present invention further provides a processor verification method based on the processor verification system, including:
reading and executing a program to be tested by a reference model, and acquiring a check point of the program to be tested;
and the simulation system and/or the reference model simulates the program to be tested according to the check point.
Optionally, the simulating the program to be tested by the simulation system and/or the reference model according to the check point includes:
when the program to be tested is simulated by the reference model, the checkpoint manager saves the execution state of the reference model when the reference model runs to a checkpoint;
the monitor sends an instruction for executing the program to be tested to the simulation system;
and the simulation system simulates the program to be tested according to the check point.
Optionally, the simulating the program to be tested by the simulation system and/or the reference model according to the check point includes:
when the program to be tested is simulated by the reference model, the checkpoint manager saves the execution state of the reference model when the reference model runs to a checkpoint;
the monitor sends an instruction for executing the program to be tested to the simulation system and the reference model;
and the simulation system and the reference model simulate the program to be tested according to the check point.
According to the processor verification system and the processor verification method based on the processor verification system, when the monitor monitors that the simulation state of the simulation system meets the preset condition, such as the asynchronous interruption condition, the check point manager is started, and the simulation state of the simulation system is stored and recovered through the check point manager, so that when the asynchronous interruption occurs in the processor, the current asynchronous interruption state is stored and the simulation state of the simulation system is recovered through starting the check point manager, comparison of expected values of reference models is facilitated, and complete verification of functions of the processor is completed while the efficiency of function verification of the processor is improved.
Drawings
FIG. 1 is a block diagram of a processor verification system according to an embodiment of the present invention;
FIG. 2 is a flowchart of a processor verification method for a processor-based verification system according to an embodiment of the present invention;
FIG. 3 is a flowchart of a processor verification method for a processor-based verification system according to another embodiment of the invention;
FIG. 4 is a flowchart of a processor verification method for a processor-based verification system according to another embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Before the integrated circuit is produced and manufactured, the correctness of the designed circuit hardware needs to be verified, the functional verification is to ensure that the behavior of the circuit to be tested is consistent with the functional design specification, and the implementation mode comprises functional simulation. General functional simulation verifies a circuit design by running a simulation program on a simulation platform, applies different excitation signals to circuit design inputs at different times, and simulates states and input scenarios that a circuit may encounter in practical application. During the simulation, the state of the circuit and the output signals are detected and compared with expected values, and if the comparison result is inconsistent, the circuit is considered to have a design defect and must be improved.
Due to the complexity of the processor, the simulation running time is relatively long, and factors such as a simulation platform, an excitation length, expected value generation comparison and the like need to be considered for improving the verification efficiency. The functional simulation platform comprises an electronic design automation program, a hardware accelerator and a field programmable gate array which run on a computer, and different simulation platforms have different simulation speeds. The simulation excitation of the processor is a program to be tested, and comprises a randomly generated program and an operating system and an application program in actual application, wherein the operating system and the application program comprise longer instruction sequences and have longer excitation lengths. The expected value generation of the processor simulation comprises self-detection of a program to be tested and a reference model, wherein the reference model is usually different from circuit RTL design, is modeled by software language and the like, and has higher abstraction level and higher simulation speed compared with a processor circuit. The comparison of expected values is of different granularity, the state and output signal at the completion of each instruction are typically compared at the instruction level, and checking may not be practical when the stimulus is longer, and only the calibration is performed at a particular simulation stage.
Asynchronous interrupts are processor-supported behaviors that include physical interrupts and virtual interrupts in the ARM v8 instruction set architecture, represented by processor pins and internal system registers. The asynchronous interruption is generated from external equipment, storage equipment and the like of the processor, and the influence factors of the generation time comprise functions of the external equipment and the storage equipment and states of the simulation system under different excitations, so that the reference model cannot be used for accurately modeling, and difficulty is caused for generating a simulation expected value.
The checkpoint is a software and hardware debugging technology, the state information of the software or the hardware is stored at the checkpoint, the stored state information is stored in a specific simulation module or a text file, and the state information can be extracted from a storage medium and restored in the software or the hardware as a new operating state. The check point can also be used as the time of the simulation comparison.
An embodiment of the present invention provides a processor verification system, and as shown in fig. 1, the processor verification system 100 includes:
the simulation system 120 is configured to receive the program under test 110 and perform simulation;
the reference model 170 is used for receiving the program under test 110;
the checkpoint manager 140 for saving and restoring the simulation state of the simulation system 120;
the monitor 150 is configured to monitor a simulation state of the simulation system, and when the simulation state of the simulation system satisfies a preset condition, start the checkpoint manager 140, so that the checkpoint manager 140 saves and restores the simulation state of the simulation system;
the simulation state of the simulation system in this embodiment satisfies a preset condition, for example, a condition of asynchronous interrupt.
The comparator 160 is configured to compare the value of the simulation state of the simulation system with the simulation expected value generated by the reference model.
In the processor verification system in the above embodiment, when the monitor monitors that the simulation state of the simulation system meets the preset condition, for example, the asynchronous interruption condition, the checkpoint manager is started, and the simulation state of the simulation system is saved and recovered by the checkpoint manager, so that when the asynchronous interruption occurs in the processor, the current asynchronous interruption state is saved by starting the checkpoint manager, and the simulation state of the simulation system is recovered, which facilitates comparison of expected values of reference models, improves efficiency of processor function verification, and completes complete verification of processor functions.
In the processor verification system in the above embodiment, the simulation system 120 includes a processor under test 130;
since the checkpoint manager 140 saves the simulation state of the simulation system when the simulation state is the preset state, in order to avoid that the comparison result of the comparator is affected due to the inconsistency between the simulation state of the simulation system and the state of the reference model after the asynchronous interrupt, the monitor and the processor to be tested in the above embodiment also have the following functions.
The monitor 150 is specifically configured to detect a simulation state of the processor under test 130 in the simulation system.
The processor 130 to be tested is further configured to control the reference model 170 to update the corresponding state and generate a simulation expected value; the corresponding state is the same state as the state of the processor under test.
The checkpoint-enabled processor verification system 100 is comprised of a program under test 110, a simulation system 120, a processor under test 130, a checkpoint manager 140, a monitor 150, a comparator 160, and a reference model 170.
The program under test 110 is randomly generated under certain constraints or consists of an operating system and an application program. The program under test 110 is used as a stimulus in the simulation process to realize different input signals at different times, and is read by the simulation system 120 and the reference model 170 through the input interface.
The simulation system 120 simulates the system-on-chip circuit in real applications to perform signal interaction with the processor 130 under test, including the processor 130 under test, and often includes modules (not shown) such as external devices, storage modules, module interconnection facilities, other master and slave devices, and the like. The emulation system 120 initializes the memory module by reading the program under test 110.
The monitor 150 monitors the simulation execution status of the processor under test 150 during the simulation process. The checkpoint manager 140 is initiated to save and restore the checkpoint simulation state when the state of the processor under test 150 satisfies a certain condition. The execution state of the processor under test 150 is also used to control the reference model 170 to perform corresponding state updates and generate corresponding expected simulation values.
The comparator 160 reads the simulated execution status of the processor under test 130 and compares the simulated execution status with the expected value generated by the reference model 170. The contents of the comparison often include the internal general purpose registers, internal system registers, of the processor under test 130. The moment of comparison is often the completion of one or a segment of instructions. When the comparison does not match, the comparator 160 displays the relevant error message and may stop the simulation.
The reference model 170 reads and executes the program under test 110, and the monitor 150 performs real-time status updating control in the simulation, generates expected processor simulation values and sends the expected processor simulation values to the comparator 160 for comparison.
In general, the simulation process of processor verification system 100 begins with a reset or checkpointed state recovery of simulation system 130 and reference model 170, and then simulation system 130 and reference model 170 read program under test 110 to begin simulation runs. The simulation process 150 detects the state of the processor under test 130 and updates the reference model 170 in real time, the comparator 160 compares the state of the processor under test 130 with the expected value generated by the reference model 170, and the checkpoint manager 140 saves and restores the states of the simulation system 120 and the reference model 170.
An embodiment of the present invention further provides a processor verification method based on the processor verification system, as shown in fig. 2, the method includes:
s201, reading and executing a program to be tested by the simulation system and the reference model, and checking the simulation state of the simulation system by the monitor;
it can be understood that, the simulation system and the reference model read and synchronously execute the program to be tested, the monitor monitors the state of the processor to be tested, and when the state of the processor changes, such as an instruction is completed, the monitor is simultaneously responsible for updating the execution state of the reference model.
S202, judging whether the processor to be tested generates asynchronous interruption or not, if so, executing a step S203; otherwise, go to step S205;
s203, when the monitor generates asynchronous interruption in a processor to be tested in the simulation system, the processor to be tested processes the asynchronous interruption;
it should be noted that, when the processor to be tested receives and processes the asynchronous interrupt, the reference model does not synchronously generate the asynchronous interrupt, and the comparison with the reference model is suspended.
S204, the checkpoint manager saves the simulation state of the simulation system and restores the simulation state of the simulation system to be consistent with the simulation state of the reference model.
And the checkpoint manager saves the environmental state of the simulation system and restores the environmental state to the reference model after the asynchronous interruption occurs, so that the state synchronization of the two is ensured.
Specifically, in step S202, when the processor to be tested does not generate an asynchronous interrupt, the method further includes:
s205, when the simulation state of the simulation system does not meet the preset condition, the comparator reads the value of the simulation state of the simulation system and compares the value of the simulation state of the simulation system with the simulation expected value generated by the reference model.
When the monitor generates asynchronous interrupt to the processor to be tested in the simulation system, the method further comprises the following steps:
the comparator stops comparing the value of the simulation state of the simulation system with the simulated expected value generated by the reference model.
S206, comparing whether an error occurs by the comparator, and if so, ending the simulation; otherwise, go to step S207;
s207, whether the execution of the program to be tested is finished or not is judged, and if yes, the simulation is finished; otherwise, step S201 is continuously performed.
The method further comprises the following steps:
and when the comparator monitors that the execution of the program to be tested is finished, the monitor sends a notification of updating the state to the reference model.
The method realizes the asynchronous interrupt behavior of the processor supporting the checkpoint, starts the checkpoint manager when the monitor monitors that the simulation state of the simulation system meets the preset condition, such as the asynchronous interrupt condition, and saves and recovers the simulation state of the simulation system through the checkpoint manager, so that when the asynchronous interrupt occurs to the processor, the current asynchronous interrupt state is saved and the simulation state of the simulation system is recovered through starting the checkpoint manager, the comparison of expected values of reference models is facilitated, the efficiency of processor function verification is improved, and meanwhile, the complete verification of the processor function is completed.
An embodiment of the present invention further provides a processor verification method based on the processor verification system, as shown in fig. 3, the processor verification method includes: switching between the simulation system and the reference model through the check point state to improve the simulation speed and accelerate the positioning of defects,
s301, reading and executing a program to be tested by a reference model, and acquiring a check point of the program to be tested;
s302, the simulation system and/or the reference model simulate the program to be tested according to the check point.
The step S302 of simulating the program to be tested by the simulation system and/or the reference model according to the check point includes:
when the program to be tested is simulated by the reference model, the checkpoint manager saves the execution state of the reference model when the reference model runs to a checkpoint;
the monitor sends an instruction for executing the program to be tested to the simulation system;
and the simulation system simulates the program to be tested according to the check point.
In another implementable manner, the simulating the program to be tested by the simulation system of step S302 and/or the reference model according to the inspection point includes:
when the program to be tested is simulated by the reference model, the checkpoint manager saves the execution state of the reference model when the reference model runs to a checkpoint;
the monitor sends an instruction for executing the program to be tested to the simulation system and the reference model;
and the simulation system and the reference model simulate the program to be tested according to the check point.
The method realizes the efficient support of the asynchronous interrupt behavior of the processor, and avoids the difficulty in establishing and comparing the expected value of the reference model; the problems of overlong simulation time, low efficiency, difficult circuit defect positioning and the like caused by overlong program to be tested are solved; including mechanisms that do not support flexible checkpoint switching between reference models and processors under test.
By providing the verification method and the verification system supporting the check point, the simulation states of the processor to be tested and the reference model can be flexibly switched, the asynchronous interrupt behavior is supported, a longer program to be tested can run in the processor to be tested in parallel, the defects of the processor are quickly positioned by utilizing state switching, and finally the efficiency of processor function verification is improved.
The processor verification method of the processor verification system in fig. 3 is described in detail below with specific detailed steps, and as shown in fig. 4, the method includes the following steps:
step S401, inquiring whether simulation starts to execute the program to be tested from the reference model, if so, entering step S402; otherwise, executing step S407;
s402, reading and executing excitation by a reference model, reading and executing a program to be tested by the reference model, and checking the state of the reference model by a detector;
s403, judging whether the program to be tested is finished or not, if so, finishing the simulation, otherwise, executing the step S404;
s404, detecting whether the reference model runs to a specific check point, if so, entering a step S405, and saving the execution state of the reference model by a check point manager; if not, executing step S402;
s405, the checkpoint manager saves the execution state of the reference model;
s406, whether the simulation system model is switched to, if so, executing a step S407; otherwise, go to step S402;
s407, the simulation system reads and executes the program to be tested, and the monitor checks the state change of the processor to be tested;
s408, whether the execution of the program to be tested is finished or not is judged, and if yes, the simulation is finished; otherwise, executing step S409;
s409, whether the program to be tested runs to the check point or not is judged, if yes, the step S410 is executed; otherwise, go to step S407;
s410, the check point manager saves the state of the simulation system;
s411, judging whether to switch to a reference model, if so, executing a step S402; otherwise, go to step S407;
step S301, inquiring whether the simulation starts to execute the program to be tested from the reference model, if so, entering step S302 to read the program to be tested from the reference model and execute excitation; step S304 in the execution process of the reference model detects whether the reference model runs to a specific checkpoint, if so, the step S305 is entered to save the execution state of the reference model by the checkpoint; then, the simulation system is switched to execute the rest program to be tested through the step S406, namely the step S407, in the step S407, the reference model can be optionally continuously used for synchronously executing the program to be tested and comparing the program to be tested with the processor to be tested, and the reference model can be stopped and the comparison can be stopped to improve the simulation speed; step S409 detects whether the processor to be tested operates to a new check point after step S407, and may switch to the reference model to execute the remaining program to be tested through saving and restoring the execution state again in step S411, that is, step S402; in step S402, the simulation system does not operate simultaneously to increase the simulation speed, and the reference model can quickly check whether the current operating state is correct compared with the execution process of the processor to be tested.
The invention also provides a processor verification method supporting the check point, which is used for improving the simulation efficiency by switching the check point between the simulation system and the reference model, firstly executing the simulation by the reference model, and saving a plurality of simulation execution states by the check point manager through the steps S402 and S405 until the simulation is finished; the multiple simulation execution states are restored to the simulation system in the multiple simulations, step S407 is started to read and run the remaining programs to be tested corresponding to the states, and simultaneously the reference model is synchronously restored and run to generate expected values, and the expected values are compared until the simulation is finished at the next checkpoint of the program to be tested. The parallel execution of the program to be tested on the simulation system, namely the processor to be tested, is realized through the steps.
Compared with the prior art, the invention has the advantages that:
by the verification method and the verification system supporting the check point, the simulation states of the processor to be tested and the reference model can be flexibly switched in a two-way mode, expected value comparison is suspended when the processor is in asynchronous interruption, and asynchronous interruption behaviors of the processor are supported with low expenditure.
By flexibly switching the states of the processor to be tested and the reference model and alternatively executing the program to be tested, the simulation speed is improved, the defects of the processor are quickly positioned, and the functional verification efficiency of the processor is improved.
By saving and restoring the state of the reference model, the longer program to be tested can run in the processor to be tested in parallel, the simulation running time of the longer program to be tested is reduced, and the efficiency of functional verification of the processor is improved.
Each functional module in each embodiment of the present invention may be integrated into one processing unit, or each module may exist alone physically, or two or more modules are integrated into one unit. The integrated unit can be realized in a form of hardware, or in a form of hardware plus a software functional unit.
The integrated unit implemented in the form of a software functional unit may be stored in a computer readable storage medium. The software functional unit is stored in a storage medium and includes several instructions to enable a computer device (which may be a personal computer, a server, or a network device) or an intelligent terminal device or a Processor (Processor) to execute some steps of the methods according to the embodiments of the present invention. And the aforementioned storage medium includes: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
In the above embodiments provided by the present invention, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described apparatus embodiments are merely illustrative, and for example, a division of modules is merely a division of logical functions, and an actual implementation may have another division, for example, a plurality of modules or components may be combined or integrated into another system, or some features may be omitted, or not executed.
Modules described as separate parts may or may not be physically separate, and parts displayed as modules may or may not be physical modules, may be located in one place, or may be distributed on a plurality of network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
Although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that modifications may be made to the embodiments described in the foregoing detailed description, or equivalent changes may be made in some of the features of the embodiments. All equivalent structures made by using the contents of the specification and the attached drawings of the invention can be directly or indirectly applied to other related technical fields, and all the equivalent structures are within the protection scope of the invention.
Claims (10)
1. A processor verification system, comprising:
the system comprises a simulation system, a reference model, a check point manager, a monitor and a comparator;
the simulation system is used for receiving the program to be tested and carrying out simulation;
the reference model is used for receiving a program to be tested;
the checkpoint manager is used for saving and restoring the simulation state of the simulation system;
the monitor is used for monitoring the simulation state of the simulation system and starting the check point manager when the simulation state of the simulation system meets a preset condition so that the check point manager saves and recovers the simulation state of the simulation system;
the comparator is used for comparing the value of the simulation state of the simulation system with the simulation expected value generated by the reference model.
2. The system of claim 1, wherein the simulation system comprises a processor under test;
the monitor is specifically configured to detect a simulation state of the processor under test in the simulation system.
3. The system of claim 2, wherein the under-test processor is further configured to control the reference model to update the corresponding state and generate a simulation expected value;
the corresponding state is the same state as the state of the processor under test.
4. A processor verification method based on the processor verification system of any one of claims 1 to 3, comprising:
reading and executing a program to be tested by the simulation system and the reference model, and checking the simulation state of the simulation system by the monitor;
when the monitor generates asynchronous interruption in a processor to be tested in the simulation system, the processor to be tested processes the asynchronous interruption;
and the checkpoint manager saves the simulation state of the simulation system and restores the simulation state of the simulation system to be consistent with the simulation state of the reference model.
5. The method of claim 4, further comprising:
and when the simulation state of the simulation system does not meet the preset condition, the comparator reads the value of the simulation state of the simulation system and compares the value of the simulation state of the simulation system with the simulation expected value generated by the reference model.
6. The method of claim 4, further comprising:
and when the comparator monitors that the execution of the program to be tested is finished, the monitor sends a notification of updating the state to the reference model.
7. The method of claim 4, wherein when the monitor is asynchronously interrupted by a processor under test in the emulation system, the method further comprises:
the comparator stops comparing the value of the simulation state of the simulation system with the simulated expected value generated by the reference model.
8. A processor verification method based on the processor verification system of any one of claims 1 to 3, comprising:
reading and executing a program to be tested by a reference model, and acquiring a check point of the program to be tested;
and the simulation system and/or the reference model simulates the program to be tested according to the check point.
9. The method according to claim 8, wherein the simulating of the program under test by the simulation system and/or the reference model according to the check point comprises:
when the program to be tested is simulated by the reference model, the checkpoint manager saves the execution state of the reference model when the reference model runs to a checkpoint;
the monitor sends an instruction for executing the program to be tested to the simulation system;
and the simulation system simulates the program to be tested according to the check point.
10. The method according to claim 8, wherein the simulating of the program under test by the simulation system and/or the reference model according to the check point comprises:
when the program to be tested is simulated by the reference model, the checkpoint manager saves the execution state of the reference model when the reference model runs to a checkpoint;
the monitor sends an instruction for executing the program to be tested to the simulation system and the reference model;
and the simulation system and the reference model simulate the program to be tested according to the check point.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000330798A (en) * | 1999-05-20 | 2000-11-30 | Mitsubishi Electric Corp | Interrupt controller and method for verifying interrupt control |
| CN103150206A (en) * | 2006-12-28 | 2013-06-12 | 英特尔公司 | Efficient and consistent software transactional memory |
| CN103713977A (en) * | 2013-10-31 | 2014-04-09 | 中国船舶重工集团公司第七0九研究所 | Microprocessor IP (internet protocol) kernel comparison and verification implementation method |
-
2017
- 2017-11-02 CN CN201711063415.3A patent/CN109753415B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000330798A (en) * | 1999-05-20 | 2000-11-30 | Mitsubishi Electric Corp | Interrupt controller and method for verifying interrupt control |
| CN103150206A (en) * | 2006-12-28 | 2013-06-12 | 英特尔公司 | Efficient and consistent software transactional memory |
| CN103713977A (en) * | 2013-10-31 | 2014-04-09 | 中国船舶重工集团公司第七0九研究所 | Microprocessor IP (internet protocol) kernel comparison and verification implementation method |
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