CN117805409A

CN117805409A - Sample analyzer and method for detecting sample analyzer

Info

Publication number: CN117805409A
Application number: CN202311282123.4A
Authority: CN
Inventors: 陈跃平; 许伟坚
Original assignee: Shenzhen Mindray Bio Medical Electronics Co Ltd
Current assignee: Shenzhen Mindray Bio Medical Electronics Co Ltd
Priority date: 2022-09-30
Filing date: 2023-09-28
Publication date: 2024-04-02

Abstract

The embodiment of the application provides a sample analyzer and a detection method of the sample analyzer, wherein the sample analyzer comprises a plurality of detection devices, at least two first processors, a first execution device, a second processor and a third processor; the first processor is connected with the detection devices to acquire detection information of the detection devices, and at least one first processor is connected with at least two detection devices; the second processor is connected with the first executing device, and the third processor is respectively connected with the first processor and the second processor; after receiving the detection information uploaded by the first processor, the third processor sends the detection information to a second processor corresponding to the detection information, and the second processor controls the first executing device to execute a preset action corresponding to the received detection information. By the first processor collecting and transmitting the detection information, manufacturability and maintainability of the sample analyzer can be improved compared to directly connecting the detection device to the second processor.

Description

Sample analyzer and method for detecting sample analyzer

Technical Field

The present application relates to the field of medical devices, and in particular, to a sample analyzer and a detection method of the sample analyzer.

Background

The sample analyzer and other devices are all full-automatic intelligent devices, a plurality of execution mechanisms are required to be coordinated and controlled, the state information of the execution mechanisms is monitored and perceived through a large number of sensors on the full-automatic intelligent detection, and the execution mechanisms are controlled through the state information, so that the automation and the intellectualization of the mechanism movement are realized.

In the prior art, a point-to-point transmission mode is generally adopted to realize acquisition and output of sensor data and control of an actuating mechanism; the sample analyzer is used as large-scale automation equipment, a plurality of sensors and actuating mechanisms are required to be connected point to point on a controller, a plurality of cables are required to be connected, and because the sample analyzer is large in size, the cables are required to be routed in a long distance, the length of the cables is in the range of 150cm to 250cm, and the whole equipment is not good in manufacturability and maintainability.

Disclosure of Invention

The present application provides a sample analyzer, a detection method of the sample analyzer, capable of improving at least manufacturability and maintainability of the sample analyzer.

In a first aspect, embodiments of the present application provide a sample analyzer, comprising:

a plurality of detection devices for outputting detection information;

The first processors are connected with the detection devices to acquire detection information of the detection devices, and at least one first processor is connected with at least two detection devices;

the first execution device is used for executing a preset action;

the second processor is connected with the first execution device;

the third processor is respectively connected with the first processor and the second processor; after receiving the detection information uploaded by the first processor, the third processor sends the detection information to the second processor corresponding to the detection information;

the second processor is further configured to control the first executing device to execute the preset action corresponding to the received detection information.

In a second aspect, an embodiment of the present application provides a detection method of a sample analyzer, including:

acquiring detection information of detection devices acquired by at least two first processors, wherein at least one first processor is connected with at least two detection devices;

and sending the detection information to a second processor corresponding to the detection information, so that the second processor controls a first execution device to execute the preset action corresponding to the received detection information.

The sample analyzer and the detection method thereof provided by the embodiment of the application comprise a plurality of detection devices, at least two first processors, a first execution device, a second processor and a third processor; the first processor is connected with the detection devices to acquire detection information of the detection devices, and at least one first processor is connected with at least two detection devices; the second processor is connected with the first executing device, and the third processor is respectively connected with the first processor and the second processor; after receiving the detection information uploaded by the first processor, the third processor sends the detection information to a second processor corresponding to the detection information, and the second processor controls the first executing device to execute a preset action corresponding to the received detection information. By the first processor collecting and transmitting the detection information, manufacturability and maintainability of the sample analyzer can be improved compared to directly connecting the detection device to the second processor.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure of embodiments of the present application.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of a sample analyzer according to an embodiment of the present disclosure;

FIG. 2 is a schematic block diagram of a sample analyzer in one embodiment;

FIG. 3 is a schematic block diagram of a sample analyzer in another embodiment;

FIG. 4 is a schematic diagram of a related art point-to-point transmission mode for implementing the collection and output of I/O information;

FIG. 5 is a schematic diagram of a related art point-to-point transmission mode implementation for controlling multiple execution devices;

FIG. 6 is a schematic diagram of transmitting data when a point-to-point transmission mode is used to control a multi-path execution device in the related art;

FIG. 7 is a schematic view of a sample analyzer according to an embodiment of the present application;

fig. 8 is a flow chart of a detection method of a sample analyzer according to an embodiment of the present application.

Reference numerals illustrate: 501. a detection device; 401. a first processor; m, a first executive device; 201. a second processor; 101. a third processor; 306. a first bus; 307. a second bus; 303. a third bus; 502. a second actuator; 401', a fourth processor;

10. a functional module; 11. a sample member; 12. a sample dispensing mechanism; 13. a reagent component; 14. a reagent dispensing mechanism; 15. a mixing mechanism; 16. a reaction member; 17. a light measurement unit; 20. an input module; 30. a display module; 40. a memory; 50. a processor; 60. and an alarm module.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.

The flow diagrams depicted in the figures are merely illustrative and not necessarily all of the elements and operations/steps are included or performed in the order described. For example, some operations/steps may be further divided, combined, or partially combined, so that the order of actual execution may be changed according to actual situations.

Some embodiments of the present application are described in detail below with reference to the accompanying drawings. The following embodiments and features of the embodiments may be combined with each other without conflict.

Referring to fig. 1, fig. 1 is a schematic structural diagram of a sample analyzer according to an embodiment of the present application.

In some embodiments, the sample analyzer includes, but is not limited to, at least one of: biochemical analyzer, electrolyte analyzer, immunity analyzer, coagulation analyzer, urine analyzer. The electrolyte analyzer is, for example, an ISE (Ion Selective Electrode, ionic electrode) analyzer.

Illustratively, the sample analyzer is a biochemical analysis module in a biochemical analyzer, and the biochemical analyzer may further include at least one of an ISE analysis module, an immunoassay module, a coagulation analysis module, a urine analysis module, and the like.

Before explaining the present invention in detail, a description will be given of the structure of a sample analyzer in some embodiments.

Referring to fig. 2, an embodiment discloses a sample analyzer, which includes at least one functional module 10 (or one or more functional modules 10), an input module 20, a display module 30, a memory 40, a processor 50, and an alarm module 60, which are described below.

Each functional module 10 is used for performing at least one function required in the sample analysis process, and the functional modules 10 cooperate together to perform the sample analysis to obtain a sample analysis result. Referring to fig. 3, a sample analyzer according to an embodiment is shown, in which some examples of the functional module 10 are provided. For example, the functional module 10 may include a sample block 11, a sample dispensing mechanism 12, a reagent block 13, a reagent dispensing mechanism 14, a mixing mechanism 15, a reaction block 16, a photometric block 17, and the like.

The sample part 11 is used for carrying a sample. Sample assembly 11 may include sample distribution modules (SDM, sample Delivery Module) and front end rails in some examples; in other examples, the sample part 11 may also be a sample tray comprising a plurality of sample positions in which sample receptacles, such as sample tubes, may be placed, the sample tray being adapted to be moved to a corresponding position by rotating its tray structure, such as a position in which sample is drawn by the sample dispensing mechanism 12.

The sample dispensing mechanism 12 is used to aspirate and discharge a sample into a reaction cup to be loaded. For example, the sample dispensing mechanism 12 may comprise a sample needle that is moved in two or three dimensions spatially by a two or three dimensional drive mechanism so that the sample needle can be moved to aspirate the sample carried by the sample part 11 and to move to the cuvette to be loaded and discharge the sample to the cuvette.

The reagent component 13 is for carrying a reagent. In one embodiment, the reagent component 13 may be a reagent disk, where the reagent disk is configured in a disk-shaped structure and has a plurality of positions for carrying reagent containers, and the reagent component 13 can rotate and drive the reagent containers carried by the reagent component to rotate to a specific position, for example, a position where the reagent is sucked by the reagent dispensing mechanism 14. The number of reagent parts 13 may be one or more.

The reagent dispensing mechanism 14 is used to aspirate and discharge the reagent into the cuvette to be filled with the reagent. In one embodiment, the reagent dispensing mechanism 14 may comprise a reagent needle that is moved in two or three dimensions spatially by a two or three dimensional drive mechanism so that the reagent needle can be moved to aspirate the reagent carried by the reagent component 13 and to move to and discharge the reagent to the cuvette to be filled with the reagent.

The mixing mechanism 15 is used for mixing the reaction liquid to be mixed in the reaction cup. The number of mixing mechanisms 15 may be one or more.

The reaction part 16 has at least one place for placing a reaction cup and incubating the reaction liquid in the reaction cup. For example, the reaction component 16 may be a reaction disk, which is arranged in a disk-like structure, and has one or more placement sites for placing reaction cups, and the reaction disk can rotate and drive the reaction cups in the placement sites to rotate, so as to schedule the reaction cups in the reaction disk and incubate the reaction liquid in the reaction cups.

The photodetection unit 17 is configured to photodetect the reaction solution after incubation, and obtain reaction data of the sample. For example, the photodetection means 17 detects the luminescence intensity of the reaction solution to be measured, and calculates the concentration of the component to be measured in the sample from the calibration curve. In one embodiment, the photodetection part 17 is separately provided outside the reaction part 16.

The foregoing is illustrative of some of the functional modules 10 and the following continues with a description of other components and structures in the sample analyzer.

The input module 20 is for receiving input from a user. Typically, the input module 20 may be a mouse, a keyboard, etc., and in some cases may also be a touch display screen, which brings about functions for a user to input and display content, so that in this example the input module 20 and the display module 30 are integrated. Of course, in some examples, the input module 20 may even be a voice input device or the like that brings up recognition voice.

The display module 30 may be used to display information. In some embodiments, the sample analyzer itself may incorporate a display module, and in some embodiments, the sample analyzer may be connected to a computer device (e.g., a computer) for displaying information via a display unit (e.g., a display screen) of the computer device, which falls within the scope of the display module 30 herein defined and protected.

For convenience of explanation, a sample analyzer will be mainly described as a biochemical analyzer.

The sample analyzer, such as large-scale biochemical equipment, is mostly full-automatic intelligent equipment, and needs to coordinate and control a plurality of executing devices such as motors, valves, pumps and the like, monitors and senses state information of the executing devices by deploying a plurality of sensors on the full-automatic intelligent detection, and realizes automation and intellectualization of motion of the executing devices by controlling the executing devices according to the sensed state information, wherein the deployed sensors generate a plurality of Input/Output (I/O) data, and the I/O information is used for monitoring and controlling different executing devices.

Referring to fig. 4, fig. 4 is a schematic diagram of a related art for implementing the collection and output of the I/O information by using a point-to-point transmission method. As shown in fig. 4, a microprocessor of a lower computer, such as an MCU (Microcontroller Unit micro control unit), acquires the acquisition signals of the sensor 51 through a GPI (General Purpose Input ) interface, and outputs control signals through a GPO (General Purpose Output ) interface to control the execution device 52. In the related art, the signals generated by each sensor 51 are transmitted to each execution device 52 through the electronic cable point-to-point by the GPIO (General Purpose Input Output, general purpose input/output) interfaces of the MCUs, and the multipath control signals output by the GPIO interface of one MCU are transmitted to each execution device 52 through the electronic cable point-to-point, so that the acquisition and control of the I/O information are performed by the point-to-point transmission manner among the sensor 51, the execution device 52 and the MCUs of the lower computer.

Referring to fig. 5, fig. 5 is a schematic diagram of a control architecture for controlling multiple execution devices in the related art by using point-to-point transmission, where the multiple execution devices include an execution device 52 and an execution device M, and the execution device M is, for example, a motor. The number of the execution devices controllable by each lower computer MCU is limited, so that the multiple execution devices of the sample analyzer are usually controlled by multiple MCUs respectively, and different MCUs are connected with a main controller of the middle computer, such as a CPU (Central Processing Unit ) through buses, and then the whole control principle is as follows: each execution device M needs to be provided with a plurality of sensors 51, the MCU of the lower computer processes the data of each sensor 51 in a point-to-point transmission mode, and then sends out corresponding instructions to control the execution device M, and meanwhile, the MCU of the lower computer can also output control signals of each execution device 52 in a point-to-point transmission mode. The CPU of the middle computer is connected with the MCU of the plurality of lower computers through a communication bus, and performs data exchange with the MCU of the lower computers through the communication bus so as to schedule the action time sequences of all the execution devices; when two related execution devices M are respectively located in MCUs of two different lower computers, at the moment, the MCUs of the different lower computers respectively acquire the position information detected by the sensors 51 corresponding to the two execution devices M, the position information is respectively reported to the CPU of the middle computer through the communication bus after being subjected to data processing, and after the CPU of the middle computer carries out data analysis processing on the sensors 51 reported by the MCUs of the lower computers, the MCU of each lower computer respectively sends out instructions to the MCUs of the two different lower computers through the communication bus, and then the MCU of each lower computer respectively sends out instructions to control the respective execution device M. Similarly, the control of the execution device 52 is also to transmit instructions to the MCUs of the lower computers respectively by the CPU of the intermediate computer, and to output control signals to control the connected execution device 52 by the MCUs of the lower computers respectively.

Referring to fig. 6, fig. 6 is a schematic diagram illustrating transmission of I/O information when the multiple execution device 52 is controlled by applying the point-to-point transmission scheme in the related art. Each sensor 51 is connected with a different I/O interface of the MCU of the lower computer and transmits corresponding data, each execution device 52 is controlled by the different I/O interface of the MCU of the lower computer, and a plurality of I/O information of the same MCU are processed and controlled by the MCU. The MCU of a plurality of lower computers is connected with the CPU of the middle computer through the bus, and is transmitted to the CPU of the middle computer through the bus, and the CPU of the middle computer also respectively issues instructions to the MCU of different lower computers through the bus to carry out overall scheduling control on the execution devices 52 under different MCU.

The inventor of the present application found that when the related art controls the multiple execution devices in a point-to-point transmission manner, at least one of the following disadvantages exists:

firstly, the CPU of the central processing unit performs overall scheduling on all execution devices, and the point-to-point transmission mode cannot enable the CPU to acquire all sensor information at the first time so as to process as soon as possible. The point-to-point transmission mode is not problematic when controlling a small number of execution devices, such as an MCU of only one lower computer, but in a sample analyzer, the execution devices required to be controlled by the CPU of the lower computer are very many, for example, the number of single-axis motors is usually more than 30, and more than 60 execution devices such as solenoids of pumps and valves are required to be generally scheduled by the CPU of the lower computer, so that specific time sequence actions are met, and incorrect coordination among mechanisms is avoided, so that flow errors are caused. The data of the sensor is firstly transmitted to the CPU of the middle computer through the MCU of the lower computer by adopting a point-to-point transmission mode, and the CPU transmits an instruction to the MCU of different lower computers through the bus to control corresponding execution devices, so that the bus is required to transmit the I/O information of the sensor and also the control instruction of the execution devices, and meanwhile, other data of the MCU of the lower computer, such as fault information, are required to be transmitted, the bus is very busy and the bandwidth is tight, so that the I/O information of the sensor cannot be transmitted in time, the CPU of the middle computer cannot acquire the information of all the sensors at the first time, the CPU of the middle computer is influenced to comprehensively judge and make accurate action scheduling, and the control of the execution devices is influenced.

Secondly, a huge number of electronic cables are required to be directly connected, so that the difficulty of equipment wiring is increased, and the manufacturing complexity and the error connection probability are increased. As shown in fig. 5, the sample analyzer is controlled by the boards of the plurality of lower computer MCUs, the boards of the plurality of lower computer MCUs are connected with each other, and meanwhile, the sample analyzer is connected into the boards of the central computer CPU through a communication cable to receive the dispatching and control of the central computer CPU. Thus, a large number of sensors 51 and executing devices 52 such as pumps, valves and the like are required to be connected to each lower computer MCU board; taking a high-end biochemical device as an example, the number of single-shaft motors of the high-end biochemical device is generally more than 30, and the number of executing devices such as a pump, a solenoid of a valve and the like is more than 60, and the number of sensors which are required to be connected in is more than 80, so that more than 180 electronic cables are required; moreover, because such sample analyzers are large in size, these electronic cables need to be routed over long distances, which are in the range of 150cm to 250 cm.

Thirdly, expansibility is poor. When the number of sensors of the execution device increases, the demand for the I/O interface resources of the MCU of the lower computer also increases, and MCU models with more I/O interface resources are needed to be selected, so that the cost is increased, the hardware change design work is increased, and meanwhile, more electronic cable connection is brought about by the increased sensors, so that the space and cost are wasted.

And fourthly, signal transmission is easy to interfere. Long-distance signal transmission is needed between the sensor corresponding to the remote execution device and the lower computer MCU, and the signal is easily interfered by surrounding space due to the adoption of an overlong electronic cable.

Based on the above findings, the inventors have improved sample analyzers to at least improve manufacturability and maintainability of the sample analyzers.

As shown in fig. 1, a sample analyzer according to an embodiment of the present application includes: a plurality of detection devices 501, at least two first processors 401, and a first execution device M, a second processor 201, and a third processor 101.

The first executing means M may include, for example, a motor or the like, but is not limited thereto. For example, when controlling the first executing device M such as the motor, a relatively complex control command is required, for example, the data amount of the control command for controlling the first executing device M is large.

The detection device 501 is illustratively configured to output detection information, such as I/O information. By way of example, the detection device 501 includes, for example, a sensor such as an optocoupler sensor, a pressure switch, a travel switch, a proximity switch, an inductive switch, etc., although not limited thereto.

In some embodiments, the detecting device 501 includes an optocoupler sensor, a travel switch, or the like, and the position detecting device 501 is not limited thereto. Illustratively, the sample analyzer further includes a first mechanism and a second mechanism, the first executing device M is configured to drive the first mechanism and the second mechanism to move relatively, and the position detecting device 501 is configured to output the detection information, such as an output switching value signal, according to a change in position between the first mechanism and the second mechanism. The first executing device M can be controlled to drive the first mechanism to be close to or far from the second mechanism according to the detection information.

Specifically, the first processor 401 is configured to obtain detection information of the detection devices 501, and at least one first processor 401 is connected to at least two detection devices 501; the first executing device M is configured to execute a preset action, and the second processor 201 is connected to the first executing device M.

The third processor 101 is connected to the first processor 401 and the second processor 201, respectively; after receiving the detection information uploaded by the first processor 401, the third processor 101 sends the detection information to the second processor 201 corresponding to the detection information; the second processor 201 is further configured to control the first executing device M to execute the preset action corresponding to the received detection information.

The first processor 401 is connected with the detection device 501, and the first processor 401 uploads the detection information of the detection device 501 to the third processor 101, that is, the first processor 401 is responsible for collecting and transmitting the detection information generated by the detection device 501. The third processor 101 transmits detection information required by each second processor 201 to each second processor 201, and the second processor 201 may control the corresponding first executing device M to execute a corresponding action according to the detection information.

In some embodiments, the second processor 201 is, for example, an MCU of a lower computer of the sample analyzer, and the third processor 101 is, for example, a CPU of a lower computer of the sample analyzer, but is not limited thereto. By using a processor other than the MCU of the lower computer, that is, the first processor 401 is responsible for collecting and transmitting the detection information, and using the first processor 401 as a node for collecting and transmitting the detection information, manufacturability and maintainability of the sample analyzer can be improved compared to directly connecting the detection device 501 to the second processor 201, such as the MCU of the lower computer.

Illustratively, a plurality of I/O boards provided with the first processor 401 may be arranged according to the position distribution of the detecting devices 501, and each I/O board provided with the first processor 401 may be connected to one or more detecting devices 501; the detection device 501 may be connected to an I/O board provided with the first processor 401 nearby, which may reduce the cable length and wiring complexity, and may also increase the interference immunity of the signal transmission. For example, the distance between the detection devices 501 connected to the same first processor 401 is less than or equal to 50 cm; optionally, the distance between all the detection devices 501 connected to the same first processor 401 is less than or equal to 50 cm.

For example, referring to fig. 7, the detecting device 501 is connected to the first processor 401 through a cable 305, and the length of the cable 305 is less than or equal to 50 cm; preferably, the length of the cable 305 is less than or equal to 20 cm, for example within ten cm. For example, the cable 305 may be a cable that is self-contained in the detection device 501, which greatly reduces the number of electronic cables required for a sample analyzer such as a large-scale biochemical device. The manufacturability of the equipment is greatly improved, and the production time of the whole machine is saved.

In some embodiments, the first processor 401 includes at least one of a complex programmable logic device (CPLD, complex Programming logic device) and a field programmable gate array (FPGA, field programmable gate array); the complex programmable logic device and the field programmable gate array are all digital logic chips.

Illustratively, the detection device 501 interfaces with an input/output (I/O) of the first processor 401. For example, the first processor 401 may have more input/output (I/O) interfaces, the number of I/O interfaces of the single first processor 401 may be led out according to actual use requirements, and/or the first processor 401 may easily expand the input/output (I/O) interfaces, for example, the I/O interfaces of the first processor 401 may be expanded by modifying an upper computer program without increasing cost. The acquisition and output resources of the I/O information are expanded, the hardware design is not required to be changed, and an electronic cable is not required to be added. For example, when the detecting device 501 of the sample analyzer is greatly increased, the I/O interface of the detecting device 501 can be conveniently extended and connected based on the first processor 401 such as a digital logic chip, so as to improve maintainability of the sample analyzer and have the advantage of cost.

The detection information output by the detection device 501 includes, for example, a switching value signal. The switching value signal is a signal similar to on-off, and usually has only two states, on or off.

In some embodiments, the detecting device 501 includes an optocoupler sensor, a travel switch, or the like, and the position detecting device 501 is not limited thereto. The position detection means 501 may be provided on the first mechanism and/or the second mechanism; the detection information output by the position detection device 501 includes a switching value signal, for example, indicating that the first mechanism is closer to the second mechanism or that the first mechanism is in contact with the second mechanism when the position detection device 501 outputs 1, and indicating that the first mechanism is farther from the second mechanism when the position detection device 501 outputs 0, and are separated from each other.

For example, the first mechanism comprises a sample dispensing module and the second mechanism comprises a sample detection channel, and the first actuator is configured to drive the sample dispensing module in relative motion with the sample detection channel. When the first executing device drives the sample distribution module to reach the sample detection channel, the position detection device 501 outputs 1, and the second processor 201 or the third processor 101 controls the first executing device to stop driving the sample distribution module to move continuously when the position detection device outputs 1, so that the sample distribution module dispatches the carried sample to the sample detection channel at the sample detection channel for the sample distribution mechanism to suck the sample.

For example, the first actuator comprises a driving mechanism of the sample needle, the first mechanism comprises a position reference part which is arranged on the driving mechanism and moves along with the driving mechanism, and a trigger position is arranged on the position reference part; the second mechanism does not follow the movement of the driving mechanism, and the position detecting device 501 may be provided on the second mechanism; when the trigger position on the position reference component reaches the position where the position detection device 501 is located, the position detection device 501 outputs 1, and the second processor 201 or the third processor 101 controls the driving mechanism to stop driving the sample needle to continuously descend when the position detection device outputs 1, so that the sample needle is prevented from touching the bottom of the sample container.

By connecting the detection device 501 outputting the switching value signal to the first processor 401, the switching value signal is collected and transmitted by the first processor 401, the performance requirement on the first processor 401 can be made lower, the cost of the first processor 401 can be reduced, or more first processors 401 can be arranged, so that the detection device 501 is connected with the first processor 401 nearby, and the wiring workload is reduced.

In some embodiments, referring to fig. 1, each first processor 401 may upload the detection information, such as I/O information, obtained from the detection device 501 to a bus, and all the I/O information may be transferred to the third processor 101 through the bus.

For example, referring to fig. 7, a plurality of first processors 401 are connected in series through a first bus 306 and then connected to the third processor 101. The first processors 401 adjacent to each other are illustratively connected through a serial peripheral interface (SPI, serial Peripheral Interface), but not limited thereto.

Illustratively, when each first processor 401 receives the detection information sent by the adjacent first processor 401, the detection information uploaded by the detection device 501 connected to the first processor 401 is sent to the adjacent other first processor 401 or to the third processor 101 together with the received detection information. For example, the first processor 401a, the first processor 401b, and the first processor 401c are sequentially connected in series, and the first processor 401c is connected to the third processor 101, and the first processor 401a sends the acquired detection information a to the first processor 401b; the first processor 401b transmits the detection information b uploaded by the detection device 501 connected thereto, together with the detection information a transmitted by the first processor 401a, to the first processor 401c; the first processor 401b sends the detection information c uploaded by the detection devices 501 connected to the first processor 401b, and the detection information a and the detection information b sent by the first processor 401b, to the third processor 101, so that the third processor 101 can acquire the detection information of the detection devices 501 connected to each first processor 401, for example, the third processor 101 can acquire the I/O information such as the detection information of all the detection devices 501 at the first time, which is beneficial for the third processor 101 to globally consider and schedule the execution mechanism.

Illustratively, when the first processor 401 acquires the detection information, the detection information of the detection device 501 is added to a data position corresponding to the detection device 501 in a data frame, so as to obtain a data frame including the detection information of a plurality of detection devices 501, and the data frame is sent to an adjacent first processor 401 or third processor 101.

For example, the first processor 401a connects the detecting device 501a1, the detecting device 501a2 and the detecting device 501a3, and the corresponding data positions are a1, a2 and a3 in sequence; the first processor 401b is connected with the detecting device 501b1, the detecting device 501b2 and the detecting device 501b3, and the corresponding data positions are b1, b2 and b3 in sequence; the first processor 401c is connected with the detecting device 501c1, the detecting device 501c2 and the detecting device 501c3, and the corresponding data positions are c1, c2 and c3 in sequence; the data frame may represent a1, a2, a3, b1, b2, b3, c1, c2, c3, and the first three data positions a1, a2, a3 in the data frame sent by the first processor 401a to the first processor 401b are respectively added with detection information of the detection device 501a1, the detection device 501a2, and the detection device 501a 3; the first processor 401b receives the data frame sent by the first processor 401a, and adds detection information of the detection device 501b1, the detection device 501b2 and the detection device 501b3 at three data positions b1, b2 and b3 in the middle of the data frame respectively; the first processor 401b adds the detection information of the corresponding detection device 501 to the first six bits in the data frame sent to the first processor 401c, the first processor 401c adds the detection information of the detection device 501c1, the detection device 501c2 and the detection device 501c3 to the last three data positions c1, c2 and c3 of the data packet, respectively, and uploads the data frame with the detection information added to the nine data positions to the third processor 101.

Illustratively, the third processor 101 sends the detection information of the data position corresponding to each of the first executing devices M in the data frame to the second processor 201 corresponding to each of the first executing devices M. For example, the third processor 101 may determine the detection information of the data position corresponding to each first execution device M in the data frame, for example, may determine the data position corresponding to the first execution device M in the data frame according to the detection device 501 corresponding to the first execution device M, and send the detection information of the corresponding data position to the second processor 201 corresponding to the first execution device M; the second processor 201 controls the first executing device M to execute the preset actions corresponding to the detection information.

Optionally, the first processor 401 is further configured to determine whether a combination of detection information of at least two detection devices 501 connected to the first processor is different from a preset first combination of detection information; and/or determining whether a combination of detection information of the detection devices 501 to which the plurality of first processors 401 are respectively connected is different from a preset second detection information combination.

For example, when each detection device 501 is normal, for example, the connection with the corresponding I/O interface of the first processor 401 is correct, and the cable is reliably and stably connected, the combination of the detection information of the different detection devices 501 should be the same as the preset combination of the detection information; for example, when the detection information of the detection device 501a1 is 1, the detection information of the detection device 501a2 should be 0, the first processor 401a may determine whether or not the combination of the detection information of the detection device 501a1 and the detection device 501a2 is the same as the first detection information combination; or when the detection information of the detection device 501a3 is 1, the detection information of both the detection device 501b1 and the detection device 501c3 should be 1, the first processor 401b may determine whether the combination of the detection information of the detection device 501a3 and the detection device 501b1 is the same as the second detection information combination, and the first processor 401c may determine whether the combination of the detection information of the detection device 501a3, the detection device 501b1 and the detection device 501c3 is the same as the second detection information combination.

Illustratively, when the combination of the detection information of at least two detection devices 501 connected to the first processor 401 is different from the preset first detection information combination, and/or the combination of the detection information of a plurality of detection devices 501 connected to the first processor 401 is different from the preset second detection information combination, the uploaded detection information is marked as abnormal detection information when the detection information of the detection devices 501 is uploaded to the third processor 101. For example, when the first processor 401c may determine whether the combination of the detection information of the detection device 501a3, the detection device 501b1, and the detection device 501c3 is different from the second detection information combination, the data frame uploaded to the third processor 101 marks that there is a detection information abnormality in the data frame or marks that at least one of the detection device 501a3, the detection device 501b1, and the detection device 501c3 is abnormal; alternatively, the third processor 101 may output corresponding prompt information according to the flag.

In some embodiments, referring to fig. 7, the sample analyzer includes a plurality of second processors 201, and the plurality of second processors 201 are connected in parallel and then connected to the third processor 101 through a second bus 307, and the third processor 101 sends the detection information to the second processor 201 through the second bus 307.

Illustratively, as shown in fig. 7, after all I/O information, such as the detection information of the detection device 501, is transmitted to the third processor 101 by the first bus 306, the I/O information required by the second processor 201 is transmitted to the second processor 201 by the third processor 101 through the additional second bus 307 according to the I/O information required by each second processor 201. The I/O signals such as the detection information of the detection device 501 are uploaded to the first processor 401 in parallel, then serialized by the first processor 401 and sent to the third processor 101 for processing, and finally parallelized by the third processor 101 and sent to the corresponding second processor 201. The transmission of the I/O information such as the detection information acquired by the first processor 401 through the first bus 306 and the transmission of the I/O information required by the second processor 201 through the second bus 307, that is, the transmission of the I/O information such as the detection information between the first processor 401 and the third processor 101 and between the third processor 101 and the second processor 201 through different buses, may enable the third processor 101 and the second processor 201 to process and respond to the I/O information such as the detection information more quickly, thereby improving the real-time performance of the transmission and processing of the I/O information in the third processor 101 and the second processor 201.

Optionally, referring to fig. 7, the second processor 201 is further connected to the third processor 101 through a third bus 303, for example, a plurality of second processors 201 are connected in parallel and then further connected to the third processor 101 through the third bus 303. The third processor 101 is further configured to send a control instruction to the second processor 201 through the third bus 303, and the second processor 201 controls the first execution device M according to the control instruction. For example, the third processor 101 may be responsible for performing overall scheduling and control of the sample analyzer, and the second processor 201 may receive control instructions of the third processor 101 and control the corresponding first executing device M according to the control instructions; the third bus 303 may be referred to as an instruction bus, dedicated to transferring control instructions between the third processor 101 and the second processor 201; by transmitting control instructions between the third processor 101 and the second processor 201 through the separate third bus 303, the influence on the transmission of the I/O information by the second bus 307 can be reduced, and the real-time performance of the transmission and processing of the I/O information between the third processor 101 and the second processor 201 can be ensured.

In some embodiments, referring to fig. 7, the sample analyzer further includes a second executing device 502 and a fourth processor 401', wherein the second executing device 502 is connected to the fourth processor 401'.

The second actuator may, for example, include, but is not limited to, a pump, a valve, etc. For example, the control signal for controlling the second actuator 502 is relatively simple, such as a switching value signal.

The fourth processor 401' is further configured to obtain a switching state of the second executing device 502, and may further upload the switching state of the second executing device 502 to the third processor 101, so that the third processor 101 performs overall control and scheduling on the sample analyzer.

Optionally, the third processor 101 sends the detection information received from the first processor 401 and/or the switch state received from the fourth processor 401' to the corresponding second processor 201; the second processor 201 controls, for example, the first executing device M to execute the action corresponding to the detection information and/or the switch state.

Illustratively, the second actuator is coupled to an input/output (I/O) interface of the fourth processor 401'. For example, the on-off state of the second execution device 502 may also be acquired and transmitted as I/O information by the fourth processor 401'. In some embodiments, the fourth processor 401 'acquires and transmits the switching state of the second actuator in the same manner as the first processor 401 acquires and transmits the detection information of the detection device 501, and the principle and process of the fourth processor 401' acquiring and transmitting the switching state of the second actuator may refer to the foregoing description of the first processor 401 acquiring and transmitting the detection information of the detection device 501.

Illustratively, the second actuator is coupled to the fourth processor 401' by a cable 302, the cable 302 having a length of less than or equal to 50 centimeters; preferably, the length of the cable 302 is less than or equal to 20 cm. Illustratively, the distance between all of the second actuators coupled to the same fourth processor 401' is less than or equal to 50 centimeters.

Illustratively, the fourth processor 401' includes at least one of a complex programmable logic device (CPLD, complex Programming logic device) and a field programmable gate array (FPGA, field programmable gate array).

Illustratively, the fourth processors 401 'are connected in series to the third processor 101 through the first bus 306 or another bus, where each fourth processor 401' sends the switch state of the connected second execution device 502 and the received switch state of the second execution device 502 to another adjacent fourth processor 401 'or to the third processor 101 when receiving the switch state of the second execution device 502 sent by the adjacent fourth processor 401'.

For example, the fourth processor 401' a and the fourth processor 401' b are sequentially connected in series, and the fourth processor 401' b is connected to the third processor 101, and the fourth processor 401' a sends the acquired switch state a to the fourth processor 401' b; the fourth processor 401' b transmits the switching state b uploaded by the second execution device 502 connected thereto to the third processor 101 together with the switching state a transmitted from the fourth processor 401' a, so that the third processor 101 can acquire the switching state of the second execution device 502 of each fourth processor 401 '.

Alternatively, referring to fig. 7, the first processor 401 and the fourth processor 401' are connected in series through the first bus 306 and then connected to the third processor 101. Illustratively, at least one of the first processor 401 and/or at least one of the fourth processor 401' is coupled to the tri-processor.

Illustratively, each of the first processor 401/fourth processor 401' sends the detection information and/or the on/off state of the second executing device 502 uploaded by the connected detecting device 501 to the adjacent other first processor 401/fourth processor 401' or to the third processor 101 together with the received detection information and/or the off state when receiving the detection information and/or the on/off state sent by the adjacent first processor 401/fourth processor 401 '. So that the third processor 101 can acquire the detection information of the detection device 501 uploaded by each first processor 401 and the on-off state of the second execution device 502 uploaded by each fourth processor 401'.

For example, the first processor 401m, the first processor 401n, the fourth processor 401'm, and the fourth processor 401' n are sequentially connected in series through the first bus 306, and the first processor 401m, the fourth processor 401' n are connected with the third processor 101; the first processor 401n transmits the acquired detection information n to the first processor 401m, and the first processor 401m transmits the detection information m acquired from the detection device 501 to which it is connected to the third processor 101 together with the detection information n; the fourth processor 401'm sends the acquired switching state m to the fourth processor 401' n, and the fourth processor 401' n sends the switching state n acquired from the second execution device 502 to which it is connected to the third processor 101 together with the switching state m.

For example, the first processor 401s, the first processor 401t, and the fourth processor 401's are sequentially connected in series through the first bus 306, and the fourth processor 401's is connected to the third processor 101; the first processor 401t sends the detection information t acquired from the detection device 501 to which it is connected to the fourth processor 401's together with the detection information s acquired from the first processor 401 s; the fourth processor 401's transmits the switching state s acquired from the second execution device 502 to which it is connected to the third processor 101 together with the detection information t and the detection information s.

Illustratively, the fourth processor 401' is further configured to determine whether a combination of switch states of the second executing device 502 connected to itself is different from a preset first switch state combination; and/or determining whether a combination of the switch states of the second executing devices 502 connected to the fourth processors 401' is different from a preset second switch state combination; and uploading the switch state of the second execution device 502 to the third processor 101 when the combination of the switch states of the second execution device 502 connected to the fourth processor 401 'is different from the first switch state combination, and/or the combination of the switch states of the second execution device 502 connected to each of the plurality of fourth processors 401' is different from the second switch state combination.

For example, when each second execution device 502 is normal, for example, the connection with the corresponding I/O interface of the fourth processor 401' is correct, the cable is reliably and stably connected, and when the second execution device 502 can be accurately controlled, the combination of the switch states of the different second execution devices 502 should be the same as the preset switch state combination; for example, when the switching state of the second actuator 502a1 is on, the switching state of the second actuator 502b2 is off; when the switch state of the second execution device 502a1 actually acquired by the fourth processor 401' is on but the switch state of the second execution device 502b2 is also on, the switch state of the second execution device 502a1 and/or the second execution device 502b2 may be marked as an abnormal switch state when uploading the switch state of the second execution device 502 to the third processor 101.

Optionally, the third processor 101 may perform at least one of the following according to the abnormal switch state: outputting state prompt information, adjusting a control instruction sent to the second processor, and adjusting a control signal of the second execution device sent to the fourth processor.

For example, by outputting the state prompt information corresponding to the abnormal switch state, the user may be prompted to check the second executing device 502 or the cable corresponding to the abnormal switch state, so as to ensure that the second executing device 502 can be accurately controlled.

For example, the third processor 101 may be responsible for performing overall scheduling and control of the sample analyzer, and by adjusting the control command of the first executing device M and/or the control signal of the second executing device 502 that is not abnormal according to the abnormal switch state, for example, the first executing device M and/or the second executing device 502 that is abnormal may be controlled to perform a preset protection action, so as to prevent a fault or loss caused by that the second executing device 502 that is abnormal cannot be accurately controlled.

In some embodiments, the third processor 101 is further configured to send a control signal of the second executing device 502 to the fourth processor 401', and the fourth processor 401' is further configured to send the control signal to the second executing device 502, so that the second executing device 502 switches a switching state according to the control signal, and preferably, the control signal is a switching value signal.

Optionally, the third processor 101 sends control signals of the second execution device 502 to the fourth processor 401' via the first bus 306 or another bus. The bus for transmitting the control signal between the third processor 101 and the fourth processor 401' may be the same as or different from the bus for transmitting the switching state.

For example, the third processor 101 may determine the control signal of the second execution device 502 according to the detection information uploaded by the first processor 401 and/or the on-off state of the second execution device 502 uploaded by the fourth processor 401'. The third processor 101 sends control signals of a plurality of second execution devices 502 corresponding to the plurality of processors to the connected fourth processor 401', for example, a data frame sent to the fourth processor 401' b includes control signals of the second execution device 502b1, the second execution device 502b2, the second execution device 502a1, and the second execution device 502a 2; the fourth processor 401' b transmits the control signals of the second executing devices 502b1 and 502b2 to the second executing devices 502b1 and 502b2; the control signals of at least the second actuator 502a1, 502a2 are also sent to the fourth processor 401' a, which sends the second actuator 502a1, 502a2 to the second actuator 502a1, 502a2 accordingly.

The fourth processor 401' is further configured to determine whether a combination of control signals of the plurality of second execution devices 502 is different from a preset control signal combination according to the control signals of the plurality of second execution devices 502, and send the control signals of the plurality of second execution devices 502 to the corresponding second execution devices 502 when the combination of the control signals of the plurality of second execution devices 502 is the same as the control signal combination.

For example, some state control of the second actuator 502 is associated, for example, when the switch state of the second actuator 502a1 is controlled to be switched on, the switch state of the second actuator 502b2 is also controlled to be switched off, and an abnormal operation may occur in the sample analyzer. When the fourth processor 401' determines that the combination of the control signals of the plurality of second execution devices 502 is the same as the preset combination of the control signals, the plurality of second execution devices 502 are controlled according to the control signals, so that the control accuracy can be improved. For example, the fourth processor 401' is further configured to not send the control signals to the second execution device 502 when the combination of the control signals of a plurality of the second execution devices 502 is different from the combination of the control signals, and the switch state of the second execution device 502 is not switched; when the fourth processor 401' uploads the on-off state of the second execution devices 502 to the third processor 101, the third processor 101 may determine that an abnormality occurs in the control of these second execution devices 502. Alternatively, the fourth processor 401' may send an abnormality notification to the third processor 101 when the combination of the control signals of the plurality of second execution devices 502 is different from the combination of the control signals, and the third processor 101 may determine that the control signals of the plurality of second execution devices 502 are abnormal.

The sample analyzer provided by the embodiment of the application comprises a plurality of detection devices, at least two first processors, a first execution device, a second processor and a third processor; the first processor is connected with the detection devices to acquire detection information of the detection devices, and at least one first processor is connected with at least two detection devices; the second processor is connected with the first executing device, and the third processor is respectively connected with the first processor and the second processor; after receiving the detection information uploaded by the first processor, the third processor sends the detection information to a second processor corresponding to the detection information, and the second processor controls the first executing device to execute a preset action corresponding to the received detection information. By the first processor collecting and transmitting the detection information, manufacturability and maintainability of the sample analyzer can be improved compared to directly connecting the detection device to the second processor.

In some embodiments, the detection information of the detection device, the switch state of the second execution device and the control signal of the second execution device are transmitted between the first processor and the fourth processor and the third processor through the first bus, and the detection information and/or the switch state are transmitted between the second processor and the third processor through the second bus.

Referring to fig. 8 in combination with the foregoing embodiments, fig. 8 is a flow chart of a detection method of a sample analyzer according to an embodiment of the present application.

As shown in fig. 8, the detection method of the sample analyzer includes the following steps S110 to S120.

Step S110, acquiring detection information of detection devices acquired by at least two first processors, wherein at least one first processor is connected with at least two detection devices;

step S120, sending the detection information to a second processor corresponding to the detection information, so that the second processor controls the first executing device to execute the received preset action corresponding to the detection information.

In some embodiments, the sample analyzer includes a plurality of the first processors, the plurality of first processors being connected in series by a first bus.

Illustratively, the acquiring the detection information of the detection devices acquired by the at least two first processors includes: and acquiring detection information from at least one first processor in at least two first processors through the first bus, wherein the detection information comprises detection information uploaded by a detection device connected with the at least one first processor, and detection information acquired by the at least one first processor from another adjacent first processor and uploaded by the detection device connected with the other first processor.

In some embodiments, the sample analyzer includes a plurality of the second processors, and the plurality of the second processors are connected in parallel and then connected to a second bus.

Exemplary, the sending the detection information to the second processor corresponding to the detection information includes: and sending the detection information to a second processor corresponding to the detection information through the second bus.

Optionally, the method further comprises: and sending a control instruction to the second processor through a third bus so that the second processor controls the first execution device according to the control instruction.

In some embodiments, the method further comprises: and sending a control signal of a second execution device of the sample analyzer to a fourth processor, so that the fourth processor sends the control signal to the second execution device, and the second execution device switches the switch state according to the control signal.

The specific principle and implementation manner of the detection method of the sample analyzer provided in the embodiment of the present application are similar to those of the sample analyzer in the foregoing embodiment, and are not repeated here.

It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

It should also be understood that the term "and/or" as used in this application and the appended claims refers to any and all possible combinations of one or more of the associated listed items, and includes such combinations.

While the invention has been described with reference to certain preferred embodiments, it will be understood by those skilled in the art that various changes and substitutions of equivalents may be made and equivalents will be apparent to those skilled in the art without departing from the scope of the invention. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A sample analyzer, comprising:

a plurality of detection devices for outputting detection information;

the first execution device is used for executing a preset action;

the second processor is connected with the first execution device;

2. The sample analyzer according to claim 1, comprising a plurality of first processors connected in series via a first bus and then connected to the third processor, wherein each first processor, when receiving detection information sent by an adjacent first processor, sends the detection information uploaded by the detection device connected to the first processor to the adjacent other first processor or sends the received detection information to the third processor together.

3. The sample analyzer of claim 1, comprising a plurality of the second processors, wherein the plurality of the second processors are connected in parallel and then connected to the third processor through a second bus, and wherein the third processor sends the detection information to the second processor through the second bus.

4. The sample analyzer of claim 3, wherein a plurality of the second processors are further connected in parallel to the third processor through a third bus, the third processor is further configured to send a control instruction to the second processor through the third bus, and the second processor controls the first executing device according to the control instruction.

5. The sample analyzer of claim 3, wherein when the first processor acquires the detection information, the detection information of the detection device is added to a data position corresponding to the detection device in a data frame, and the data frame is sent to an adjacent first processor or the third processor;

and the third processor sends detection information of the data position corresponding to each first execution device in the data frame to the second processor corresponding to each first execution device.

6. The sample analyzer of claim 1, wherein the detection device is connected to the first processor by a cable, the cable having a length of less than or equal to 50 centimeters; preferably, the length of the cable is less than or equal to 20 cm.

7. The sample analyzer of claim 1, wherein a distance between the detection devices connected to the same first processor is less than or equal to 50 cm.

8. The sample analyzer of claim 1, wherein the first processor comprises at least one of a complex programmable logic device and a field programmable gate array.

9. The sample analyzer of any one of claims 1-8, wherein the detection device is coupled to an input/output interface of the first processor.

10. The sample analyzer of claim 9, wherein the detection device comprises a position detection device, and the detection information output by the position detection device comprises a switching value signal;

the sample analyzer further comprises a first mechanism and a second mechanism, the first executing device is used for driving the first mechanism to move relative to the second mechanism, and the position detecting device is used for outputting the switching value signal according to the position change between the first mechanism and the second mechanism.

11. The sample analyzer of any one of claims 1-8, wherein the first processor is further configured to determine whether a combination of detection information of at least two detection devices connected to the first processor is different from a preset first combination of detection information; and/or judging whether the combination of the detection information of the detection devices respectively connected with the first processors is different from the preset second detection information combination; and

And when the combination of the detection information of at least two detection devices connected with the first processor is different from the preset first detection information combination, and/or the combination of the detection information of a plurality of detection devices connected with the first processors is different from the preset second detection information combination, uploading the detection information of the detection devices to the third processor, and marking the uploaded detection information as abnormal detection information.

12. The sample analyzer of any one of claims 1-8, further comprising a second execution device and a fourth processor, the second execution device being coupled to the fourth processor;

the third processor is further configured to send a control signal of the second execution device to the fourth processor, and the fourth processor is further configured to send the control signal to the second execution device, so that the second execution device switches a switching state according to the control signal, and preferably, the control signal is a switching value signal.

13. The sample analyzer of claim 12, wherein the fourth processor is further configured to determine whether a combination of control signals of the plurality of second actuators is different from a preset control signal combination according to the control signals of the plurality of second actuators, and send the control signals of the plurality of second actuators to the corresponding second actuators when the combination of the control signals of the plurality of second actuators is the same as the control signal combination.

14. The sample analyzer of claim 12, wherein the fourth processor is further configured to determine whether a combination of switch states of the second executing device connected to the fourth processor is different from a preset first switch state combination; and/or judging whether the combination of the switch states of the second execution devices respectively connected with the fourth processors is different from the preset second switch state combination; and

uploading the switch state of the second execution device to the third processor to mark the uploaded switch state as an abnormal switch state when the combination of the switch states of the second execution device connected to the fourth processor is different from the first switch state combination and/or the combination of the switch states of the second execution device connected to the fourth processors is different from the second switch state combination, so that the third processor executes at least one of the following according to the abnormal switch state: outputting state prompt information, adjusting a control instruction sent to the second processor, and adjusting a control signal of the second execution device sent to the fourth processor.

15. The sample analyzer of claim 12, wherein the first processor and the fourth processor are connected in series via a first bus to the third processor, wherein at least one of the first processor and/or at least one of the fourth processor is connected to the third processor;

And when receiving detection information and/or switch states sent by the adjacent first processor/fourth processor, each first processor/fourth processor sends the detection information uploaded by the connected detection device or the switch state of the second execution device to the adjacent other first processor/fourth processor or sends the received detection information and/or switch state to the third processor.

16. A method of detecting a sample analyzer, comprising:

and sending the detection information to a second processor corresponding to the detection information, so that the second processor controls a first execution device to execute the received preset action corresponding to the detection information.

17. The method of claim 16, wherein the sample analyzer comprises a plurality of the first processors, the plurality of first processors being connected in series by a first bus;

the obtaining the detection information of the detection devices obtained by the at least two first processors includes:

And acquiring detection information from at least one first processor in at least two first processors through the first bus, wherein the detection information comprises detection information uploaded by a detection device connected with the at least one first processor, and detection information acquired by the at least one first processor from another adjacent first processor and uploaded by the detection device connected with the other first processor.