CN117795493A - Protocol independent control of NAND flash memory - Google Patents
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Abstract
An apparatus and method comprising: a command input for receiving a command with a macro identification from a channel processor; a macro memory for storing a plurality of flash control commands, each flash control command including a respective duration and a respective plurality of target control values to control a flash target; and a second finite state machine comprising a plurality of control outputs, each control output corresponding to a control input on the flash memory target, wherein in response to a received command, the first finite state machine locates a sequence of flash memory control commands associated with a macro identification in the macro memory and sequentially outputs the flash memory control commands to the second finite state machine; and wherein the second finite state machine drives each control output of the plurality of control outputs for a duration specified in the current flash control command based on a corresponding value in the first flash control command.
Description
Related patent application
The present application claims priority from commonly owned U.S. provisional patent application No. 63/296,626, filed on 1/5 of 2022, which is hereby incorporated by reference.
Technical Field
The present application relates to a system and method for controlling flash memory targets.
Background
Flash memory storage devices provide high throughput, low latency, and long term storage of computer data. The flash memory controller sequences commands to the flash memory storage device to complete burst read, burst write, and control commands.
Disclosure of Invention
In some examples, an apparatus is provided that includes a first finite state machine including a command input to receive a command from a channel processor, the command including a macro identification. The apparatus includes a macro memory for storing a plurality of flash control commands, each flash control command including a plurality of target control values and durations for controlling a flash target. And the apparatus includes a second finite state machine comprising a plurality of control outputs, each control output corresponding to one of the plurality of control inputs on the flash memory target. In response to the received command, the first finite state machine locates a sequence of flash control commands associated with the macro identification of the command in the macro memory and sequentially outputs the first flash control commands in the sequence to the second finite state machine. And the second finite state machine driving each of the plurality of control outputs for a duration specified in a current flash control command based on a corresponding value in the first flash control command. In some examples, the apparatus includes a dynamic value selector with an output coupled to the second finite state machine; a selection input driven by a dynamic value indicative identifier of a current flash control command; a first selectable input coupled to the macro memory to receive a value from a current flash control command; and a second selectable input coupled to a buffer in the first finite state machine for storing a dynamic value specified in the command received by the channel processor. When the dynamic value indication flag is asserted, the second finite state machine drives additional outputs for driving additional inputs on the flash memory target based on the dynamic value stored in the buffer. When the dynamic value indication flag is not asserted, the second finite state machine drives additional outputs based on values in the current flash control command. In some examples, the apparatus includes a control selector with an output coupled to the second finite state machine; a selection input driven by the first finite state machine; a first input driven by a plurality of values in the command from the channel processor; and a second input driven by a value in the first flash control command. In some examples, the second finite state machine drives the plurality of target control values in a predetermined sequence corresponding to the command from the channel processor when the control selector select input is asserted. In some examples, the control selector select input is coupled to a pass-through input to the second finite state machine. In some examples, the apparatus includes an initialization processor coupled to the non-volatile memory, the initialization processor to copy each flash control command in the sequence of one or more flash control commands from the non-volatile firmware memory into the macro memory. In some examples, the second finite state machine includes a predetermined sequence for instructing the flash memory target to perform a function from the set of: burst read, burst write and pass, wherein when the function is a burst read, the control finite state machine drives at least a first portion of the plurality of outputs according to a first predetermined timing sequence, when the function is a burst write, the control finite state machine drives at least a second portion of the plurality of outputs according to a second predetermined timing sequence, and when the function is a pass, the control finite state machine drives each of the plurality of control outputs for a duration timing sequence specified in a current flash control command based on a corresponding value in the first flash control command. In some examples, the plurality of control outputs corresponds to the control input of the flash memory target.
In some examples, a method includes: receiving a command from a channel processor, the command including a macro identification; locating in a macro memory a sequence of flash control commands associated with the macro identification, each flash control command including a duration and a plurality of target control values corresponding to a plurality of control inputs on a flash target; and executing a first flash control command in the sequence by reading the first flash control command from the macro memory and driving the plurality of target control values from the first flash control command to a plurality of control outputs coupled to the plurality of control inputs on the flash target for at least a first flash control command duration. In some examples, the command from the channel processor includes a dynamic value, and the method includes: storing the dynamic value in a buffer; executing the current flash control command in the sequence by reading the current flash control command of the sequence, the current flash control command including a dynamic data indication identifier; when the dynamic value indication flag is asserted, driving the dynamic value from the buffer to a plurality of additional outputs coupled to an additional plurality of inputs on the flash memory target; and driving a static value from the current flash control command of the sequence to the plurality of additional outputs when the dynamic value indication flag is not asserted. In some examples, the method includes: a second finite state machine driving the plurality of control outputs and the plurality of additional outputs; transmitting a current flash control command from the macro memory to the second finite state machine; and sending the command from the channel processor to the second finite state machine. In some examples, the method includes: the first finite state machine recognizes the command as a macro command and causes the second finite state machine to pass the current flash control command to the control output. In some examples, the method includes: the first finite state machine recognizes the command as a stock command (stock command), and causes the second finite state machine to decode and execute the stock command. In some examples, the reserved command is a burst read command or a burst write command. In some examples, each loaded reserve command is associated in the second finite state machine with a fixed sequence of target control values, each of the target control values corresponding to one of the plurality of control inputs on the flash memory target. In some examples, the method includes copying flash control commands from the non-volatile memory to the macro memory. In some examples, each input of the flash target is driven by a bit from a current flash control command or a bit from a buffered dynamic value.
In some examples, a configurable flash memory controller is provided that includes a channel processor to schedule commands for controlling a flash memory target; a first finite state machine with a command input for receiving a command from the channel processor, the command including a macro identification and an indication that the command is a macro command; a macro memory RAM for storing a plurality of flash control commands, each flash control command including a target control value and a duration corresponding to each input on the flash target; and a plurality of outputs corresponding to a set of inputs on the flash memory target. The controller is responsive to an indication that the flash control command is a macro command, the first finite state machine locates a sequence of flash control commands associated with the macro command and reads a current flash control command of the sequence for each flash control command in the sequence, and drives the plurality of outputs for at least the first flash control command duration based on the current flash control command target control value. In some examples, the controller includes a second finite state machine encoding a predetermined sequence of flash control commands for driving the plurality of outputs in a sequence to cause the flash target to perform at least one of a burst read or a burst write. In some examples, the controller includes a non-volatile memory to store a sequence of flash control commands.
Drawings
Fig. 1 is an illustration of a system for issuing commands to flash memory according to an example of the present disclosure.
Fig. 2 is a diagram of signal timing provided to a flash memory according to an example of the present disclosure.
Fig. 3 is an instruction table stored in macro memory according to an example of the present disclosure.
Fig. 4 is a flow chart of a method for issuing commands to flash memory according to some examples of the present disclosure.
Fig. 5 is a flow chart of a method for issuing commands to flash memory according to some examples of the present disclosure.
Fig. 6 is an illustration of a system for issuing commands to flash memory according to an example of the present disclosure.
Fig. 7 is an illustration of a system for issuing commands to flash memory according to an example of the present disclosure.
Detailed Description
Fig. 1 is an illustration of a system for issuing commands to flash memory according to an example of the present disclosure. System 100 includes a macro Finite State Machine (FSM) 102, RAM 104, multiplexers (mux) 106 and 108, and control FSM 110, as well as the various buses and control lines as shown. The macro FSM accepts macro commands from the Channel Processor (CPU) that contain macro addresses, macro lengths, and (in some cases) dynamic values such as addresses or a portion of addresses. The macro FSM stores any dynamic values in register 103 for later use. The macro FSM then retrieves each instruction of the macro successively from RAM 104. The macro FSM executes instructions by reading instructions from RAM 104 and selecting RAM inputs of mux 108 to pass the instructions to control FSM 110 and ultimately to the flash target. Some instructions may require dynamic data, such as instructions that load the address of a flash block for erasure. When an instruction from RAM 104 requires dynamic data, the select line on mux 106 is set to extract a data bits from register 103 and the remaining n-a data bits from RAM 104. Some instructions may require static data from RAM 104. When an instruction from RAM 104 requires static data from RAM 104, it may contain a field that specifies the location of the static data to be contained in RAM 104. The select lines on mux 106 are reset to extract a bits from RAM 104. The number of bits may be configurable. In some examples, an instruction may select one, two, or three bytes of static or dynamic data to send to a flash target. The term "data" as used herein may refer to an address or a portion of an address that communicates with a flash memory target. Control FSM 110 is a finite state machine designed to efficiently implement burst operations, such as burst reads and burst writes, which may enable transfers on both rising and falling edges of a clock signal. In an example burst write operation to a DDR flash target, FSM 110 is controlled to transfer data on the Data (DQ) lines on each rising and trailing edge of the data strobe (DQS output). FSM 110 is controlled to drive DQs in synchronization with the data output to the DQ lines. In an example burst read operation, FSM 110 is controlled to receive data on DQ lines at each rising and trailing edge of DQS, where DQS is driven by a flash memory target.
When the pass signal is asserted on control FSM 110, control FSM 110 passes the values directly to the flash target control and address lines for the specified duration. In some examples, control FSM 110 may interpret (e.g., by decoding an operation code) one or more of its input lines as a pass-through signal. Control FSM 110 has m outputs coupled to all m inputs of the target flash memory module. In addition, RAM 104 drives n inputs to control FSM 110, including n inputs corresponding to n inputs of the target flash module. The n inputs to control FSM 110 include at least m data bits and may additionally include signals to control FSM 110 that are not passed to the flash memory target. This arrangement allows macro FSM 102 to order the n inputs of the target flash memory module to execute macro level commands. In some examples, the logic of macro FSM 102 and control FSM 110 are combined. In some examples, signals are passed through operation type drivers such that burst reads and permissions are handled by control FSM 110, and other operations are handled by macro FSM 102.
In some examples, the initialization processor 120 is coupled to the non-volatile memory 121 and the RAM 104. The initialization processor 120 may load a set of macros into the memory 104 as part of the initialization of the system 100. When a new flash target is introduced, the memory expert may prepare and adjust a set of macro commands to augment the existing macro library stored in the non-volatile memory 121. These new macrocommand sets will be loaded the next time the system 100 is initialized. In another example, a memory expert may discover an alternative to a problem for a particular flash target and may update one or more macros in a macro library. For example, an alternative may require longer setup and hold times for one or more steps in the command.
Fig. 2 is a diagram of signal timing provided to a flash memory according to an example of the present disclosure. The signals are timed according to the instruction table in fig. 3. Timing diagram 200 includes times 210-206 corresponding to the timing of instructions issued by macro FSM 102 when executing an example macro. Ce_n is a chip enable signal with inversion logic. CLE is a command latch enable signal. ALE is the address latch enable signal t. We_n is a write enable signal with inversion logic. RE_t and RE_c form a differential pair (with true and complement logic values, respectively) representing a read enable signal. DQS_t and DQS_c form a differential pair representing the data strobe signal. DQ [0:0 is an eight bit data bus that may carry address or data values.
Fig. 3 is an instruction table stored in macro memory according to an example of the present disclosure. Each instruction includes a value corresponding to each input of the flash memory target. Each instruction also includes a time period for holding those values on the flash memory input. Each instruction also includes an indication of whether the dynamic data from register 103 should override the data bus (dq) line. Instruction 0x00 executes at time 201 and holds the specified value for a time between times 201 and 202 (i.e., t CS Subtracting t CALS ). Instruction 0x01 executes at time 202 and holds the specified value for between times 202 and 203The time between (i.e., t CALS Subtracting t wP ). Instruction 0x02 executes at time 203 and holds the specified value for a time between times 203 and 204 (i.e., t CAS ). Instruction 0x03 executes at time 204 and holds the specified value for a time between times 204 and 205 (i.e., t CAH ). Note that instructions 0x02 and 0x03 also pass the address value embedded in the call of the macro by asserting the DQOE. Asserting the DQOE selects the dynamic value from register 103 to pass to the flash target instead of the static value from RAM 104. Instruction 0x04 executes at time 205 and holds the specified value for a time between times 205 and 206 (i.e., t CH Subtracting t CAH ). Instruction 0x05 executes at time 206 and holds the specified value for a time between times 206 and 207 (i.e., t CSD )。
Fig. 4 is a flow chart of a method 400 for issuing commands to flash memory according to some examples of the present disclosure. At block 402, the channel processor sends a macro command to the macro FSM 102, identifying the macro to be executed and providing dynamic data (e.g., partial or full address values) if applicable. Macro FSM 102 receives the macro identification and stores any dynamic data in register 103. In some examples, RAM 104 includes a lookup table that identifies the start and end addresses of each macro instruction sequence. At block 404, macro FSM 102 looks up the macro by macro identification and identifies the first instruction of the macro as the current instruction. At block 404, macro FSM 102 fetches the current instruction and causes RAM 104 to output n data bits, including a bit for each input of the flash memory target and a bit specifying the amount of time the flash memory target input is held at a specified value. At block 406, the macro FSM determines whether the current instruction requires dynamic data. If dynamic data is not required, then at block 408 the macro FSM selects a bits from RAM 104 via mux 106 to add n-a bits from RAM 104 as input to mux 108. If dynamic data is required, then the macro FSM selects a bits from register 103 via mux 106 to add the n-a bits from RAM 104 as input to mux 108. At block 412, macro FSM 102 selects a macro instruction (possibly including a bits from register 103) from RAM 104 to send to control FSM 110 along with a transfer signal to transfer m bits to a flash target for a specified amount of time. At block 414, if the end of the macro has been reached, the macro FSM 102 returns to block 402. At block 414, if the end of the macro has not been reached, the current instruction pointer is incremented before returning to block 404.
Fig. 5 is a flow chart of a method 500 for issuing commands to flash memory according to some examples of the present disclosure. At block 502, macro FSM 102 receives a macro command from a channel processor. Macro FSM 102 locates macro sequences in RAM 104. At block 504, macro FSM 102 addresses the first macro instruction in the sequence and asserts read enable on RAM 104. At block 508, the first macro instruction is passed to and driven on an output line to a flash memory target. If the macro includes additional instructions in the sequence, the method returns to block 504 and advances the macro instruction counter to fetch the next instruction. Otherwise, macro FSM 102 returns to receive the next macro command at block 502.
Fig. 6 is an illustration of a system for issuing commands to flash memory according to an example of the present disclosure. The system 600 includes a macro FSM 602, RAM 604, an output 606 that controls inputs to the FSM 610 and to the flash memory target. Macro FSM 602 may be implemented in software, hardware, or configurable logic to perform the method steps of the examples disclosed herein. Macro FSM 602 accepts commands from the channel processor and may identify macro identifications in specific commands. Macro FSM 602 identifies a first macro command corresponding to the sequence of macro identifications. And macro FSM 602 sends a first macro command to control FSM 610. The control FSM 610 ignores its internal hard coded command sequence and drives the output 606 with the value specified in the first macrocommand. After the first macrocommand value has been output for the duration specified in the macrocommand, control FSM 610 signals to macrocommand FSM 602 to fetch the next macrocommand in the sequence.
Fig. 7 is an illustration of a system for issuing commands to flash memory according to an example of the present disclosure. The system 700 includes a channel processor 701, a macro FSM 702, RAM 704, and an output 706 to an input of a flash memory target. A channel processor is a processor that is used to manage and coordinate reads and writes to a flash memory storage system. The channel processor 701 may be a general purpose processor such as a RISC processor. Channel processor 701 may execute instructions from memory and edit data structures in memory to allow it to prioritize reads and writes to achieve performance guarantees, distribute reads/writes across flash memory targets to distribute workload and heat, and perform other tasks/optimizations. Macro FSM 702 may be implemented in software, hardware, or configurable logic to perform the method steps of the examples disclosed herein. Macro FSM 702 accepts commands from the channel processor and may identify macro identifications in specific commands. Macro FSM 702 identifies a first macro command corresponding to the sequence of macro identifications. And macro FSM 702 sends a first macro command and drives output 706 with the value specified in the first macro command. After the first cmdlet value has been output for the duration specified in the cmdlet, the macro FSM 702 retrieves the next cmdlet in the sequence and continues the method.
Although example embodiments have been described above, other variations and embodiments can be made by the present disclosure without departing from the spirit and scope of these embodiments.
Claims (20)
1. An apparatus, the apparatus comprising:
a first finite state machine comprising a command input for receiving a command from a channel processor, the command comprising a macro identification;
a macro memory for storing a plurality of flash control commands, each flash control command including a plurality of target control values and durations for controlling a flash target; and
a second finite state machine comprising a plurality of control outputs, each control output corresponding to one of a plurality of control inputs on the flash memory target;
wherein in response to a received command, the first finite state machine will locate a sequence of flash control commands associated with the macro identification of the command in the macro memory and sequentially output the first flash control commands in the sequence to the second finite state machine; and is also provided with
Wherein the second finite state machine is to drive each control output of the plurality of control outputs for the duration specified in the current flash control command based on a corresponding value in the first flash control command.
2. The apparatus of claim 1, the apparatus comprising:
a dynamic value selector, the dynamic value selector comprising:
an output coupled to the second finite state machine;
a selection input driven by a dynamic value indication identifier of a current flash control command;
a first selectable input coupled to the macro memory to receive a value from a current flash control command; and
a second selectable input coupled to a buffer in the first finite state machine for storing a dynamic value specified in the command received from the channel processor;
wherein when a dynamic value indication flag is asserted, the second finite state machine will drive a plurality of additional outputs based on the dynamic value stored in the buffer, the additional outputs being used to drive additional inputs on the flash memory target, and
wherein when the dynamic value indication flag is not asserted, the second finite state machine is to drive the plurality of additional outputs based on a plurality of values in the current flash control command.
3. The apparatus of any one of claims 1 to 2, comprising a control selector, the control selector comprising:
an output coupled to the second finite state machine;
a selection input driven by the first finite state machine;
a first input driven by a plurality of values in the command from the channel processor; and
a second input driven by a value in the first flash control command.
4. The device of claim 3, wherein when the control selector select input is asserted, the second finite state machine is to drive the plurality of target control values in a predetermined sequence corresponding to the command from the channel processor.
5. The apparatus of any of claims 3-4, wherein the control selector select input is coupled to a pass-through input to the second finite state machine.
6. The apparatus according to any one of claims 1 to 5, comprising: an initialization processor coupled to the non-volatile memory, the initialization processor for copying each command in the sequence of one or more flash control commands from the non-volatile firmware memory into the macro memory.
7. The apparatus of any of claims 1 to 6, wherein the second finite state machine comprises a predetermined sequence for instructing a flash memory target to perform a function from the set of: burst read, burst write and transfer, wherein:
when the function is a burst read, the controlling finite state machine will drive at least a first portion of the plurality of outputs according to a first predetermined timing sequence,
when the function is burst writing, the control finite state machine will drive at least a second portion of the plurality of outputs according to a second predetermined timing sequence, and
when the function is pass, the control finite state machine will drive each of the plurality of control outputs for a duration specified in the current flash control command based on a corresponding value in the first flash control command.
8. The apparatus of any of claims 1-7, wherein the plurality of control outputs are in one-to-one correspondence with the control inputs of the flash memory target.
9. A method, the method comprising:
receiving a command from a channel processor, the command comprising a macro identification for locating in macro memory a sequence of flash control commands associated with the macro identification, each flash control command comprising a duration and a plurality of target control values corresponding to a plurality of control inputs on a flash target; and
executing a first flash control command in a sequence by:
reading the first flash control command from the macro memory, and
the plurality of target control values from the first flash control command are driven to a plurality of control outputs coupled to the plurality of control inputs on the flash target for at least the first flash control command duration.
10. The method of claim 9, wherein the command from the channel processor comprises a dynamic value, the method comprising:
the dynamic value is stored in a buffer,
executing the current flash memory control command by:
reading the current flash control command of the sequence, the current flash control command including a dynamic data indication identifier,
driving the dynamic value from the buffer to a plurality of additional outputs coupled to an additional plurality of inputs on the flash target when the dynamic value indication flag is asserted, an
When the dynamic value indication flag is not asserted, a static value is driven from the current flash control command of the sequence to the plurality of additional outputs.
11. The method according to any one of claims 9 to 10, the method comprising:
a second finite state machine drives the plurality of control outputs and the plurality of additional outputs,
transmitting a current flash control command from the macro memory to the second finite state machine, and
the command is sent from the channel processor to the second finite state machine.
12. The method according to claim 11, the method comprising:
the first finite state machine recognizes the command as a macro command, and
causing the second finite state machine to pass the current flash control command to the control output.
13. The method according to claim 11, the method comprising:
the first finite state machine recognizes the command as a reserve command, and
causing the second finite state machine to decode and execute the reserve command.
14. The method of claim 13, wherein the reserved command is a burst read command or a burst write command.
15. The method of any of claims 13 to 14, wherein the reserve command for each load is associated in the second finite state machine with a fixed sequence of target control values, each target control value corresponding to one of the plurality of control inputs on the flash memory target.
16. The method of any of claims 9 to 15, comprising copying flash control commands from non-volatile memory to the macro memory.
17. The method of any of claims 10 to 16, wherein each input of the flash target is driven by a bit from the current flash control command or a bit from the buffered dynamic value.
18. A configurable flash memory controller, the configurable flash memory controller comprising:
a channel processor for scheduling commands for controlling flash memory targets;
a first finite state machine with a command input for receiving a command from the channel processor, the command including a macro identification and an indication that the command is a macro command;
a macro memory RAM for storing a plurality of flash control commands, each flash control command including a target control value and a duration corresponding to each input on the flash target; and
a plurality of outputs corresponding to a set of inputs on the flash memory target;
wherein in response to an indication that the flash control command is a macro command, the first finite state machine locates a sequence of flash control commands associated with the macro identification and, for each flash control command in the sequence:
reading the current flash control command of the sequence
The plurality of outputs are driven for at least the first flash control command duration based on the current flash control command target control value.
19. The configurable flash memory controller of claim 18, the configurable flash memory controller comprising a second finite state machine for encoding a predetermined sequence of flash control commands for driving the plurality of outputs in sequence to cause the flash target to perform at least one of a burst read or a burst write.
20. The configurable flash memory controller of any one of claims 18 to 19, comprising a non-volatile memory for storing a sequence of flash control commands.
Applications Claiming Priority (4)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US63/296,626 | 2022-01-05 | ||
| US18/146,715 | 2022-12-27 | ||
| US18/146,715 US20230214121A1 (en) | 2022-01-05 | 2022-12-27 | Protocol Agnostic Control of NAND Flash |
| PCT/US2023/010077 WO2023133114A1 (en) | 2022-01-05 | 2023-01-04 | Protocol agnostic control of nand flash |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117795493A true CN117795493A (en) | 2024-03-29 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202380013080.1A Pending CN117795493A (en) | 2022-01-05 | 2023-01-04 | Protocol independent control of NAND flash memory |
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| Country | Link |
|---|---|
| CN (1) | CN117795493A (en) |
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2023
- 2023-01-04 CN CN202380013080.1A patent/CN117795493A/en active Pending
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