CN117794104A - Circuit board and manufacturing method thereof - Google Patents

Abstract

The invention provides a circuit board and a manufacturing method thereof. The circuit board comprises a circuit substrate, a build-up circuit structure and a metal column. The build-up circuit structure is stacked on the circuit substrate and comprises a dielectric layer, a covering layer and a circuit layer. The dielectric layer is arranged between the covering layer and the circuit substrate. The wiring layer is embedded in the dielectric layer and is covered by the cover layer. The circuit layer comprises a first circuit, a second circuit and a third circuit. The first circuit is electrically connected with the circuit substrate. The third line is exposed at the outer surface of the cover layer. The metal column and the second circuit are of an integrally formed structure, and the metal column protrudes out of the outer surface of the covering layer, wherein the lengths of the metal columns are equal, and the risk of empty welding can be reduced.

Description

Circuit board and manufacturing method thereof

Technical Field

The present invention relates to a circuit board, and more particularly, to a circuit board having at least two circuit layers and a method for manufacturing the circuit board.

Background

With the progress of electronic technology, electronic products are being developed to be light and compact, and the application of high-density interconnection (High Density Interconnector, abbreviated as HDI) circuit boards is becoming wider and wider. In order to meet the requirement of high-density interconnection, the pitch of the contact pads of the circuit board is smaller and smaller, but the contact pads of the circuit board are disadvantageously electrically connected, so that the contact pads of the circuit board are formed into protruding metal columns to increase the solder contact area.

There are two current ways of forming metal pillars. The first is to form metal posts in the openings of the circuit board, followed by grinding and leveling. The metal columns have large height differences and are easy to cause empty welding risks under the influence of grinding precision. The second is to electroplate metal posts on the additional circuit board to form a build-up structure. The combination of the metal column and the connecting pad is affected by the laser precision, so that the smaller the spacing of the connecting pad is, the smaller the area of the connecting pad is, and the manufacturing difficulty is further improved.

Disclosure of Invention

Therefore, an objective of the present invention is to provide a circuit board and a manufacturing method thereof, so as to reduce the risk of soldering and the difficulty of manufacturing.

The invention provides a circuit board, which comprises a circuit substrate, at least one build-up layer circuit structure and a plurality of metal posts. The build-up circuit structure is stacked on the circuit substrate. Each of the build-up circuitry structures includes a dielectric layer, at least one conductive via, a capping layer, and a circuitry layer. The dielectric layer is laminated to the circuit substrate. The conductive blind via is formed within the dielectric layer. The cover layer is arranged on the dielectric layer, wherein the dielectric layer is arranged between the cover layer and the circuit substrate. The wiring layer is embedded in the dielectric layer and covered by the cover layer. The circuit layer comprises at least one first circuit, at least one second circuit and at least one third circuit. The first circuit is electrically connected with the circuit substrate by utilizing the conductive blind hole. The cover layer covers the first circuit and the second circuit. The third line is exposed at the outer surface of the cover layer. The metal posts and the second circuit are integrally formed, and the metal posts protrude out of the outer surface of the covering layer, wherein the lengths of the metal posts are equal.

In at least one embodiment of the present invention, the metal pillar is a tapered pillar.

In at least one embodiment of the invention, each of the metal posts has opposite first and second ends, the first end connecting the second line and the second end protruding beyond the outer surface of the cover layer, the outer diameter of each of the metal posts tapering from the first end toward the second end.

In at least one embodiment of the present invention, each of the second wires has a stop portion abutting the cover layer and abutting the first end of the corresponding metal post.

In at least one embodiment of the invention, each of the third lines has an end face that is flush with the outer surface of the corresponding cover layer.

In at least one embodiment of the present invention, the cover layer has at least one opening, and the third line extends to the opening.

In at least one embodiment of the present invention, the number of the build-up layer circuit structures is two, and the build-up layer circuit structures are respectively disposed on two opposite sides of the circuit substrate.

The invention provides a circuit board, comprising at least one insulating additional circuit board; attaching a double-layer cover film on each of the insulating additional circuit boards, the double-layer cover film comprising a release layer and a cover layer, the release layer being located between the insulating additional circuit boards and the cover layer; forming at least one blind hole and at least one opening in the double-layer covering film, wherein the blind hole extends the covering layer and the release layer, and the opening extends the covering layer, and the depth of the opening is smaller than that of the blind hole; forming a wiring layer and at least one metal post on the double-layer cover film to form a build-up unit on each of the insulated additional circuit boards, wherein the wiring layer is located on the cover layer, a portion of the wiring layer extends to the opening, and the metal post extends to the blind hole and is integrally formed on another portion of the wiring layer; pressing the build-up unit, at least one dielectric layer and a circuit substrate, wherein the dielectric layer is positioned between the corresponding build-up unit and the circuit substrate; and removing the release layer and the insulating additional circuit board.

In at least one embodiment of the present invention, the above manufacturing method removes the insulating additional circuit board before laminating the build-up unit, the dielectric layer and the circuit substrate.

In at least one embodiment of the present invention, the above manufacturing method removes the insulating additional circuit board after laminating the build-up unit, the dielectric layer and the circuit substrate.

In at least one embodiment of the present invention, the above manufacturing method uses a laser to form the blind hole and the opening on the double-layer covering film.

In at least one embodiment of the present invention, in the above manufacturing method, the cover layer has photosensitivity, and the opening is formed in the double-layer cover film by exposure and development.

In at least one embodiment of the present invention, the above-mentioned manufacturing method uses electroless plating and electroless plating to form the circuit layer and the metal pillar on the double-layer cover film.

Based on the above, the lengths of the metal columns are equal, so that the risk of empty welding can be reduced. The metal column and the third line are of an integrally formed structure, and the binding force is good. The circuit layer is embedded in the dielectric layer to improve the adhesion. The third circuit is exposed on the outer surface of the covering layer, so that the influence of the precision of the subsequent exposure process can be avoided, and the manufacturing difficulty is reduced. The circuit layer provides circuits with different thicknesses, and can manufacture local thick circuits bearing larger current.

Drawings

The foregoing and other objects, features, advantages and embodiments of the invention will be apparent from the following description of the drawings.

Fig. 1 is a schematic cross-sectional view of a circuit board according to at least one embodiment of the invention.

Fig. 2A to 2F are cross-sectional views illustrating a method for manufacturing a circuit board according to at least one embodiment of the invention.

It should be noted that the various features of the drawings are not drawn to scale in accordance with industry practice standards. The dimensions of the various features may be arbitrarily increased or reduced for clarity of understanding.

Detailed Description

Embodiments of the present invention are discussed in detail below. However, it is to be understood that the embodiments provide many applicable concepts that can be embodied in a wide variety of specific contexts. The embodiments discussed and disclosed are merely illustrative and are not intended to limit the scope of the invention. For example, a recitation of "a first feature being formed on a second feature" includes embodiments where the first feature is in direct contact with the second feature, as well as embodiments where other features are formed between the first feature and the second feature, such that the first feature and the second feature are not in direct contact.

In addition, spatially relative terms, such as "below," "above," and the like, may be used for brevity and clarity in describing the relationship of an element or feature to another element or feature depicted in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The spatially relative descriptions used herein may also be construed accordingly when the elements are otherwise oriented (rotated 90 degrees or in other directions).

Referring to fig. 1, a schematic cross-sectional view of a circuit board 100 according to at least one embodiment of the invention is shown. The circuit board 100 includes a circuit substrate 101, a build-up circuit structure 102, and a plurality of metal pillars 103. The build-up circuit structure 102 is stacked on the circuit substrate 101, and the build-up circuit structure 102 is electrically connected to the circuit substrate 101. The metal pillars 103 are formed on the build-up circuitry 102 to increase the bonding contact area.

With continued reference to fig. 1, the build-up circuitry 102 includes a dielectric layer 1021, conductive via 1021h, a capping layer 1022 and a circuitry layer 1023. The dielectric layer 1021 is stacked on the circuit substrate 101. A conductive via 1021h is formed within the dielectric layer 1021. The cover layer 1022 is disposed on the dielectric layer 1021, wherein the dielectric layer 1021 is located between the cover layer 1022 and the circuit substrate 101. The circuit layer 1023 is embedded in the dielectric layer 1021 and covered by the cover layer 1022 to improve adhesion between the circuit layer 1023 and the dielectric layer 1021.

The circuit layer 1023 includes a first circuit 1023a, a second circuit 1023b, and a third circuit 1023c. The first circuit 1023a electrically connects the circuit substrate 101 using the conductive blind via 1021h. The cover layer 1022 covers the first line 1023a and the second line 1023b, i.e., the first line 1023a and the second line 1023b are not exposed on the outer surface 1022s of the cover layer 1022. The third line 1023c is exposed on the outer surface 1022s of the cover 1022, which is not affected by the precision of the subsequent exposure process. The thickness of the third line 1023c is greater than that of the first line 1023a and the thickness of the second line 1023b, i.e. the thickness of the line layer 1023 is not consistent, so that a locally thick line can be provided to withstand a larger current.

With continued reference to fig. 1, the metal pillars 103 and the second circuit 1023b are integrally formed, so that the bonding force is good, and the metal pillars 103 protrude from the outer surface 1022s of the cover 1022, wherein the lengths of the metal pillars 103 are equal, so that the risk of soldering is reduced.

With continued reference to fig. 1, the metal post 103 has a first end 103a and a second end 103b opposite to each other. The first end 103a of the metal post 103 is connected to the second line 1023b. The second ends 103b of the metal posts 103 protrude beyond the outer surface 1022s of the cover 1022. Wherein, the metal pillar 103 is a tapered pillar, and an outer diameter D of the metal pillar 103 tapers from the first end 103a toward the second end 103b. I.e. the outer diameter D at the first end 103a of the metal post 103 is the maximum outer diameter D of the metal post 103.

With continued reference to fig. 1, the second line 1023b has a stop portion 1023bs, the stop portion 1023bs abuts the first end 103a of the metal pillar 103, and the cover 1022 covers and abuts the stop portion 1023bs of the second line 1023b. I.e. the maximum outer diameter D of the metal post 103 is smaller than the width of the second line 1023b.

With continued reference to fig. 1, the outer surface 1022s of the cover 1022 forms an opening 1022o, and the third line 1023c extends to the opening 1022o. Wherein the end face 1023cs of the third line 1023c is located entirely at the opening 1022o, i.e., the end face 1023cs of the third line 1023c is entirely exposed at the outer surface 1022s of the cover 1022, i.e., the third line 1023c is not covered by the cover 1022. In some embodiments, the end face 1023cs of the third line 1023c is flush with the outer surface 1022s of the cover 1022, i.e., the end face 1023cs of the third line 1023c does not protrude beyond the outer surface 1022s of the cover 1022.

As shown in fig. 1, the circuit substrate 101 includes a first circuit layer 1011, a second circuit layer 1012, and an insulating layer 1013. The insulating layer 1013 is located between the first wiring layer 1011 and the second wiring layer 1012, and a blind via 1013h is provided in the insulating layer 1013. The first wiring layer 1011 and the second wiring layer 1012 are electrically connected through the blind via 1013h. The circuit layer of the circuit substrate 101 is not limited to the first circuit layer 1011 and the second circuit layer 1012, and in some embodiments, the circuit substrate 101 may be a multi-layer circuit board having more than two circuit layers.

With continued reference to fig. 1, the number of the build-up circuit structures 102 may be two, and the two build-up circuit structures 102 may be disposed on two opposite sides of the circuit substrate 101, i.e. one build-up circuit structure 102 is electrically connected to the first circuit layer 1011 of the circuit substrate 101 by using the conductive blind holes 1021h, and the other build-up circuit structure 102 is electrically connected to the second circuit layer 1012 of the circuit substrate 101 by using the conductive blind holes 1021h.

Referring to fig. 2A to 2F, a cross-sectional view of a method for manufacturing a circuit board 100 according to at least one embodiment of the invention is shown, wherein the method disclosed in fig. 2A to 2F can be used to manufacture the circuit board 100. As shown in fig. 2A, first, an insulating additional circuit board 200 is provided.

Next, as shown in fig. 2B, a double-layer cover film 201 is attached to the insulating additional circuit board 200. Wherein the dual-layer cover film 201 comprises a release layer 2011 and a cover layer 1022, and the release layer 2011 is located between the insulating additional circuit board 200 and the cover layer 1022. In some embodiments, a double-layer cover film 201 may be attached to one side of the additional circuit board 200. In some embodiments, the double-layer cover film 201 may be attached to two opposite sides of the additional circuit board 200, and double-sided fabrication may be used to improve the process efficiency.

Next, as shown in fig. 2C, a blind hole 201h and an opening 1022o are formed in the dual-layer cover film 201. Wherein the blind hole 201h extends the cover layer 1022 and the release layer 2011, and the opening 1022o extends the cover layer 1022 but does not extend into the release layer 2011, so the depth of the opening 1022o is smaller than the depth of the blind hole 201 h. In other words, the depth of the blind via 201h is substantially equal to the sum of the thickness of the cover layer 1022 and the thickness of the release layer 2011, and the depth of the opening 1022o is substantially equal to the thickness of the cover layer 1022. In some embodiments, the blind holes 201h and the openings 1022o can be formed on the dual-layer film 201 by using a laser, and the blind holes 201h and the openings 1022o can be formed by using a laser disposable process, so that the condition that the secondary process reduces the precision can be avoided, and good precision can be provided.

In some embodiments, the cover layer 1022 has photosensitivity, and an opening 1022o can be formed in the dual-layer cover film 201 by exposure and development. In the above description, the side wall of the opening 1022o may be perpendicular to the connection surface where the release layer 2011 is attached to the cover layer 1022, or the side wall of the opening 1022o may be inclined to the connection surface where the release layer 2011 is attached to the cover layer 1022.

Next, as shown in fig. 2D, a wiring layer 1023 and a metal pillar 103 are formed on the double-layer cover film 201 to form a build-up unit 202 on the insulating additional circuit board 200. Wherein the wiring layer 1023 is located on the cover layer 1022, a portion of the wiring layer 1023 extends to the opening 1022o, and the metal pillar 103 extends into the blind via 201h, and the metal pillar 103 is integrally formed on another portion of the wiring layer 1023. The length L of the metal pillar 103 is determined by the depth of the blind hole 201 h. Referring to fig. 2C, the depths of the blind holes 201h are equal to each other, and referring to fig. 2D, the lengths of the metal pillars 103 formed by filling the blind holes 201h are also equal to each other, i.e., the heights of the metal pillars 103 are equal. In some embodiments, electroless plating and electroless plating may be utilized to form the wiring layer 1023 and the metal posts 103 on the bilayer cover film 201.

Next, as shown in fig. 2E and fig. 2F, the build-up unit 202, the dielectric layer 1021 and the circuit substrate 101 are laminated. Wherein the dielectric layer 1021 is located between the build-up unit 202 and the circuit substrate 101, and the build-up unit 202 is electrically connected to the circuit substrate 101 by the conductive via 1021h of the dielectric layer 1021. In some embodiments, a metal paste such as copper may be filled into the dielectric layer 1021 to form the conductive via 1021h. In some embodiments, a semi-cured film (prepreg) is used as the dielectric layer 1021, and the semi-cured film is softened under heating and pressure, may even have fluidity, and is solidified after cooling, so that the dielectric layer 1021 can soften, flow and fill gaps when laminating the build-up unit 202, the dielectric layer 1021 and the circuit substrate 101 to bond the build-up unit 202 and the circuit substrate 101.

With continued reference to fig. 2E, the build-up unit 202 is bonded on opposite sides of the circuit substrate 101 with a dielectric layer 1021. That is, the number of the circuit substrates 101 is one, the number of the dielectric layers 1021 is two and is respectively located at two opposite sides of the circuit substrates 101, and the number of the build-up units 202 is two and is respectively located at the outer sides of the two dielectric layers 1021. Namely, the dielectric layer 1021 and the build-up unit 202 are sequentially disposed above the circuit substrate 101, and the dielectric layer 1021 and the build-up unit 202 are also sequentially disposed below the circuit substrate 101. After the circuit substrate 101, the dielectric layer 1021 and the build-up unit 202 are disposed relatively, the dielectric layer 1021 is bonded to the circuit substrate 101 and the build-up unit 202 by using a lamination method.

As shown in fig. 1, the release layer 2011 and the insulating additional circuit board 200 are removed to form the circuit board 100 with the metal posts 103. In some embodiments, the insulating additional circuit board 200 may be removed prior to lamination of the build-up unit 202, the dielectric layer 1021, and the circuit substrate 101. In some embodiments, the insulation additional circuit board 200 and the release layer 2011 may be removed after the build-up unit 202, the dielectric layer 1021 and the circuit substrate 101 are pressed together, wherein the release layer 2011 may be removed after the insulation additional circuit board 200 is removed. Since the release layer 2011 participates in the lamination operation, the release layer 2011 is used for protecting the metal column 103, so that the metal column 103 is not affected in the lamination process.

As is apparent from the above embodiments, the manufacturing method described above allows the manufactured circuit board 100 to have the metal posts 103 with the same height, and reduces the risk of empty soldering of the circuit board 100 by improving the grasp of the height of the metal posts 103. The circuit layer 1023 is embedded in the dielectric layer 1021 to improve adhesion. By using the structure in which the metal posts 103 are integrally formed with the third lines 1023c of the line layer 1023, the bonding force between the metal posts 103 and the third lines 1023c can be improved. By using the above manufacturing method, the third line 1023c is directly exposed on the outer surface 1022s of the cover layer 1022, so that the precision of the subsequent exposure process is not affected, and the manufacturing difficulty is reduced. The thickness of the third line 1023c is greater than that of the first line 1023a and also greater than that of the second line 1023b, so that the line layer 1023 can provide lines with different thicknesses, and a locally thick line bearing a large current can be manufactured.

Although the present invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but may be variously modified and modified by those skilled in the art without departing from the spirit and scope of the present invention, and the scope of the present invention is defined by the appended claims.

[ symbolic description ]

100 circuit board

101 Circuit Board

102 build-up circuitry structure

103 Metal column

103a first end

103b second end

200 insulating additional circuit board

201 double layer cover film

201h blind hole

202 cover layer

1011 first circuit layer

1012 second circuit layer

1013 insulating layer

1013h blind hole

1021 dielectric layer

1021h conductive blind hole

1022 cover layer

1022o opening

1022s outer surface

1023 Circuit layer

1023a first line

1023b second line

1023bs, face guard

1023c third line

1023cs end face

2011 release layer

Length L

D, outer diameter.

Claims (10)

1. A circuit board, the circuit board comprising:

a circuit substrate;

at least one build-up circuit structure stacked on the circuit substrate, each of the build-up circuit structures comprising:

a dielectric layer stacked on the circuit substrate;

at least one conductive blind via is formed in the dielectric layer;

a cover layer, which is arranged on the dielectric layer, wherein the dielectric layer is arranged between the cover layer and the circuit substrate; and

a wiring layer embedded in the dielectric layer and covered by the cover layer, the wiring layer comprising:

at least one first circuit electrically connected with the circuit substrate by the conductive blind hole, wherein the cover layer covers the first circuit;

at least one second circuit, the said cover layer covers the said second circuit; and

at least one third circuit exposed out of the outer surface of the covering layer; and

the metal posts and the second circuit are of an integrally formed structure, and the metal posts protrude out of the outer surface of the covering layer, wherein the lengths of the metal posts are equal.

2. The circuit board of claim 1, wherein the metal posts are tapered posts.

3. The circuit board of claim 2, wherein each of the metal posts has opposite first and second ends, the first end connecting the second circuit and the second end protruding beyond the outer surface of the cover layer, the outer diameter of each of the metal posts tapering from the first end toward the second end.

4. A circuit board according to claim 3, wherein each of the second wires has a stop portion abutting the cover layer and abutting the first end of the corresponding metal post.

5. The circuit board of claim 1, wherein each of the third lines has an end face that is flush with the outer surface of the corresponding cover layer.

6. The circuit board of claim 1, wherein the cover layer has at least one opening, the third line extending to the opening.

7. The circuit board of claim 1, wherein the number of build-up circuitry structures is two and is disposed on opposite sides of the circuit substrate.

8. A method of manufacturing a circuit board, the method comprising:

providing at least one insulating additional circuit board;

attaching a double-layer cover film on each of the insulating additional circuit boards, the double-layer cover film comprising a release layer and a cover layer, the release layer being located between the insulating additional circuit boards and the cover layer;

forming at least one blind hole and at least one opening in the double-layer covering film, wherein the blind hole extends the covering layer and the release layer, and the opening extends the covering layer, and the depth of the opening is smaller than that of the blind hole;

forming a wiring layer and at least one metal post on the double-layer cover film to form a build-up unit on each of the insulated additional circuit boards, wherein the wiring layer is located on the cover layer, a portion of the wiring layer extends to the opening, and the metal post extends to the blind hole and is integrally formed on another portion of the wiring layer;

pressing the build-up unit, at least one dielectric layer and a circuit substrate, wherein the dielectric layer is positioned between the corresponding build-up unit and the circuit substrate; and

and removing the release layer and the insulating additional circuit board.

9. The method of manufacturing a circuit board according to claim 8, wherein the blind via and the opening are formed in the double-layered cover film by using a laser.

10. The method of manufacturing a circuit board according to claim 8, wherein the cover layer has photosensitivity, and the opening is formed in the double-layered cover film by exposure and development.