CN117792840A - DC offset measurement circuit and method thereof, power measurement circuit and radio frequency transceiver - Google Patents
DC offset measurement circuit and method thereof, power measurement circuit and radio frequency transceiver Download PDFInfo
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Abstract
The invention relates to an integrated circuit, and discloses a direct current offset measuring circuit and a method thereof, a power measuring circuit and a radio frequency transceiver. The DC offset measurement circuit includes: a sigma-delta ADC including a sigma-delta integrator, a single-bit quantizer for single-bit quantizing an output of the sigma-delta integrator, a positive pulse counter and a negative pulse counter for pulse counting an output of the single-bit quantizer, and a difference calculator; the difference calculator outputs an absolute value of a difference between the count value of the positive pulse counter and the count value of the negative pulse counter, the absolute value of the difference representing an estimate of the dc offset of the input voltage. The DC offset measurement circuit remarkably improves the temperature and process independence, reduces the production and integration cost, and improves the system time sequence budget.
Description
Technical Field
The present invention relates to integrated circuits, and more particularly to dc offset measurement techniques and power measurement techniques.
Background
This section is intended to provide a background or context to the embodiments of the invention that are recited in the claims. The statements in this section are to be read in this light, and not as admissions or confirmations of prior art.
In the field of high-speed wireless communications, in particular millimeter-wave (mmWave) technology and automotive applications, the performance of the transceiver is critical. Millimeter wave transceivers are widely used in 5G networks, automotive radar systems, wireless local area networks, and other scenarios requiring high data transmission rates due to their high frequency characteristics. In particular, in the automotive industry, millimeter wave transceivers play a central role in Advanced Driving Assistance Systems (ADAS) and autopilot technologies, and can utilize millimeter wave radars to detect and analyze the surrounding environment of a vehicle, thereby realizing vehicle positioning, obstacle detection and collision prevention.
However, the prior art uses dedicated Hardware (HW) components, such as sensors and dedicated analog-to-digital converters (ADCs), to measure the dc offset and power level of the receive link in all transceivers. These specialized hardware present some challenges, including:
temperature and process dependence: the performance of dedicated hardware components, such as sensors and ADCs, is sensitive to temperature and process variations, leading to inconsistencies and inaccuracies in the measurement results. This dependence requires a large amount of characterization data and statistical analysis to compensate.
Production and integration costs: the dedicated hardware introduced to achieve dc offset and power measurement increases production costs and complexity. These additional components require special calibration, additional power consumption and design considerations, adding to the overall manufacturing cost.
Compromise of system timing budget: traditional measurement methods rely on fully converged and post-processing algorithms of the receive chain ADC, possibly introducing significant timing delays, possibly affecting the timing budget of the overall system.
Accordingly, developing new measurement methods and techniques to overcome these challenges and improve the performance and reliability of millimeter wave transceivers in applications such as automobiles has become a key direction in the development of technology.
Disclosure of Invention
The invention aims to provide a direct current offset measuring circuit and a method thereof, a power measuring circuit and a radio frequency transceiver, which eliminate the need for special hardware, sensors and ADC post-processing, thereby remarkably improving the temperature and process independence, reducing the production and integration cost and improving the time sequence budget of a system.
The invention discloses a DC offset measurement circuit, comprising:
a sigma-delta ADC comprising a sigma-delta integrator, an input of the sigma-delta ADC being coupled to an input voltage;
a single bit quantizer having an input coupled to the output of the sigma delta integrator;
a positive pulse counter having an input coupled to the output of the single bit quantizer, configured to count positive pulses of the output of the single bit quantizer;
a negative pulse counter having an input coupled to the output of the single bit quantizer, configured to count negative pulses of the output of the single bit quantizer; and
and a difference calculator having two input terminals coupled to the output terminals of the positive pulse counter and the negative pulse counter, respectively, the difference calculator outputting an absolute value of a difference between the count value of the positive pulse counter and the count value of the negative pulse counter, the absolute value of the difference representing an estimate of the dc offset of the input voltage.
In a preferred embodiment, the positive pulse counter includes:
a clock;
a first analog comparator having a positive input coupled to the output of the single bit quantizer and a negative input coupled to a first reference voltage;
a first AND gate having two inputs coupled to the output of the first analog comparator and the output of the clock, respectively; and
a first counter having an input coupled to the output of the first and gate is configured to count the high signal every clock cycle.
In a preferred embodiment, the undershoot counter includes:
a second analog comparator having a negative input coupled to the output of the single bit quantizer and a positive input coupled to a second reference voltage;
a second AND gate having two inputs coupled to the output of the second analog comparator and the output of the clock, respectively; and
a second counter having an input coupled to the output of the second and gate is configured to count the low level signal every clock cycle.
In a preferred embodiment, the first reference voltage is between a low level and a high level of the single bit quantizer output;
the second reference voltage is between a low level and a high level of the single bit quantizer output.
In a preferred embodiment, the first counter includes a hit port and a reset port, and the hit port issues a hit signal when a count value of the first counter reaches a predetermined threshold; the hit port is coupled to the reset port via a delay;
the second counter includes a reset port coupled to the hit port of the first counter via a delay.
In a preferred embodiment, the difference calculator comprises a reset port coupled to the hit port of the first counter via a delay.
The invention also discloses a direct current offset measurement method, which comprises the following steps:
single-bit quantization is carried out on the electric signal output by the sigma-delta integrator in the sigma-delta ADC, so as to obtain a single-bit quantized signal;
respectively counting positive pulses and negative pulses generated by the single-bit quantized signals to obtain positive pulse count values and negative pulse count values; and
an absolute value of a difference between the positive pulse count value and the negative pulse count value is calculated, the absolute value of the difference representing an estimate of a dc offset of the input voltage of the sigma delta ADC.
The invention also discloses a power measurement circuit, which comprises:
a dc offset measurement circuit as described hereinbefore;
and the power calculation circuit is coupled with the direct current offset measurement circuit and calculates power according to the estimated value of the direct current offset output by the direct current offset measurement circuit.
In a preferred embodiment, the dc offset measurement circuit is configured to detect a dc offset of the rf transceiver receive link.
In a preferred embodiment, the method further comprises:
a power measurement circuit for power measurement of the radio frequency transceiver receive link; and
and the direct current offset adjusting circuit is used for adjusting the direct current offset of the receiving link of the radio frequency transceiver according to the estimation of the direct current offset output by the direct current offset measuring circuit so as to improve the accuracy of power measurement of the power measuring circuit.
Embodiments of the present invention have the following advantages over the prior art:
temperature and process independence: by utilizing the existing sigma delta ADC integrator output, the measurement system is largely independent of temperature and process variations, eliminating the need for extended features and statistical analysis.
Production and integration costs are reduced: eliminating dedicated hardware for dc offset and power measurement can significantly reduce production costs and complexity, thereby enabling a more compact, cost-effective design.
Improved system time budget: by eliminating ADC post-processing, the scheme of the embodiment of the invention reduces time sequence delay to the greatest extent, thereby realizing a system with higher efficiency and more sensitive response.
The technical features disclosed in the above summary, the technical features disclosed in the following embodiments and examples, and the technical features disclosed in the drawings may be freely combined with each other to constitute various novel technical solutions (which should be regarded as having been described in the present specification) unless such a combination of technical features is technically impossible. For example, in one example, feature a+b+c is disclosed, in another example, feature a+b+d+e is disclosed, and features C and D are equivalent technical means that perform the same function, technically only by alternative use, and may not be adopted simultaneously, feature E may be technically combined with feature C, and then the solution of a+b+c+d should not be considered as already described because of technical impossibility, and the solution of a+b+c+e should be considered as already described.
Drawings
FIG. 1 is a schematic diagram of a DC offset measurement circuit according to one embodiment of the invention;
fig. 2 is a schematic diagram of a dc offset measurement circuit according to one embodiment of the invention.
Detailed Description
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be understood by those skilled in the art that the claimed invention may be practiced without these specific details and with various changes and modifications from the embodiments that follow.
Some well-known structures, steps, or functions may not be described in detail in order to avoid unnecessarily obscuring the relevant description. The details of these structures, steps, or functions may be found by those skilled in the art by looking up the relevant publications.
The terminology used in the description presented below is intended to be interpreted in its broadest reasonable manner, even though it is being used in conjunction with a detailed description of specific examples of the invention. Certain terms may be emphasized in the following description; however, any terms intended to be interpreted in any limited manner will be defined explicitly and specifically in this detailed description section.
Description of the partial concepts:
ADC: analog-to-Digital Converter) for converting an Analog signal (e.g., voltage) to an electronic device that is a digital signal.
Sigma-delta ADC: a high-precision ADC. It converts an analog signal into a digital signal by sigma-delta modulation. The sigma-delta integrator is an important component of the sigma-delta ADC.
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in further detail below with reference to the accompanying drawings.
A first embodiment of the present invention relates to a dc offset measurement circuit, as shown in fig. 1, including:
a sigma-delta ADC 101 comprising a sigma-delta integrator 102, an input of the sigma-delta ADC 101 being coupled to an input voltage Vin;
a single bit quantizer 103 having an input coupled to the output of the sigma-delta integrator 102;
a positive pulse counter 104 having an input coupled to the output of the single bit quantizer 103, configured to count positive pulses of the output of the single bit quantizer 103;
a negative pulse counter 105 having an input coupled to the output of the single bit quantizer 103, configured to count negative pulses of the output of the single bit quantizer 103; and
a difference calculator 106 having two inputs coupled to the outputs of the positive pulse counter 104 and the negative pulse counter 105, respectively, the difference calculator 106 outputting an absolute value of a difference between the count value of the positive pulse counter 104 and the count value of the negative pulse counter 105, the absolute value of the difference representing an estimate of the dc offset of the input voltage. The difference calculator 106 may comprise a subtractor and a unit for calculating the absolute value, or a processor may be used to perform the subtraction and absolute value operations. The processor may be a central processing unit (Central Processing Unit, abbreviated as "CPU"), an image processor (Graphic Processing Unit, abbreviated as "GPU"), a digital signal processor (Digital Signal Processor, abbreviated as "DSP"), a micro control unit (Microcontroller Unit, abbreviated as "MCU"), a neural network processor (abbreviated as "NPU"), an application specific integrated circuit (Application Specific Integrated Circuit, abbreviated as "ASIC"), an off-the-shelf programmable gate array (Field Programmable Gate Array, abbreviated as "FPGA"), or other programmable logic device, etc.
In this embodiment, each clock cycle is a pulse, and a positive pulse is a high-level pulse and a negative pulse is a low-level pulse. The high level and the low level are relatively high, and the high level is higher than the low level. The low level is not necessarily a negative voltage, for example the negative pulse may be 0V. Also, the high level is not necessarily a positive voltage.
Rather than redesigning the entire ADC, embodiments of the present invention utilize the output of a portion of the prior art sigma-delta ADC (sigma-delta integrator). The sigma-delta integrator is an important component in the sigma-delta ADC, responsible for processing the input signal and converting it into a form suitable for digital conversion. The sigma delta ADC itself is a prior art, the structure of which is not an innovation of the present invention and is not described in detail here. The sigma-delta ADC still works properly, and the additional circuitry of the embodiments of the present invention does not affect the normal operation of the sigma-delta ADC.
Optionally, in one embodiment, a single-bit quantizer is also included in the sigma-delta ADC 101, and the input of the single-bit quantizer is coupled to the output of the sigma-delta integrator 102. In this case, the single-bit quantizer in the sigma-delta ADC 101 is directly used as the single-bit quantizer 103 in the dc offset measurement circuit, so that a separate single-bit quantizer 103 can be further saved. In other words, the present embodiment makes more full use of the inherent components in the sigma-delta ADC (sigma-delta integrator and single bit quantizer) than the embodiment of fig. 1, so that one single bit quantizer 103 can be reduced in the newly added circuit, thereby further reducing the cost.
Optionally, in an embodiment, as shown in fig. 2, a specific implementation of the positive pulse counter 104 and the negative pulse counter 105 is further provided on the basis of fig. 1. Wherein,
the positive pulse counter 104 includes:
a clock 107;
a first analog comparator 1041 having a positive input coupled to the output of the single bit quantizer 103 and a negative input coupled to the first reference voltage V1;
a first and gate 1042 having two inputs coupled to the output of the first analog comparator 1401 and the output of the clock, respectively; and
a first counter 1043, an input of which is coupled to an output of the first and gate 1402, is configured to count high signals every clock cycle.
The negative pulse counter 105 includes:
a second analog comparator 1051 having a negative input coupled to the output of the single bit quantizer 103 and a positive input coupled to the second reference voltage V2;
a second and gate 1052 having two inputs coupled to the output of the second analog comparator 1501 and the output of the clock 107, respectively; and
a second counter 1053, an input of which is coupled to the output of the second and gate 1052, is configured to count the low level signal every clock cycle.
Alternatively, in one embodiment, the first reference voltage and the second reference voltage are both between a low level and a high level of the output of the single bit quantizer 103. The first reference voltage and the second reference voltage may be the same voltage or different voltages. For example, the single bit quantizer 103 outputs a low level of 0V and a high level of 5V, the first reference voltage may be 2V, and the second reference voltage may be 3V. As another example, the low level of the output of the single bit quantizer 103 is-3V, the high level is 3V, and the first reference voltage and the second reference voltage may both be 0V.
Optionally, in one embodiment, the first counter 1043 includes a hit port and a reset port, and the hit port issues a hit signal when the count value of the first counter 1043 reaches a predetermined threshold. The hit port is coupled to the reset port through a first delay. The second counter 1053 includes a reset port coupled to the hit port of the first counter 1043 through a second delay. The difference calculator 106 includes a reset port coupled to the hit port of the first counter via a delay. Details of this embodiment, including the first delay, and hit and reset ports of the two counters, the reset port of the difference calculator 106, and the like, are not shown in fig. 2.
The above-described embodiments address key challenges of temperature and process dependencies, production costs, and limited system time budget by eliminating the need for dedicated hardware, sensors, and ADC post-processing, paving the way for more robust, cost-effective, and performance-optimized transceiver designs.
A second embodiment of the present invention relates to a dc offset measurement method, the flow of which is shown in fig. 2, the method comprising the steps of:
the single-bit quantizer is used for carrying out single-bit quantization on the electric signal output by the sigma-delta integrator in the sigma-delta ADC to obtain a single-bit quantized signal;
respectively counting positive pulses and negative pulses generated by a single-bit quantized signal through a counter to obtain a positive pulse count value and a negative pulse count value; and
the absolute value of the difference between the positive pulse count value and the negative pulse count value, which represents an estimate of the dc offset of the input voltage of the sigma-delta ADC, is calculated by the arithmetic unit.
The positive pulse and the negative pulse can be obtained by periodically sampling a single-bit quantized signal based on a clock signal.
The first embodiment is a product embodiment corresponding to the present embodiment, and the technical details in the first embodiment can be applied to the present embodiment.
A third embodiment of the present invention relates to a dc offset measurement power measurement circuit including:
the dc offset measurement circuit disclosed in the first embodiment; and
and the power calculation circuit is coupled with the direct current offset measurement circuit and calculates power according to the estimated value of the direct current offset output by the direct current offset measurement circuit.
The correction of the power calculation according to the dc offset or the participation in the power calculation as one of the parameters is possible in the prior art. And will not be described in detail herein. Optionally, in one embodiment, the power measurement circuit further includes a voltage measurement circuit and a current measurement circuit, calculates power according to a voltage value output by the voltage measurement circuit and a current value output by the current measurement circuit, and corrects the calculated power value using an estimated value of the dc offset output by the dc offset measurement circuit.
A fourth embodiment of the invention is directed to a radio frequency transceiver comprising the dc offset measurement circuit of the first embodiment configured to detect a dc offset of a radio frequency transceiver receive chain.
Optionally, in one embodiment, the radio frequency transceiver further comprises:
a power measurement circuit for power measurement of the radio frequency transceiver receiving link; and
and the direct current offset adjusting circuit is used for adjusting the direct current offset according to the estimation of the direct current offset output by the direct current offset measuring circuit so as to improve the power measurement precision of the power measuring circuit.
The method of adjusting the dc offset according to the estimation of the dc offset may be various. For example, the dc offset may be adjusted in the direction of 0, and reducing the dc offset may generally improve the accuracy of the power measurement circuit. For another example, compensation values of several dc offsets with specific magnitudes may be calibrated in advance, the closest calibrated dc offset may be adjusted according to the estimated value of the current dc offset, and when the current dc offset is adjusted to the vicinity of one of the calibrated dc offsets, the power measurement measured by the power measurement circuit may be continuously compensated by using the corresponding compensation value.
Various circuits of the present invention may be used in integrated circuits (or chips).
It is noted that in the present disclosure, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In the present invention, if it is mentioned that a certain action is performed according to a certain element, it means that the action is performed at least according to the element, and two cases are included: the act is performed solely on the basis of the element and is performed on the basis of the element and other elements. Multiple, etc. expressions include 2, 2 times, 2, and 2 or more, 2 or more times, 2 or more.
The terms "connected," "coupled," or any variant thereof, mean any connection or coupling, either direct or indirect, between elements, and may encompass the presence of intervening elements between two elements that are "connected" or "coupled" together via the intervening elements. The coupling and/or connection between the elements may be physical, logical, or a combination thereof. As employed herein, elements may be "connected" or "coupled" together through the use of one or more wires, cables, and/or printed circuit connections, as well as through the use of electromagnetic energy. Electromagnetic energy may have wavelengths in the radio frequency region, the microwave region, and/or the optical (both visible and invisible) region. The above examples are non-limiting and non-exhaustive.
This specification includes combinations of the various embodiments described herein. Separate references to embodiments (e.g., "one embodiment" or "some embodiments" or "preferred embodiments") do not necessarily refer to the same embodiment; however, unless indicated as mutually exclusive or as would be apparent to one of skill in the art, the embodiments are not mutually exclusive. It should be noted that the term "or" is used in this specification in a non-exclusive sense unless the context clearly indicates otherwise or requires otherwise.
All references mentioned in this disclosure are to be considered as being included in the disclosure of the invention in its entirety so that modifications may be made as necessary. Further, it is understood that various changes and modifications of the invention may be made by those skilled in the art after reading the disclosure of the invention, and such equivalents are intended to fall within the scope of the invention as claimed.
Claims (10)
1. A dc offset measurement circuit, comprising:
a sigma-delta ADC comprising a sigma-delta integrator, an input of the sigma-delta ADC being coupled to an input voltage;
a single bit quantizer having an input coupled to the output of the sigma delta integrator;
a positive pulse counter having an input coupled to the output of the single bit quantizer, configured to count positive pulses of the output of the single bit quantizer;
a negative pulse counter having an input coupled to the output of the single bit quantizer, configured to count negative pulses of the output of the single bit quantizer; and
and a difference calculator having two input terminals coupled to the output terminals of the positive pulse counter and the negative pulse counter, respectively, the difference calculator outputting an absolute value of a difference between the count value of the positive pulse counter and the count value of the negative pulse counter, the absolute value of the difference representing an estimate of the dc offset of the input voltage.
2. The dc offset measurement circuit of claim 1, wherein the positive pulse counter comprises:
a clock;
a first analog comparator having a positive input coupled to the output of the single bit quantizer and a negative input coupled to a first reference voltage;
a first AND gate having two inputs coupled to the output of the first analog comparator and the output of the clock, respectively; and
a first counter having an input coupled to the output of the first and gate is configured to count the high signal every clock cycle.
3. The dc offset measurement circuit of claim 2, wherein the negative pulse counter comprises:
a second analog comparator having a negative input coupled to the output of the single bit quantizer and a positive input coupled to a second reference voltage;
a second AND gate having two inputs coupled to the output of the second analog comparator and the output of the clock, respectively; and
a second counter having an input coupled to the output of the second and gate is configured to count the low level signal every clock cycle.
4. The DC offset measurement circuit of claim 3, wherein,
the first reference voltage is between a low level and a high level of the single bit quantizer output;
the second reference voltage is between a low level and a high level of the single bit quantizer output.
5. The dc offset measurement circuit of claim 3, wherein the first counter includes a hit port and a reset port, the hit port issuing a hit signal when a count value of the first counter reaches a predetermined threshold; the hit port is coupled to the reset port via a delay;
the second counter includes a reset port coupled to the hit port of the first counter via a delay.
6. The dc offset measurement circuit of claim 5, wherein the difference calculator comprises a reset port coupled to the hit port of the first counter via a delay.
7. A method for measuring dc offset, comprising:
single-bit quantization is carried out on the electric signal output by the sigma-delta integrator in the sigma-delta ADC, so as to obtain a single-bit quantized signal;
respectively counting positive pulses and negative pulses generated by the single-bit quantized signals to obtain positive pulse count values and negative pulse count values; and
an absolute value of a difference between the positive pulse count value and the negative pulse count value is calculated, the absolute value of the difference representing an estimate of a dc offset of the input voltage of the sigma delta ADC.
8. A power measurement circuit, comprising:
the dc offset measurement circuit of any one of claims 1-6;
and the power calculation circuit is coupled with the direct current offset measurement circuit and calculates power according to the estimated value of the direct current offset output by the direct current offset measurement circuit.
9. A radio frequency transceiver comprising the dc offset measurement circuit of any one of claims 1-6 configured to detect a dc offset of a radio frequency transceiver receive chain.
10. The radio frequency transceiver of claim 9, further comprising:
a power measurement circuit for power measurement of the radio frequency transceiver receive link; and
and the direct current offset adjusting circuit is used for adjusting the direct current offset of the receiving link of the radio frequency transceiver according to the estimation of the direct current offset output by the direct current offset measuring circuit so as to improve the accuracy of power measurement of the power measuring circuit.
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| CN202410171921.8A CN117792840B (en) | 2024-02-07 | DC offset measurement circuit and method thereof, power measurement circuit and radio frequency transceiver |
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| CN202410171921.8A CN117792840B (en) | 2024-02-07 | DC offset measurement circuit and method thereof, power measurement circuit and radio frequency transceiver |
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| 黄志武;李艺;单勇腾;刘心昊;: "一种新型的改进型积分器定子磁链观测器", 计算机仿真, no. 05, 15 May 2007 (2007-05-15) * |
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