CN117792310A

CN117792310A - Fully differential amplifier circuit

Info

Publication number: CN117792310A
Application number: CN202311863396.8A
Authority: CN
Inventors: 陈俊龙; 杨守军; 李菁
Original assignee: Jirui Microelectronics Kunshan Co ltd
Current assignee: Jirui Microelectronics Kunshan Co ltd
Priority date: 2023-12-29
Filing date: 2023-12-29
Publication date: 2024-03-29

Abstract

The invention discloses a fully differential amplifier circuit, comprising: the circuit comprises an input stage circuit, an intermediate stage circuit, an output stage circuit, a common mode feedback circuit, a bias circuit and a current control module; the input stage circuit comprises a complementary differential input pair, wherein the complementary differential input pair is formed by connecting a first POMS differential pair and a first NMOS differential pair in parallel to form a rail-to-rail input; the intermediate stage circuit is connected with the input stage circuit and is of a folding type common-source common-gate amplifying structure; the output stage circuit is connected with the intermediate stage circuit; the common mode feedback circuit is connected with the output stage circuit and feeds back an output signal to the output stage so as to realize common mode feedback; the bias circuit provides bias voltage for the input stage circuit, the intermediate stage circuit and the common mode feedback circuit; the current control module is used for controlling the current of the intermediate stage to enable the common mode output voltage to be constant. The circuit of the invention has stable output common-mode voltage and can be suitable for low supply voltage environment.

Description

Fully differential amplifier circuit

Technical Field

The present invention relates to an operational amplifier circuit, and more particularly, to a fully differential amplifier circuit.

Background

In recent years, with the popularization of portable electronic products and the improvement of the CMOS process level, integrated circuits are continuously developed toward low power supply voltage and high integration. The fully differential operational amplifier is a basic module constituting an analog circuit such as a switched capacitor filter, a signal amplifier, and an input/output buffer, and has wide application in many fields such as analog operation, signal processing, analog-to-digital and digital-to-analog converters. For the traditional differential pair-pipe input fully differential operational amplifier circuit, the reduction of the power supply voltage of the MOSFET transistor and the reduction of the threshold voltage are in a nonlinear relation, so that the input common mode level range of the fully differential operational amplifier is greatly reduced, and the performances of the fully differential operational amplifier such as Common Mode Rejection Ratio (CMRR), power Supply Rejection Ratio (PSRR) and the like are seriously affected.

The existing scheme for realizing the fully differential amplifier mainly comprises two types:

1. the adoption of a single type of MOS transistor as a differential input pair (NMOS input pair or PMOS input pair) can limit the common mode level range of the input of the MOS transistor, and is not suitable for low-voltage use.

2. A fully differential amplifier circuit combines NMOS and PMOS input pairs to form a rail-to-rail input is disclosed in FDA design with continuous time common mode feedback for rail-to-rail constant transconductance (journal electronic measurement technique 2023-7-23, feng Xiuping). The common mode feedback adopted by the structure extracts voltage from the output stage for comparison, and the common mode feedback loop forms a three-stage amplifier, and a signal path is formed: for the three-stage amplifier loop formed by M29> M16/M5> M18/M17, the frequency response characteristic of the three-stage amplifier loop needs to be carefully considered, and frequency compensation is performed, so that the complexity of the circuit is increased, and additional compensation capacitance may need to be realized in a larger area. The circuit has a common mode feedback circuit, but when the common mode voltage is changed, the current of the gain stage is changed, the static working point of the gain stage circuit is influenced, so that the output static current and the stability of the common mode voltage are influenced, and when the common mode voltage is serious, the circuit can not work normally, particularly under the condition of low power supply voltage.

Disclosure of Invention

The invention aims to provide a fully differential amplifier circuit which is used for solving the problems that an output common-mode voltage is unstable and is not suitable for a low power supply voltage environment in the prior art. In order to achieve the above purpose, the present invention adopts the following technical scheme:

the invention discloses a fully differential amplifier circuit, comprising: the circuit comprises an input stage circuit, an intermediate stage circuit, an output stage circuit, a common mode feedback circuit, a bias circuit and a current control module.

The input stage circuit includes a complementary differential input pair connected to the Vin and Vip terminals, the complementary differential input pair being formed as a rail-to-rail input by a first POMS differential pair and a first NMOS differential pair in parallel. The intermediate stage circuit is connected with the input stage circuit, and is of a folding type common-source common-gate amplifying structure and provides high gain for the circuit. The output stage circuit is connected with the intermediate stage circuit. The common mode feedback circuit is connected with the output stage circuit, feeds back an output signal to the output stage, controls the current of the output stage circuit and realizes common mode feedback. The bias circuit provides bias voltages for the input stage circuit, the intermediate stage circuit and the common mode feedback circuit. The current control module is used for controlling the current of the intermediate stage so as to stabilize a static working point and coact with the common mode feedback circuit to enable the common mode output voltage to be constant.

Further, the input stage circuit further comprises a current mirror copying unit, an input stage current control unit and a current compensation unit; the current mirror copying unit is used for copying the reference current and providing the reference current to the complementary differential input pair; the input stage current control unit is connected to the Vin end and the Vip end and is used for controlling the compensation current; the current compensation unit is connected with the current control unit and the complementary differential input pair and is used for providing compensation current for the complementary differential input pair so as to realize constant transconductance of the input stage circuit.

Preferably, the input stage current control unit includes a second POMS differential pair and a second NMOS differential pair, and both ends of the second POMS differential pair and the second NMOS differential pair are connected to the Vin end and the Vip end.

The current compensation unit comprises a first compensation transistor group and a second compensation transistor group, wherein the first compensation transistor group provides additional compensation current for a first POMS differential pair; the second compensation transistor group provides additional compensation current to the first NMOS differential pair.

Preferably, the intermediate stage circuit comprises a folding cascode amplifying circuit and a voltage detection circuit; the folding type cascode amplifying circuit comprises transistors M33-M40; the sources of the transistors M33 and M34 are connected with the VDD terminal, and the sources of the transistors M39 and M40 are grounded; the gates of the transistors M33 and M34, the gates of the transistors M35 and M36 and the gates of the transistors M37 and M38 are connected to the bias circuit; the gates of the transistors M39, M40 are connected to the voltage detection circuit; the drains of the transistors M33, M34, M39 and M40 are all input ends of an intermediate stage, and the input ends of the intermediate stage are connected with the input stage circuit.

The transistors M35 and M36 and the transistors M37 and M38 respectively form two groups of cascode transistors and amplify signals at the input end of the intermediate electrode; the output end of the intermediate stage is arranged between the two groups of cascode transistors; and the output end of the intermediate stage is connected with the output stage circuit.

In one embodiment, the voltage detection circuit includes a resistor R3, a resistor R4, a capacitor C3, and a capacitor C4; the resistor R3 is connected with the resistor R4 in series and is connected with the output end of the intermediate stage; the capacitor C3 is connected in parallel with two ends of the resistor R3, and the capacitor C4 is connected in parallel with two ends of the resistor R4.

Further, the miller compensation circuit is connected between the output end of the intermediate stage and the output stage circuit, and miller compensation of the intermediate stage and the output stage is achieved.

In one embodiment, the miller compensation circuit includes a resistor R1 and a capacitor C1 sequentially connected to one end of a resistor R3, and a resistor R2 and a capacitor C2 sequentially connected to one end of a resistor R4; the other end of the capacitor C1 is connected to the Vop end of the output stage circuit, and the other end of the capacitor C2 is connected to the Von end of the output stage circuit.

The output stage circuit comprises load transistors M41 and M42 and output transistors M43 and M44; the gates of the load transistors M41 and M42 are connected, the sources of the load transistors M41 and M42 are connected to the VDD terminal, and the drains of the load transistors M41 and M42 are connected to the drains of the output transistors M43 and M44, respectively. The gates of the output transistors M43 and M44 are connected to the output terminal of the intermediate stage, the sources of the output transistors M43 and M44 are grounded, and the drains of the output transistors M43 and M44 are connected to the Vop terminal and the Von terminal of the output stage circuit, respectively.

Further, the current control module comprises a first current control unit and a second current control unit; one end of the first current control unit is connected with the input stage circuit, and the other end of the first current control unit is connected to the drain electrode of the transistor M39 and the drain electrode of the transistor M40 of the intermediate stage circuit; one end of the second current control unit is connected with the input stage circuit, and the other end of the second current control unit is connected to the drain electrode of the transistor M33 and the drain electrode of the transistor M34 of the intermediate stage circuit; the first current control unit and the second current control unit make the current of the transistor M39 equal to the current of the transistor M33, and the current of the transistor M40 equal to the current of the transistor M34.

In an embodiment, the first current control unit includes transistors Pa0, na1, na2, and Na3, where a source electrode of the transistor Pa0 is connected to the VDD terminal, a gate electrode of the transistor Pa0 is connected to the first compensation transistor group of the input stage circuit, and mirrors currents of the first compensation transistor group and mirrors the currents of the first compensation transistor group through Na1, na2, and Na3, and currents of the transistors Na2 and Na3 are greater than currents of Na 1; the source of the transistors Na2, na3 is grounded, the gates of the transistors Na2, na3 are connected to the drain of Pa0, the drain of the transistor Na2 is connected to the drain of M40, and the drain of the transistor Na3 is connected to the drain of M39.

The second current control unit comprises transistors Na0, pa1, pa2 and Pa3, the source electrode of the transistor Na0 is grounded, the grid electrode of the transistor Na0 is connected with a second compensation transistor group of the input stage circuit, the current of the second compensation transistor group is mirrored and mirrored through Pa1, pa2 and Pa3, and the current of the transistors Pa2 and Pa3 is larger than the current of Pa 1; the source of the transistors Pa2, pa3 is connected to the VDD terminal, the gate of the transistor Pa2, pa3 is connected to the drain of Na0, the drain of the transistor Pa2 is connected to the drain of M34, and the drain of the transistor Pa3 is connected to the drain of M33.

Preferably, the common mode feedback circuit comprises a comparison circuit, a current mirror group, a bias current source and a source negative feedback resistor; the comparison circuit is used for converting the voltages of the Vop end and the Von end of the output stage circuit into current and comparing the current with a reference voltage, and feeding back output signals to load transistors M41 and M42 of the output stage to realize common mode feedback; the current mirror group is connected to two ends of the comparison circuit; the bias current source is connected to two ends of the comparison circuit; the source negative feedback resistor is connected in parallel with two ends of the bias current source.

Wherein the voltage of the VDD terminal is less than 1.1V.

After the technical scheme is adopted, the invention has the following effects:

1. the input stage of the invention adopts a complementary differential input pair structure of the first NMOS tube and the first PMOS tube which are connected in parallel as the input tube of the signal, so that the circuit can realize rail-to-rail input, the middle stage limits the minimum power supply voltage, and the input stage is suitable for being used in a low power supply voltage environment and can be applied to a low power supply voltage circuit below 1.1V.

2. The circuit common mode feedback loop is a two-stage amplifying circuit, so that the loop is easier to stabilize and easy to compensate, and the circuit structure is simple.

3. The invention ensures the static working point of the intermediate stage by arranging the current control module, ensures stable output static current and stable output common mode level by combining the common mode feedback circuit, and does not change along with the change of the input common mode level.

4. The invention provides variable current for the complementary differential input pair through the current compensation technology, realizes that the input stage has constant transconductance characteristic when the input common mode level changes, and widens the range of the input common mode level.

Drawings

Fig. 1 is a circuit frame diagram of the present invention.

Fig. 2 is a circuit diagram of an input stage circuit according to an embodiment of the invention.

Fig. 3 is a circuit diagram of an intermediate stage circuit of the present invention.

Fig. 4 is a circuit diagram of the current control module of the present invention.

Fig. 5 is a circuit diagram of a common mode feedback circuit of the present invention.

Fig. 6 is a circuit diagram of a bias circuit of the present invention.

Fig. 7 is a circuit diagram of an input stage and a current control module according to a second embodiment of the invention.

Detailed Description

The present invention will be described in further detail with reference to the drawings and examples, in order to make the objects, technical solutions and advantages of the present invention more apparent.

Example 1

As shown in fig. 1, the present invention discloses a fully differential amplifier circuit, comprising: the circuit comprises an input stage circuit, an intermediate stage circuit, a current control module, a bias circuit, an output stage circuit and a common mode feedback circuit. The respective circuits are described in detail below.

1. Input stage circuit

As shown in fig. 2, the input stage circuit includes a complementary differential input pair, a current mirror replica unit, an input stage current control unit, and a current compensation unit.

The complementary differential input pair forms a rail-to-rail input from the first POMS differential pair M3, M4 and the first NMOS differential pair M1, M2 in parallel. The gates of M2, M3 are connected to Vin terminals, and the gates of M1, M4 are connected to Vip terminals. The drains of M1, M2, M3, M4 are connected to the intermediate stage.

The current mirror copy unit is used for copying the reference current (I _REF ) And provided to the complementary differential input pair. As shown, transistors M10, M16, M23 replicate the current of M9, and M17, M24 replicate the current of M25.

The input stage current control unit includes a second POMS differential pair M7, M8 and a second NMOS differential pair M5, M6. The gates of M6 and M8 are connected to Vin terminal, and the gates of M5 and M7 are connected to Vip terminal. The input stage current control unit forms a switch to control the compensation current.

The current compensation unit is connected with the current control unit and the complementary differential input pair and is used for providing compensation current for the complementary differential input pair so as to realize constant transconductance of the input stage circuit. The current compensation unit comprises a first compensation transistor group M11-M15 and a second compensation transistor group M18-M22, and the first compensation transistor group M11-M15 provides additional compensation current for the first POMS differential pair; the second compensation transistor group M18-M22 provides additional compensation current to the first NMOS differential pair.

The principle of realizing constant transconductance of the input stage circuit of the invention is as follows:

(1) When 0 is less than or equal to V _{in_CM} ≤V _TH +2V _dsat When V is _{in_CM} Input common mode voltage V _TH For threshold voltage, V _dsat Is an overdrive voltage. The M1 and M2 tubes enter the cut-off region, the M3 and M4 tubes are in the saturation region, and only the PMOS differential input pair works at the moment. At the same time, the current on the branch controlled by the M5 and M6 control pipes is reduced, so that the current on the current mirror formed by M11, M12 and M13 is reduced, the current on the branch controlled by the M7 and M8 control pipes is kept stable, the current comes from the tail current sources M24 and M24, and the current I from M9 is duplicated _REF . The current on the current mirror formed by M20, M21 and M22 is kept stable, the current of the M21 pipe totally flows into the M14 pipe, and because the M14 and the M15 form a 1:3 current mirror, the M15 provides 3 times of additional compensation current to the PMOS differential input pair, namely 2I is respectively obtained on the PMOS pipes M3 and M4 _REF 。

(2) When VDD- (V) _TH +2V _dsat )≤V _{in_CM} When the voltage is less than or equal to VDD, the M1 and M2 tubes are in a saturation region, the M3 and M4 tubes enter a cut-off region, and only the NMOS differential input pair works. At the same time, the current on the M5 and M6 control pipe branches keeps stably reproducing the reference current I _REF The current on the current mirror formed by M11, M12 and M13 is kept stable, the current on the branch controlled by M7 and M8 tubes is gradually reduced, the current on the current mirror formed by M20, M21 and M22 is reduced, the current of M12 tube is led to flow into M19 tube completely, and because M18 and M19 form a 3:1 current mirror, M18 provides 3 times of additional compensation current to NMOS differential input pair, namely NMOS tubes M1 and M2 are respectively divided into 2I _REF 。

(3) When V is _TH +2V _dsa t≤V _{in_CM} ≤VDD-(V _TH +2V _dsat ) When the PMOS differential input pair and the NMOS differential input pair work simultaneously, at the moment, because the control tubes of four compensation currents are simultaneously conducted, and the conducted currents of the two control branches are equal, the currents on the MOS tubes connected in parallel with the tail current source are all 0, that is to say, the current compensation circuit is in a non-working mode, and the currents flowing through each differential input PMOS tube and NMOS tube are all 0.5I _REF 。

2. Intermediate stage circuit

The intermediate stage circuit is connected with the input stage circuit, and is of a folding type common-source common-gate amplifying structure and provides high gain for the circuit.

Specifically, the intermediate stage circuit comprises a folding type common-source common-gate amplifying circuit, a voltage detection circuit and a miller compensation circuit.

As shown in fig. 3, the folded cascode circuit includes transistors M33 to M40. The sources of the transistors M33 and M34 are connected to the VDD terminal, and the sources of the transistors M39 and M40 are grounded. The gates of the transistors M33, M34, the gates of the transistors M35, M36, and the gates of the transistors M37, M38 are connected to the bias circuit (VBP 2, VBP3, BN2, connected to the bias circuit in the figure). The gates of the transistors M39, M40 are connected to a voltage detection circuit. The drains of the transistors M33, M34, M39, and M40 are input terminals of the intermediate stage (in the figure, the drain of M33 corresponds to the input terminal N11, the drain of M34 corresponds to the input terminal N12, the drain of M39 corresponds to the input terminal P11, and the drain of M40 corresponds to the input terminal P12). The input end of the intermediate stage is connected with the input stage circuit.

Transistors M35 and M36 and transistors M37 and M38 respectively form two groups of cascode transistors, and the signals at the input end of the intermediate stage are amplified, so that the gain of the intermediate stage can be greatly improved. The output end of the intermediate stage is arranged between the cascode transistors. The output end of the intermediate stage is connected with the output stage circuit.

The voltage detection circuit comprises a resistor R3, a resistor R4, a capacitor C3 and a capacitor C4. The resistor R3 is connected with the resistor R4 in series and is connected with the output end of the intermediate stage; the capacitor C3 is connected in parallel with two ends of the resistor R3, and the capacitor C4 is connected in parallel with two ends of the resistor R4.

The miller compensation circuit is connected between the output end of the intermediate stage and the output stage circuit to realize miller compensation of the intermediate stage and the output stage. The miller compensation circuit comprises a resistor R1, a capacitor C1, a resistor R2 and a capacitor C2. One end of a resistor R3 is sequentially connected with a resistor R1 and a capacitor C1, and one end of a resistor R4 is sequentially connected with a resistor R2 and a capacitor C2. The other end of the capacitor C1 is connected to the Vop end of the output stage circuit, and the other end of the capacitor C2 is connected to the Von end of the output stage circuit.

3. Output stage circuit

As shown in fig. 3, the output stage circuit includes load transistors M41, M42 and output transistors M43, M44.

The gates of the load transistors M41 and M42 are connected, the sources of the load transistors M41 and M42 are connected to the VDD terminal, and the drains of the load transistors M41 and M42 are connected to the drains of the output transistors M43 and M44, respectively. The gate voltages of the load transistors M41 and M42 are controlled by a common mode feedback circuit (VCMFB in fig. 3 is a voltage output terminal of the common mode feedback circuit), and the common mode feedback circuit outputs a common mode level signal by sampling, and the output feedback signal adjusts the gate voltages of the load transistors M41 and M42 to control the current of the output stage, so as to stably output the common mode level.

The sources of the output transistors M43 and M44 are grounded, and the drains of the output transistors M43 and M44 are respectively connected to the Vop terminal and the Von terminal of the output stage circuit. The gates of the output transistors M43 and M44 are connected to the output terminal of the intermediate stage, and the signal amplified by the intermediate stage is amplified again and finally outputted from the drain.

4. Current control module

The current control module is used for controlling the current of the intermediate stage so as to stabilize the static working point and act together with the common mode feedback circuit to enable the common mode output voltage to be constant.

As shown in fig. 4, the current control module includes a first current control unit and a second current control unit.

One end of the first current control unit is connected with the input stage circuit, and one end is connected with the drain electrode of the transistor M39 and the drain electrode of the transistor M40 of the intermediate stage circuit. Specifically, the first current control unit includes transistors Pa0, na1, na2, and Na3, where the source of the transistor Pa0 is connected to the VDD terminal, the gate of Pa0 is connected to the first compensation transistor group of the input stage circuit, and in this embodiment, is connected to the VCTRL2 port of M14, mirrors the current of M14, and mirrors the current through Na1, na2, and Na 3. The currents of the transistors Na2 and Na3 are larger than the current of Na1, and in this embodiment, the currents of Na2 and Na3 are 2 times the current of Na 1. The source of the transistors Na2, na3 is grounded, the gates of the transistors Na2, na3 are connected to the drain of Pa0, the drain of the transistor Na2 is connected to the drain of M40 (P12), and the drain of the transistor Na3 is connected to the drain of M39 (P11).

One end of the second current control unit is connected with the input stage circuit, and one end is connected with the drain electrode of the transistor M33 and the drain electrode of the transistor M34 of the intermediate stage circuit. Specifically, the second current control unit includes transistors Na0, pa1, pa2, and Pa3, the source of the transistor Na0 is grounded, the gate of the transistor Na0 is connected to the second compensation transistor group of the input stage circuit, in this embodiment, the second current control unit is connected to the VCTRL1 port of the M19, mirrors the current of the M19, and mirrors the current through Pa1, pa2, and Pa3, where the currents of the transistors Pa2 and Pa3 are greater than the current of Pa1, and in this embodiment, the currents of Pa2 and Pa3 are 2 times the current of Pa 1. The source of the transistors Pa2, pa3 is connected to the VDD terminal, the gate of the transistor Pa2, pa3 is connected to the drain of Na0, the drain of the transistor Pa2 is connected to the drain of M34 (N12), and the drain of the transistor Pa3 is connected to the drain of M33 (N11).

The first current control unit and the second current control unit make the current of the transistor M39 equal to the current of the transistor M33, and the current of the transistor M40 equal to the current of the transistor M34, so that the static working point is stabilized, and the common mode feedback circuit acts together to ensure that the final common mode output voltage is constant. The specific principle is described as follows:

(1) When the input common mode level approaches the ground rail (0.ltoreq.V) _{in_CM} ≤V _TH +2V _dsat ) When the current in N11 and N12 decreases to 0, the current in the P11 and P12 ports increases to 2I _REF . The Na0 tube of the current control module is closed, the current of the Pa2 tube and the Pa3 tube is 0, and the current obtained by copying the Na2 tube and the Na3 tube from the input stage is 2I _REF These currents pass through the intermediate stage N1 (N2) point, making the currents flowing to M39 and M40 equal to the currents of M33 and M34 (I _M39 ＝I _M33 、I _M40 ＝I _M34 )。

(2) When the input common mode level approaches the power rail (V _DD -(V _TH +2V _dsat )≤V _{in_CM} ≤V _DD ) The current in N11 and N12 will increase, eventually approaching 2I _REF The current in the P11 and P12 ports is 0. The current copied from the input stage by the current of the Pa2 pipe and the Pa3 pipe of the current control module is also 2I _REF The Pa0 tube was closed and the Na2 and Na3 tube currents were 0. These currents pass through the P1 (P2) point of the intermediate stage, causing the currents flowing to M39 and M40 to phase with the currents of M33 and M34Etc. (I) _M39 ＝I _M33 、I _M40 ＝I _M34 )。

(3) When V is _TH +2V _dsat ≤V _{in_CM} ≤V _DD -(V _TH +2V _dsat ) At the time, the current in N11 and N12 is 0.5I _REF The current in P11 and P12 is 0.5I _REF . The Na0 tube and the Pa0 tube of the current control module are in a closed state according to the control voltage of the input stage, and the current consumption is 0. M33 (M34) flows to M39 (M40) through P1 (P2) point to be I _M33 -0.5I _REF (I _M33 -0.5I _REF ) This current is summed with the current of P11 (P12) at point N1 (N2) and flows together to M39 (M40) such that the current that eventually flows through M39 (M40) is equal to the current of M33 (M34).

5. Common mode feedback circuit

The common mode feedback circuit is connected with the output stage circuit, feeds back an output signal to the output stage, and controls the current of the output stage circuit to realize common mode feedback.

As shown in fig. 5, the common mode feedback circuit includes a comparison circuit, a current mirror group, a bias current source, and a source degeneration resistor.

The comparison circuit is used for converting the voltages of the Vop end and the Von end of the output stage circuit into current and comparing the current with a reference voltage. Specifically, the comparison circuit in this embodiment includes transistors M50, M51, and M52, and gates of the transistors M50 and M51 are respectively connected to Vop and Von terminals, and form a differential input pair with M52. The gate of M52 is connected to the reference voltage Vref. The current mirror groups M45 to M48 are connected to both ends of the comparison circuit. Bias current sources M53, M54 are connected to both ends of the comparison circuit. The source negative feedback resistor R5 is connected in parallel with two ends of the bias current source. The output stage circuit of the amplifier is directly connected with the grid electrodes of M50 and M51, and the gain of the amplifier is not affected due to the high resistance characteristic. Common mode feedback is achieved by converting the voltage into current through M50 and M51 for comparison with a reference, and feeding back the output signal from the VCMFB terminal to the current mirror loads M41, M42 of the output stage.

The common mode feedback loop in the whole circuit is a two-stage amplifying circuit, and the compensation is easy to realize according to actual pipe parameters.

6. Bias circuit

The bias circuit provides bias voltages for the input stage circuit, the intermediate stage circuit and the common mode feedback circuit. Fig. 6 is a schematic diagram of a bias circuit according to the present invention, where VBP2, VBP3, BN2 interfaces of the bias circuit are respectively connected to corresponding positions of a folded cascode circuit.

Example two

The embodiment discloses a fully differential amplifier circuit, comprising: the circuit comprises an input stage circuit, an intermediate stage circuit, a current control module, a bias circuit, an output stage circuit and a common mode feedback circuit. The difference between this embodiment and the first embodiment is that: the input stage circuit and the circuit of the current control module differ from the first embodiment. The intermediate stage circuit, the bias circuit, the output stage circuit, and the common mode feedback circuit of this embodiment are the same as those of the first embodiment.

As shown in fig. 7, the input stage circuit of the present embodiment includes a complementary differential input pair, a current mirror replica unit, and an input stage current control unit.

The complementary differential input pair forms a rail-to-rail input from the first POMS differential pair M3, M4 and the first NMOS differential pair M1, M2 in parallel. The gates of M2, M3 are connected to Vin terminals, and the gates of M1, M4 are connected to Vip terminals. The drains of M1, M2, M3 and M4 are respectively connected to the N11 end, the N12 end, the P12 end and the P11 end of the intermediate stage correspondingly.

The current mirror copying units M9 to M13 are used for copying the reference current (I _REF ) And provided to the complementary differential input pair. As in the figure, M9: m10: the current ratio of M11 is: 1:1:4, M12: current ratio 1 of M13: 4.

the input stage current control unit includes a second POMS differential pair M7, M8 and a second NMOS differential pair M5, M6. The gates of M6 and M8 are connected to the Vip terminal, and the gates of M5 and M7 are connected to the Vin terminal. The input stage current control unit forms a switch to control the current to achieve a constant transconductance rail-to-rail input.

The current control module comprises transistors M14-M25, M14, M15 and M23, M24 for detecting the input common mode level, thereby controlling the current of M16 and M20. The current ratio of M16, M17 and M18 is 1:2:2, M20, M21,The current ratio of M22 is 1:2: 2. the drain ends of M17 and M18 are connected with P11/P12 of the intermediate stage, the drain ends of M21 and M22 are connected with N11 and N12 of the intermediate stage, so as to ensure that when the input common-mode voltage changes, the tube currents of the intermediate stages M39 and M40 are kept unchanged and are respectively equal to the currents of M33 and M34 (I _M39 ＝I _M33 、I _M40 ＝I _M34 )。

In the foregoing, only the preferred embodiments of the present invention are described, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be covered by the present invention.

Claims

1. A fully differential amplifier circuit, comprising: the circuit comprises an input stage circuit, an intermediate stage circuit, an output stage circuit, a common mode feedback circuit, a bias circuit and a current control module;

the input stage circuit comprises a complementary differential input pair, wherein the complementary differential input pair is connected to a Vin end and a Vip end, and the complementary differential input pair is formed by connecting a first POMS differential pair and a first NMOS differential pair in parallel to form a rail-to-rail input;

the intermediate stage circuit is connected with the input stage circuit, is of a folding type common-source common-gate amplifying structure and provides high gain for the circuit;

the output stage circuit is connected with the intermediate stage circuit;

the common mode feedback circuit is connected with the output stage circuit, feeds back an output signal to the output stage, controls the current of the output stage circuit and realizes common mode feedback;

the bias circuit provides bias voltage for the input stage circuit, the intermediate stage circuit and the common mode feedback circuit;

the current control module is used for controlling the current of the intermediate stage so as to stabilize a static working point and coact with the common mode feedback circuit to enable the common mode output voltage to be constant.

2. The fully differential amplifier circuit of claim 1, wherein: the input stage circuit also comprises a current mirror copying unit, an input stage current control unit and a current compensation unit;

the current mirror copying unit is used for copying the reference current and providing the reference current to the complementary differential input pair;

the input stage current control unit is connected to the Vin end and the Vip end and is used for controlling the compensation current;

the current compensation unit is connected with the current control unit and the complementary differential input pair and is used for providing compensation current for the complementary differential input pair so as to realize constant transconductance of the input stage circuit.

3. The fully differential amplifier circuit of claim 2, wherein: the input stage current control unit comprises a second POMS differential pair and a second NMOS differential pair, and both ends of the second POMS differential pair and the second NMOS differential pair are connected to a Vin end and a Vip end;

4. The fully differential amplifier circuit of claim 2, wherein: the intermediate stage circuit comprises a folding type cascade amplifying circuit and a voltage detection circuit;

the folding type cascode amplifying circuit comprises transistors M33-M40; the sources of the transistors M33 and M34 are connected with a VDD terminal, and the voltage of the VDD terminal is less than 1.1V; the sources of the transistors M39 and M40 are grounded; the gates of the transistors M33 and M34, the gates of the transistors M35 and M36 and the gates of the transistors M37 and M38 are connected to the bias circuit; the gates of the transistors M39, M40 are connected to the voltage detection circuit; the drains of the transistors M33, M34, M39 and M40 are all input ends of an intermediate stage, and the input ends of the intermediate stage are connected with the input stage circuit;

5. The fully differential amplifier circuit of claim 4, wherein: the voltage detection circuit comprises a resistor R3, a resistor R4, a capacitor C3 and a capacitor C4; the resistor R3 is connected with the resistor R4 in series and is connected with the output end of the intermediate stage; the capacitor C3 is connected in parallel with two ends of the resistor R3, and the capacitor C4 is connected in parallel with two ends of the resistor R4.

6. The fully differential amplifier circuit of claim 5, wherein: the miller compensation circuit is connected between the output end of the intermediate stage and the output stage circuit to realize miller compensation of the intermediate stage and the output stage;

the miller compensation circuit comprises a resistor R1 and a capacitor C1 which are sequentially connected with one end of a resistor R3, and a resistor R2 and a capacitor C2 which are sequentially connected with one end of a resistor R4; the other end of the capacitor C1 is connected to the Vop end of the output stage circuit, and the other end of the capacitor C2 is connected to the Von end of the output stage circuit.

7. The fully differential amplifier circuit of claim 4, wherein: the output stage circuit comprises load transistors M41 and M42 and output transistors M43 and M44;

the gates of the load transistors M41 and M42 are connected, the sources of the load transistors M41 and M42 are connected to the VDD terminal, and the drains of the load transistors M41 and M42 are connected to the drains of the output transistors M43 and M44 respectively;

the gates of the output transistors M43 and M44 are connected to the output terminal of the intermediate stage, the sources of the output transistors M43 and M44 are grounded, and the drains of the output transistors M43 and M44 are connected to the Vop terminal and the Von terminal of the output stage circuit, respectively.

8. The fully differential amplifier circuit of claim 4, wherein: the current control module comprises a first current control unit and a second current control unit;

one end of the first current control unit is connected with the input stage circuit, and the other end of the first current control unit is connected to the drain electrode of the transistor M39 and the drain electrode of the transistor M40 of the intermediate stage circuit;

one end of the second current control unit is connected with the input stage circuit, and the other end of the second current control unit is connected to the drain electrode of the transistor M33 and the drain electrode of the transistor M34 of the intermediate stage circuit;

the first current control unit and the second current control unit make the current of the transistor M39 equal to the current of the transistor M33, and the current of the transistor M40 equal to the current of the transistor M34.

9. The fully differential amplifier circuit of claim 8, wherein: the first current control unit comprises transistors Pa0, na1, na2 and Na3, wherein the source electrode of the transistor Pa0 is connected to the VDD end, the grid electrode of the transistor Pa0 is connected with a first compensation transistor group of the input stage circuit, the currents of the first compensation transistor group are mirrored and mirrored through Na1, na2 and Na3, and the currents of the transistors Na2 and Na3 are larger than the currents of Na 1; the source of the transistors Na2 and Na3 is grounded, the gates of the transistors Na2 and Na3 are connected to the drain of Pa0, the drain of the transistor Na2 is connected to the drain of M40, and the drain of the transistor Na3 is connected to the drain of M39;

10. The fully differential amplifier circuit of claim 7, wherein: the common mode feedback circuit comprises a comparison circuit, a current mirror group, a bias current source and a source negative feedback resistor;

the comparison circuit is used for converting the voltages of the Vop end and the Von end of the output stage circuit into current and comparing the current with a reference voltage, and feeding back output signals to load transistors M41 and M42 of the output stage to realize common mode feedback;

the current mirror group is connected to two ends of the comparison circuit;

the bias current source is connected to two ends of the comparison circuit;

the source negative feedback resistor is connected in parallel with two ends of the bias current source.