CN117790453A

CN117790453A - Power lead frame package with reduced solder void

Info

Publication number: CN117790453A
Application number: CN202311293747.6A
Authority: CN
Inventors: J·S·塔列多
Original assignee: STMicroelectronics lnc USA
Current assignee: STMicroelectronics lnc USA
Priority date: 2022-09-29
Filing date: 2023-10-08
Publication date: 2024-03-29

Abstract

The present disclosure relates to a power lead frame package that reduces solder voids. An electronic device includes an Integrated Circuit (IC) with a second face bonded to a first surface of a first support. The first portion of the conductive clip is elongated and extends across the IC with the second surface thereof bonded to the first face of the IC by a solder layer. The second portion of the clip extends from the first portion away from the IC toward the second support with the second surface thereof being joined to the first surface of the second support. The first surface of the clip has a pattern formed therein that includes a recessed floor having fins extending upwardly therefrom. The through hole extends through the recessed floor to the second surface of the clip. The encapsulation layer covers portions of the first and second supports, the IC, and the clip while exposing a first surface of the first portion to allow heat to radiate away therefrom.

Description

Power lead frame package with reduced solder void

RELATED APPLICATIONS

The present application claims priority from U.S. provisional patent application No.63/411,306, filed on 9/29 of 2022, the contents of which are incorporated by reference in their entirety.

Technical Field

The present disclosure relates to the field of electronic devices, and more particularly, to the design of clip interconnects (clip interconnect) that facilitate assembly without forming solder voids (solder void) between such clip interconnects and an Integrated Circuit (IC) die during solder reflow.

Background

In many conventional applications, an Integrated Circuit (IC) die of an electronic device is interconnected with other components of the electronic device using wire bond (wirebond). However, in certain high current applications, the use of wire bonds may be impractical due to the number of wire bonds required to carry the intended current load, which in turn increases the complexity in the equipment assembly. Thus, in such high current applications, clip interconnects may be used to provide interconnections between the integrated circuit die and other components due to the high current carrying capability of the clip interconnects.

A cross-section of a known electronic device 1 using clip interconnections is shown in fig. 1. The bottom surface of the IC die 5 is bonded to the top surface of a die pad (pad) 3 of a lead frame (leadframe) by a die attach layer 4 (e.g., a solder layer), and the top surface of the IC die 5 is bonded to the bottom surface of a first portion 7a of the clip 7 by a solder layer 6. The clip 7 has a second portion 7b extending from the first portion 7a at an angle, and a bottom surface of the second portion 7b of the clip 7 is bonded to a top surface of one or more leads 9 of the lead frame by a solder layer 8.

During device assembly, the bottom surface of the IC die 5 is attached to the top surface of the die pad 3 using solder material, the top surface of the IC die 5 is attached to the bottom surface of the first portion 7a of the clip 7, and the top surface of the wire 9 is attached to the bottom surface of the cross-section portion 7b of the clip 7, after which the electronic device 1 assembly is subjected to controlled heating to form the solder layers 4, 6, and 8. However, the solder material contains volatile components (e.g., flux) that release bubbles during solidification. If these bubbles are trapped between the surfaces being joined via the solder reflow process, voids are thereby formed within the solder layer, and in particular within the solder layer 6. In fig. 2, a cross-sectional view of the solder layer 6 is shown, including a cavity 6a formed therein. Such solder voids increase thermal resistance between layers, reduce heat dissipation, and create localized hot spots. Such solder voids also reduce electrical conductivity between layers, which may reduce device performance.

To ensure that such bubbles are not trapped between the surfaces being bonded, the reflow process may be carefully optimized. However, this optimization is a trial and error process (trial and error process) and becomes more difficult to perform as the IC die 5 and clip 7 size increases. Thus, there is a need for further development of assembly techniques and clip designs.

Disclosure of Invention

An electronic device is disclosed herein that includes a first support substrate and a second support substrate spaced apart from the first support substrate. An Integrated Circuit (IC) die has opposing first and second faces, the second face being bonded to the first surface of the first support substrate. The conductive clip is formed from a first portion and a second portion, each having opposing first and second surfaces, the first portion of the conductive clip being elongated and extending across the IC die, the second surface of the first portion of the conductive clip being bonded to the first face of the IC die by a solder layer, the second portion of the conductive clip extending from the first portion away from the IC die toward the second support substrate such that the second surface thereof is bonded to the first surface of the second support substrate.

The first surface of the conductive clip has a pattern formed therein that includes a recessed floor having fins (fins) extending upwardly therefrom. The through holes extend from the recessed floor of the pattern through the first surface of the conductive clip to the second surface of the conductive clip. The encapsulation layer covers the first support substrate, the second support substrate, the IC die, and portions of the conductive clip while exposing a first surface of the first portion of the conductive clip to allow heat to radiate away therefrom.

The through holes may be straight-cut (straight-cut) of the same size and shape at the recessed floor of the pattern and at the second surface of the conductive clip.

The through-holes may be enlarged in size from the recessed floor of the pattern up to the second surface of the conductive clip such that the size of the through-holes at the recessed floor is smaller than the size of the through-holes at the second surface of the conductive clip.

The through-holes may be scaled down in size from the recessed floor of the pattern up to the second surface of the conductive clip such that the size of the through-holes at the recessed floor is greater than the size of the through-holes at the second surface of the conductive clip.

The through-hole may have a cross-section that is circular in shape, or may have a pill-shaped cross-section.

The fins may extend upwardly from the recessed floor to a level at a highest point of the first surface of the first portion of the conductive clip.

The second surface of the first portion of the conductive clip may be planar.

The first support substrate may be a die pad of a leadframe and the second support substrate may be at least one lead of the leadframe.

Drawings

Fig. 1 is a schematic cross-sectional view of a prior art electronic device utilizing conductive clip interconnects.

Fig. 2 is a diagram of solder voids formed in the solder layer joining the bottom surface of the conductive clip to the top surface of the integrated circuit in fig. 1.

Fig. 3 is a schematic cross-sectional view of an electronic device disclosed herein utilizing conductive clip interconnects.

Fig. 4 is a perspective view of a first embodiment of the conductive clip of fig. 3.

Fig. 5 is a perspective view of a second embodiment of the conductive clip of fig. 3.

Fig. 6 is a perspective view of a third embodiment of the conductive clip of fig. 3.

Fig. 7 is a perspective view of a fourth embodiment of the conductive clip of fig. 3.

Detailed Description

The following disclosure enables one skilled in the art to make and use the subject matter disclosed herein. The general principles described herein may be applied to embodiments and applications other than those detailed above without departing from the spirit and scope of the disclosure. The present disclosure is not intended to be limited to the embodiments shown, but is to be accorded the widest scope consistent with the principles and features disclosed or suggested herein.

Referring now to fig. 3-4, an electronic device 10 is described that includes a die pad 11 (e.g., a portion of a leadframe) and a lead 14 (e.g., a portion of a leadframe) spaced apart from one another and having a conductive clip 20 (formed of, for example, copper) that forms an interconnect therebetween. As will be explained below, the conductive clip 20 is specifically designed to mitigate the concern of forming solder voids during solder reflow.

In more detail, the top surface of the die pad 11 is bonded to the bottom surface of the IC13 by a die attach layer 12 (e.g., a solder layer such as soft solder/Ag sintering). The conductive clip 20 includes a first portion 21 and a second portion 22, the first portion 21 having a planar bottom surface bonded to the top surface of the IC13 by a die attach layer (e.g., solder layer 16 such as soft solder/Ag sintering), the second portion extending laterally away from the IC13 from the first portion 21 such that the planar bottom surface of the second portion 22 is bonded to the top surface of the leads 14 by a die attach layer 15 (e.g., solder layer such as soft solder/Ag sintering). The second portion 22 of the conductive clip 20 is observed to have a stepped shape defining a height decrease from the top surface of the IC13 to the top surface of the leads 14. It is also observed that the first portion 21 of the conductive clip 21 is elongated and extends across the IC 13.

The encapsulation layer 24 extends from the top surfaces of the die pad 11 and the leads 14 to be flush with the top surface of the first portion 21 of the conductive clip 20, environmentally sealing the sides and bottom surfaces of the first portion 21, thereby environmentally sealing the IC13, and environmentally sealing the covered portion of the top surface of the die pad 11 while leaving the top surface of the first portion 21 exposed. The encapsulation layer 24 also environmentally encapsulates the second portion 22 and the covered portion of the top surface of the leads 14. Note that the encapsulation layer 24 also environmentally encapsulates the gap between the die pad 11 and the leads 14.

As described above, during the solder reflow process, it is desirable to prevent as much as possible the formation of solder voids in the solder 16, thereby providing more efficient heat transfer from the IC13 to the conductive clip 20. To facilitate this, the first portion 21 of the conductive clip 20 has a through hole 23 defined therein. The shape and location of these vias 23 are adjusted so that gases released from volatile components during solder reflow can escape the solder layer 16 through the vias 23, thereby eliminating solder voids formed by these gases and enhancing the cooling capacity of the electronic device 10, as well as potentially enhancing improved device performance by increasing electrical conductivity between the IC13, the conductive clip 20, and the leads 14.

The exposure of the top surface of the first portion 21 of the conductive clip 20 by the encapsulation layer 24 helps to provide the ability for heat in the clip 20 to radiate and dissipate away from the clip 20. To enhance this effect, the top surface of the first portion 21 of the conductive clip 20 has an exposed surface area increased by the pattern 25 defined above. The pattern 25 includes a recessed floor 25a defined by a plurality of interconnected recesses or channels formed in the top surface of the first portion 21 extending into the conductive clip 20, with protrusions or fins 25b (defined by the recesses or channels) extending upwardly from the recessed floor 25 a. The fins 25b may extend all the way to a level that is aligned with the highest point of the other portion of the top surface of the first portion 21 of the conductive clip 20, may extend to a level that is above the other highest point of the other portion of the top surface of the first portion 21 of the conductive clip 20, or may extend to a level that is below the highest point of the other portion of the top surface of the first portion 21 of the conductive clip 20. By increasing the surface area of the top surface of the first portion 21 of the conductive clip 20, heat can be more easily radiated outward.

In the illustrative example of fig. 4, the through hole 23 is circular and uniform in diameter from the top surface of the first portion 21 of the conductive clip 20 to the bottom surface of the first portion 21 of the conductive clip 20 (e.g., formed by a straight cut). However, the through holes 23 may take other suitable shapes. For example, the shape of the through hole 23' may be elliptical or may be a pill shape as shown in fig. 5. The through hole 23 "may taper in the cutout, being wider at the top surface of the first portion 21 of the conductive clip 20 than at the bottom surface of the first portion 21 of the conductive clip 20, as shown in fig. 6. The through hole 23' "may alternatively taper in the opposite manner in the cutout, being narrower at the top surface of the first portion 21 of the conductive clip 20 than at the bottom surface of the first portion 21 of the conductive clip 20, as shown in fig. 7.

The pitch and pattern of the vias 23 may be adjusted depending on the surface area of the top surface of the IC13 and the surface area of the top surface of the first portion 21 of the conductive clip 20, on the intended operating conditions of the IC13, and/or on the specific composition of the solder layer 16.

A method for manufacturing the electronic device 10 will now be described. The method includes providing a substrate or leadframe carrying a die pad 11, and bonding a bottom surface of an IC13 to a top surface of the die pad 11 by a solder layer 12. The bottom surface of the first portion 21 of the conductive clip 20 is then bonded to the top surface of the IC13 by the solder layer 16, and in this step the bottom surface of the second portion 21 of the conductive clip 21 is bonded to the top surface of the wire 14 by the solder layer 15. Thereafter, solder reflow is performed and the electronic device 10 is allowed to cool before the encapsulation layer 24 is deposited.

It will be apparent that modifications and variations may be made to what has been described and illustrated herein without departing from the scope of the disclosure as defined in the appended claims.

While the disclosure has been described with respect to a limited number of embodiments, those skilled in the art, having benefit of this disclosure, will appreciate that other embodiments can be devised which do not depart from the scope of the disclosure as disclosed herein. Accordingly, the scope of the present disclosure should be limited only by the attached claims.

Claims

1. An electronic device, comprising:

a first support substrate;

a second support substrate spaced apart from the first support substrate;

an integrated circuit IC die having opposed first and second faces, the second face being bonded to the first surface of the first support substrate;

a conductive clip formed from a first portion and a second portion, each having opposing first and second surfaces, the first portion of the conductive clip being elongate and extending across the IC die, the second surface of the first portion of the conductive clip being bonded to the first face of the IC die by a solder layer, the second portion of the conductive clip extending from the first portion away from the IC die toward the second support substrate such that the second surface thereof is bonded to the first surface of the second support substrate;

wherein the first surface of the conductive clip has a pattern formed therein, the pattern comprising a recessed floor having fins extending upwardly therefrom;

wherein a through hole extends from the recessed floor of the pattern through the first surface of the conductive clip to the second surface of the conductive clip; and

an encapsulation layer covering the first support substrate, the second support substrate, the IC die, and portions of the conductive clip while exposing a first surface of the first portion of the conductive clip to allow heat to radiate away therefrom.

2. The electronic device of claim 1, wherein the through-hole is cut straight, the same size and shape at the recessed floor of the pattern and at the second surface of the conductive clip.

3. The electronic device of claim 1, wherein the through-hole expands in size from the recessed floor of the pattern to the second surface of the conductive clip such that a size of the through-hole at the recessed floor is smaller than a size of the through-hole at the second surface of the conductive clip.

4. The electronic device of claim 1, wherein the through-hole is reduced in size from the recessed floor of the pattern to the second surface of the conductive clip such that the through-hole has a larger size at the recessed floor than at the second surface of the conductive clip.

5. The electronic device of claim 1, wherein the through hole has a cross-section that is circular in shape.

6. The electronic device of claim 1, wherein the through-hole has a pill-shaped cross-section.

7. The electronic device defined in claim 1 wherein the fins extend upwardly from the recessed floor to a level at the highest point of the first surface of the first portion of the conductive clip.

8. The electronic device of claim 1, wherein the second surface of the first portion of the conductive clip is planar.

9. The electronic device of claim 1, wherein the first support substrate is a die pad of a leadframe.

10. The electronic device of claim 1, wherein the second support substrate is at least one lead of a lead frame.

11. A method of manufacturing an electronic device, comprising:

forming a conductive clip from a first portion and a second portion, each having opposing first and second surfaces, such that the first portion of the conductive clip is elongated and such that the second portion of the conductive clip extends outwardly away from the first portion of the conductive clip in an out-of-plane direction;

forming a pattern in a first surface of a first portion of the conductive clip such that the pattern includes a recessed floor having fins extending upwardly therefrom;

forming a through hole in a recessed floor of a first portion of the conductive clip;

coupling a second face of the integrated circuit IC to the first surface of the first support substrate;

bonding the second surface of the first portion of the conductive clip to the first face of the IC by a solder layer formed between the second surface of the first portion of the conductive clip and the first face of the IC;

coupling a second surface of a second portion of the conductive clip to a first surface of a second support substrate spaced apart from the IC;

heating the electronic device to reflow the solder layer, gas released from the solder layer during reflow escaping the electronic device through the through-holes;

allowing the electronic device to cool; and

an encapsulation layer is formed over the electronic device such that a first surface of the conductive clip is exposed.

12. The method of claim 11, further comprising: coupling the second surface of the first support substrate to the first surface of the base substrate prior to coupling the second face of the integrated circuit IC to the first surface of the first support substrate; and further comprising: after the encapsulation layer is formed, the base substrate is removed from the first support substrate.

13. The method of claim 11, wherein the through holes are formed to be the same size and shape at the recessed floor of the pattern and at the second surface of the conductive clip, which are cut straight.

14. The method of claim 11, wherein the via is formed to expand in size from the recessed floor of the pattern up to the second surface of the conductive clip such that the via has a smaller size at the recessed floor than at the second surface of the conductive clip.

15. The method of claim 11, wherein the via is formed to decrease in size from the recessed floor of the pattern to the second surface of the conductive clip such that the via has a larger size at the recessed floor than at the second surface of the conductive clip.

16. The method of claim 11, wherein the through hole is formed to have a cross section having a circular shape.

17. The method of claim 11, wherein the through-hole is formed to have a pill-shaped cross-section.

18. The method of claim 11, wherein the first support substrate is a die pad of a leadframe.

19. The method of claim 11, wherein the second support substrate is at least one lead of a lead frame.