CN117789806A - Flash memory testing device - Google Patents
Flash memory testing device Download PDFInfo
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- CN117789806A CN117789806A CN202211372361.XA CN202211372361A CN117789806A CN 117789806 A CN117789806 A CN 117789806A CN 202211372361 A CN202211372361 A CN 202211372361A CN 117789806 A CN117789806 A CN 117789806A
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- 238000012360 testing method Methods 0.000 title claims abstract description 93
- 230000015654 memory Effects 0.000 title claims abstract description 79
- 238000001514 detection method Methods 0.000 claims abstract description 47
- 238000010438 heat treatment Methods 0.000 claims abstract description 23
- 230000000087 stabilizing effect Effects 0.000 claims description 33
- 239000003990 capacitor Substances 0.000 claims description 12
- 238000006243 chemical reaction Methods 0.000 claims description 8
- 238000010586 diagram Methods 0.000 description 4
- 239000002184 metal Substances 0.000 description 4
- 230000009194 climbing Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 150000003071 polychlorinated biphenyls Chemical class 0.000 description 1
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Abstract
The invention provides a flash memory testing device. The first power management circuit and the second power management circuit are controlled by the control circuit to provide a first test power voltage and a second test power voltage for the flash memory. The heating control circuit is controlled by the control circuit to control the heater to heat the flash memory. The current detection circuit is controlled by the control circuit to detect the current flowing through the first power management circuit and the second power management circuit.
Description
Technical Field
The present disclosure relates to testing devices, and particularly to a flash memory testing device.
Background
In many electronic devices, electronic components are mounted on printed circuit boards (printed circuit board, PCBs). For example, various electronic components such as controllers, flash memories, buffer memories, input/output (I/O) ports, electrolytic capacitors, and the like may be mounted on the PCB.
In the USB device, because the conditions such as the number of layers, the area size, the power supply mode, the voltage size, and the voltage climbing speed of the printed circuit board are different, it is necessary to perform various tests on the flash memory by using the test fixture, so as to rank the flash memory according to the performance of the flash memory. Therefore, how to test the flash memory more accurately and more efficiently is an important issue.
Disclosure of Invention
The invention provides a flash memory grading (BIN) testing device which can accurately and effectively test a flash memory.
The invention relates to a flash memory testing device, which is used for testing a flash memory and comprises a control circuit, a first power management circuit, a second power management circuit, a heater, a heating control circuit and a current detection circuit. The first power management circuit is coupled to the control circuit and is controlled by the control circuit to provide a first test power voltage to the flash memory. The second power management circuit is coupled to the control circuit and is controlled by the control circuit to provide a second test power voltage to the flash memory. The heater is used for heating the flash memory and sensing the temperature of the flash memory. The heating control circuit is coupled with the control circuit and the heater and is controlled by the control circuit to control the heater to heat the flash memory. The current detection circuit is coupled with the power management circuit and the control circuit and is controlled by the control circuit to detect the current flowing through the power management circuit.
In an embodiment of the invention, the first power management circuit and the second power management circuit respectively include a voltage stabilizing circuit, a current detecting resistor, a feedback circuit and a variable capacitance circuit. The current detection resistor is coupled between the output end of the voltage stabilizing circuit and the output end of the power management circuit, and the voltage stabilizing circuit provides a first test power supply voltage or a second test power supply voltage through the current detection resistor. The feedback circuit is coupled to the output end of the voltage stabilizing circuit, the feedback end and the control circuit, and the control circuit adjusts the resistance value of the feedback circuit to adjust the first test power supply voltage or the second test power supply voltage. The variable capacitance circuit is coupled to the output end of the power management circuit and the control circuit, and the control circuit adjusts the capacitance value of the variable capacitance circuit to adjust the boosting speed of the first test power supply voltage or the second test power supply voltage.
In an embodiment of the present invention, the first test power voltage is a core voltage, and the second test power voltage is an input/output voltage.
In an embodiment of the invention, the core voltage is used for supplying power to a core circuit of the flash memory, and the input/output voltage is used for supplying power to an input/output circuit of the flash memory.
In an embodiment of the invention, the control circuit controls the first power management circuit and the second power management circuit to adjust start-up time of the first test power voltage and the second test power voltage.
In an embodiment of the invention, the current detection circuit includes a current-to-voltage circuit, a first switching circuit, and a second switching circuit. The first switching circuit is coupled to one end of the current detection resistor of the first power management circuit and one end of the current detection resistor of the second power management circuit, the control circuit and the current-to-voltage circuit, and is controlled by the control circuit to connect the current-to-voltage circuit to the current detection resistor of the first power management circuit or the current detection resistor of the second power management circuit. The second switching circuit is coupled to the other ends of the current detection resistors of the first power management circuit and the second power management circuit, the control circuit and the current-to-voltage circuit, and is controlled by the control circuit to switch and connect the current-to-voltage circuit to the current detection resistor connected with the first switching circuit, and the current-to-voltage circuit converts a current signal flowing through the current detection resistor connected with the current-to-voltage circuit into a voltage signal.
In an embodiment of the invention, the current-to-voltage circuit includes an operational amplifier, and positive and negative input terminals of the operational amplifier are respectively coupled to the first switching circuit and the second switching circuit, and generate a voltage signal according to voltages at two ends of the current detection resistor connected to the current-to-voltage circuit.
In an embodiment of the invention, the current-to-voltage circuit further includes an analog-to-digital conversion circuit coupled to an output terminal of the operational amplifier for converting the voltage signal into a digital signal.
In an embodiment of the invention, the feedback resistor circuit includes a first resistor, a second resistor, a plurality of switches, and a plurality of third resistors. The second resistor and the first resistor are coupled between the output end of the voltage stabilizing circuit and the ground, and a common joint of the first resistor and the second resistor is coupled with the feedback end of the voltage stabilizing circuit. The switches are coupled with the control circuit, and the conducting states of the switches are controlled by the control circuit. The third resistors and the corresponding switches are connected in series between the feedback end of the voltage stabilizing circuit and the ground.
In an embodiment of the invention, the capacitor circuit includes a first capacitor, a plurality of switches, and a plurality of second capacitors. The first capacitor is coupled between the output end of the power management circuit and the ground. The switches are coupled with the control circuit, and the conducting states of the switches are controlled by the control circuit. The second capacitors and the corresponding switches are connected in series between the output end of the power management circuit and the ground.
Based on the above, the flash memory testing device according to the embodiment of the invention can control the first power management circuit, the second power management circuit, the heater and the current detection circuit to adjust the testing parameters of the flash memory and detect the corresponding testing results.
In order to make the above features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Drawings
FIG. 1 is a schematic diagram of a flash memory testing device according to an embodiment of the invention;
FIG. 2 is a flow chart of a testing method of a flash memory testing device according to another embodiment of the invention;
FIG. 3 is a schematic diagram of a power management circuit according to an embodiment of the invention;
FIGS. 4A and 4B are waveforms of test voltages provided by the power management circuit according to an embodiment of the invention;
fig. 5 is a schematic diagram of a current detection circuit according to an embodiment of the invention.
Detailed Description
In order that the invention may be more readily understood, the following examples are provided as illustrations of the true practice of the invention. In addition, wherever possible, the same reference numbers will be used throughout the drawings and the description to refer to the same or like parts.
Fig. 1 is a schematic diagram of a flash memory testing device according to an embodiment of the invention, please refer to fig. 1. The flash memory test apparatus may include a control circuit 102, a first power management circuit 104, a current detection circuit 106, a second power management circuit 108, a heating control circuit 110 and a heater 112, wherein the control circuit 102 is coupled to the first power management circuit 104, the current detection circuit 106, the second power management circuit 108 and the heating control circuit 110, the current detection circuit 106 is coupled to the first power management circuit 104 and the second power management circuit 108, the control circuit 102, the first power management circuit 104 and the second power management circuit 108 may be coupled to the flash memory 114 to be tested, and the heating control circuit 110 is coupled to the heater 112. The control circuit 102 may be connected to a host (not shown) via a Universal Serial Bus (USB) interface to communicate with the host, and control the first power management circuit 104, the current detection circuit 106, the second power management circuit 108, the heating control circuit 110, etc. according to instructions of the host, and may transmit instruction signals and data signals with the flash memory. The control circuit 102 may be, for example, a USB flash drive controller, but not limited thereto.
Further, as shown in fig. 2, the host connected to the flash memory test device can confirm the grading condition of the flash memory (step S202), such as the test parameters and test results of the flash memory. Then, various test parameters (such as test voltage and test temperature, but not limited to) for grading are generated according to the grading condition of the flash memory (step S204), and then the test parameters are loaded into the flash memory testing device (step S206), for example, into the control circuit 102. The control circuit 102 may control the first power management circuit 104, the current detection circuit 106, the second power management circuit 108 and the heating control circuit 110 to perform the test of the flash memory 114 according to the test parameters (step S208). For example, the control circuit 102 may control the first power management circuit 104 and the second power management circuit 108 to provide the first test power voltage and the second test power voltage to the flash memory 114, respectively (step S210), and control the current detection circuit 106 to detect the current flowing through the first power management circuit 104 and the second power management circuit 108 (step S212), and control the heating control circuit 110 to control the heater 112 to heat the flash memory 114, and sense the temperature of the flash memory 114 (step S214). Finally, the flash memory 114 may be ranked according to the test result (step S216).
The test result may be, for example, the magnitude of the current detected by the current detection circuit 106 under the specified conditions of the first test power voltage, the second test power voltage, and the temperature of the flash memory 114. The current detected by the current detection circuit 106 may include, for example, a standby current flowing through the first power management circuit 104 and the second power management circuit 108 detected when the flash memory 114 is in standby state of the flash memory test device, or an operation current flowing through the first power management circuit 104 and the second power management circuit 108 detected when the flash memory test device performs an access operation to the flash memory 114, but is not limited thereto.
In addition, the heater 112 may include a heating metal plate and a temperature sensor, wherein the heating metal plate may be disposed above or below the flash memory 114 for heating, for example, to reduce the error of the heating temperature. In some embodiments, the flash memory 114 may also be placed in the heating box together with the heating metal plate and the temperature sensor to control the temperature of the flash memory 114 more stably, wherein the volume of the heating box is reduced, the energy required for heating is reduced, and the time for heating to the target temperature is reduced. When the heating control circuit 110 controls the heater 112 to heat according to the instruction of the control circuit 102, the control circuit 102 can adjust the power of the heater 112 according to the temperature of the flash memory 114 or the heating metal plate sensed by the temperature sensor, so as to ensure that the heater 112 can maintain the flash memory 114 at a specified temperature.
In detail, an embodiment of the first power management circuit 104 and the second power management circuit 108 can be shown in fig. 3, wherein the first power management circuit 104 includes a voltage stabilizing circuit 302, a current detecting resistor RT1, a feedback circuit 306, and a variable capacitance circuit 308, and the second power management circuit 108 includes a voltage stabilizing circuit 310, a current detecting resistor RT2, a feedback circuit 314, and a variable capacitance circuit 316. In the first power management circuit 104, the feedback circuit 306 is coupled between the output terminal and the feedback terminal of the voltage stabilizing circuit 302, the current detection resistor RT1 is coupled between the output terminal of the voltage stabilizing circuit 302 and the output terminal of the first power management circuit 104, and the variable capacitance circuit 308 is coupled between the output terminal of the voltage stabilizing circuit 302 and the control circuit 102. The voltage stabilizing circuit 302 may provide the first test power voltage through the current detecting resistor RT1, and the voltage stabilizing circuit 302 may be, for example, a low dropout linear regulator (LDO), but not limited thereto. The control circuit 102 can adjust the resistance value of the feedback circuit 306 and the capacitance value of the variable capacitance circuit 308 to change the voltage level and the boosting rate of the first test power voltage provided by the voltage stabilizing circuit 302, thereby changing the test condition of the flash memory 114.
Similarly, in the second power management circuit 108, the feedback circuit 314 is coupled between the output terminal of the voltage stabilizing circuit 310 and the feedback terminal, the current detection resistor RT2 is coupled between the output terminal of the voltage stabilizing circuit 310 and the output terminal of the second power management circuit 108, and the variable capacitance circuit 316 is coupled between the output terminal of the voltage stabilizing circuit 310 and the control circuit 102. The voltage stabilizing circuit 310 may provide the second test power voltage through the current detecting resistor RT2, and the voltage stabilizing circuit 310 may be, for example, a low dropout linear regulator, but not limited thereto. The control circuit 102 can adjust the resistance of the feedback circuit 314 and the capacitance of the variable capacitance circuit 316 to change the voltage level and the boosting rate of the second test power voltage provided by the voltage stabilizing circuit 310, thereby changing the test condition of the flash memory 114. The first test power voltage may be, for example, a core voltage VCC, and the second test power voltage may be, for example, an input/output voltage VCCQ, but not limited thereto, the core voltage VCC is used for supplying power to the core circuit of the flash memory 114, and the input/output voltage VCCQ is used for supplying power to the input/output circuit of the flash memory 114. The core voltage VCC may be, for example, 3.3V, and the input/output voltage VCCQ may be, for example, 1.8V, but not limited thereto.
Further, the feedback circuit 306 may include resistors R1 to R5 and transistors M1 to M3, wherein the resistor R1 and the resistor R2 are connected in series between the output terminal of the voltage stabilizing circuit 302 and the ground, the common junction of the resistor R1 and the resistor R2 is coupled to the feedback terminal of the voltage stabilizing circuit 302, the transistors M1 to M3 and the corresponding resistors R3 to R5 are connected in series between the feedback terminal of the voltage stabilizing circuit 302 and the ground, and the control terminal of the transistors M1 to M3 is coupled to the control circuit 102. The control circuit 102 can adjust the resistance value of the feedback circuit 306 by controlling the on states of the transistors M1 to M3, so as to change the voltage level of the first test power voltage provided by the voltage stabilizing circuit 302.
In addition, the variable capacitance circuit 308 includes, for example, capacitors C1-C4 and transistors M4-M6, the capacitor C4 is coupled between the output terminal of the first power management circuit 104 and the ground, the transistors M4-M6 are respectively connected in series with the corresponding capacitors C1-C3 between the output terminal of the first power management circuit 104 and the ground, and the control terminals of the transistors M4-M6 are coupled to the control circuit 102. The control circuit 102 can adjust the capacitance value of the variable capacitance circuit 308 by controlling the on states of the transistors M4 to M6, thereby changing the boosting rate of the first test power voltage provided by the first power management circuit 104.
In addition, the feedback circuit 314 and the variable capacitance circuit 316 of the second power management circuit 108 can be implemented in a similar manner, wherein the feedback circuit 314 can include resistors R6-R10 and transistors M7-M9, and the variable capacitance circuit 308 can include capacitors C5-C8 and transistors M10-M12, for example. Since the embodiments of the feedback circuit 314 and the variable capacitance circuit 316 are similar to the feedback circuit 306 and the variable capacitance circuit 308, the coupling methods thereof are not described herein.
The control circuit 102 can adjust the resistance value of the feedback circuit 314 by controlling the on states of the transistors M7 to M9, thereby changing the voltage level of the second test power voltage provided by the voltage stabilizing circuit 310, and adjust the capacitance value of the variable capacitance circuit 316 by controlling the on states of the transistors M10 to M12, thereby changing the boosting rate of the second test power voltage provided by the second power management circuit 108.
In some embodiments, the start-up times of the core voltage VCC and the input/output voltage VCCQ may be different depending on the design of the flash memory 114, and the control circuit 102 may control the start-up times of the core voltage VCC and the input/output voltage VCCQ by controlling the on states of the transistors M1 to M3 and M8 to M10 to test the flash memory 114 according to the design of the flash memory 114. For example, as shown in fig. 4A, the control circuit 102 may lead the transistors M1 to M3 to enable the first power management circuit 104 to provide the core voltage VCC, and after the time T1, the transistors M7 to M9 are turned on to enable the second power management circuit 108 to provide the input/output voltage VCCQ. Alternatively, as shown in fig. 4B, the control circuit 102 turns on the transistors M7 to M9 to cause the second power management circuit 108 to provide the input/output voltage VCCQ, and turns on the transistors M1 to M3 after the time T1 has elapsed to cause the first power management circuit 104 to provide the core voltage VCC.
In addition, the embodiment of the current detection circuit 106 may include, for example, as shown in fig. 5, switching circuits SW1 and SW2 and a current-to-voltage circuit 502, wherein the switching circuits SW1 and SW2 are coupled to the current detection resistor RT1 of the first power management circuit 104, the current detection resistor RT2 of the second power management circuit 108 and the current-to-voltage circuit 502.
When detecting the current flowing through the first power management circuit 104, the control circuit 102 can control the switching circuits SW1 and SW2 to switch the current-to-voltage circuit 502 to the two ends of the current detection resistor RT1, so as to detect the current flowing through the current detection resistor RT 1. Similarly, during the detection of the current flowing through the second power management circuit 108, the control circuit 102 controls the switching circuits SW1 and SW2 to switch the current-to-voltage circuit 502 to the two ends of the current detection resistor RT2 to detect the current flowing through the current detection resistor RT 2.
The current-to-voltage circuit 502 may convert a current signal flowing through a resistor connected to the current-to-voltage circuit 502 into a voltage signal. Further, the current-to-voltage circuit 502 may include an operational amplifier 504 and an analog-to-digital conversion circuit 506, wherein positive and negative inputs of the operational amplifier 504 are respectively coupled to the switching circuits SW1 and SW2, and the analog-to-digital conversion circuit 506 is coupled to an output of the operational amplifier 504. The operational amplifier 504 may generate a voltage signal according to the voltage across the resistor to which it is connected, and the adc 506 may convert the voltage signal into a digital signal, which may be provided to a host connected to the control circuit 102, for example, to inform the host of the test result, such as the standby current, the operation current, etc., and rank the flash memory 114 accordingly.
In summary, the flash memory test device according to the embodiment of the invention can control the first power management circuit, the second power management circuit, the heater and the current detection circuit to adjust the test parameters of the flash memory and detect the corresponding test results.
Although the invention has been described with reference to the above embodiments, it should be understood that the invention is not limited thereto, but rather may be modified or altered somewhat by persons skilled in the art without departing from the spirit and scope of the invention.
Claims (10)
1. A flash memory testing apparatus for testing a flash memory, comprising:
the control circuitry is configured to control the operation of the control circuitry,
the first power management circuit is coupled with the control circuit and is controlled by the control circuit to provide a first test power supply voltage for the flash memory;
the second power management circuit is coupled with the control circuit and is controlled by the control circuit to provide a second test power supply voltage for the flash memory;
a heater for heating the flash memory and sensing the temperature of the flash memory;
the heating control circuit is coupled with the control circuit and the heater and is controlled by the control circuit to control the heater to heat the flash memory; and
the current detection circuit is coupled with the power management circuit and the control circuit and is controlled by the control circuit to detect the current flowing through the power management circuit.
2. The flash memory test apparatus of claim 1, wherein the first power management circuit and the second power management circuit each comprise:
a voltage stabilizing circuit;
the current detection resistor is coupled between the output end of the voltage stabilizing circuit and the output end of the power management circuit, and the voltage stabilizing circuit provides the first test power supply voltage or the second test power supply voltage through the current detection resistor;
the feedback circuit is coupled with the output end, the feedback end and the control circuit of the voltage stabilizing circuit, and the control circuit adjusts the resistance value of the feedback circuit so as to adjust the first test power supply voltage or the second test power supply voltage; and
and the control circuit adjusts the capacitance value of the variable capacitance circuit so as to adjust the boosting speed of the first test power supply voltage or the second test power supply voltage.
3. The flash memory test device of claim 1, wherein the first test power supply voltage is a core voltage and the second test power supply voltage is an input/output voltage.
4. The flash memory test apparatus of claim 3, wherein the core voltage is used to power core circuitry of the flash memory and the input-output voltage is used to power input-output circuitry of the flash memory.
5. The flash memory test device of claim 1, wherein the control circuit controls the first power management circuit and the second power management circuit to adjust start-up times of the first test power supply voltage and the second test power supply voltage.
6. The flash memory test apparatus of claim 2, wherein the current detection circuit comprises:
a current-to-voltage circuit;
the first switching circuit is coupled with one end of the current detection resistor of the first power management circuit and one end of the current detection resistor of the second power management circuit, the control circuit and the current-to-voltage circuit, and is controlled by the control circuit to connect the current-to-voltage circuit to the current detection resistor of the first power management circuit or the current detection resistor of the second power management circuit; and
the second switching circuit is coupled with the other ends of the current detection resistors of the first power management circuit and the second power management circuit, the control circuit and the current-to-voltage conversion circuit, and is controlled by the control circuit to switch and connect the current-to-voltage conversion circuit to the current detection resistor connected with the first switching circuit, and the current-to-voltage conversion circuit converts a current signal flowing through the current detection resistor connected with the current-to-voltage conversion circuit into a voltage signal.
7. The flash memory test apparatus of claim 6, wherein the current-to-voltage circuit comprises:
and the positive input end and the negative input end of the operational amplifier are respectively coupled with the first switching circuit and the second switching circuit, and the voltage signal is generated according to the voltage at the two ends of the current detection resistor connected with the current-to-voltage circuit.
8. The flash memory test apparatus of claim 7, wherein the current-to-voltage circuit further comprises:
and the analog-digital conversion circuit is coupled with the output end of the operational amplifier and converts the voltage signal into a digital signal.
9. The flash memory test apparatus of claim 2, wherein the feedback circuit comprises:
a first resistor;
the second resistor is coupled between the output end of the voltage stabilizing circuit and the ground with the first resistor, and a common joint of the first resistor and the second resistor is coupled with the feedback end of the voltage stabilizing circuit;
a plurality of switches coupled to the control circuit, wherein the conducting states of the switches are controlled by the control circuit; and
the third resistors and the corresponding switches are connected in series between the feedback end of the voltage stabilizing circuit and the ground.
10. The flash memory test apparatus of claim 2, wherein the capacitance circuit comprises:
the first capacitor is coupled between the output end of the power management circuit and the ground;
a plurality of switches coupled to the control circuit, wherein the conducting states of the switches are controlled by the control circuit; and
the second capacitors and the corresponding switches are connected in series between the output end of the power management circuit and the ground.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW111135872 | 2022-09-22 | ||
| TW111135872A TWI835306B (en) | 2022-09-22 | 2022-09-22 | Test apparatus for nand flash |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117789806A true CN117789806A (en) | 2024-03-29 |
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ID=90382217
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211372361.XA Pending CN117789806A (en) | 2022-09-22 | 2022-11-03 | Flash memory testing device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN117789806A (en) |
| TW (1) | TWI835306B (en) |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200828325A (en) * | 2006-12-18 | 2008-07-01 | Golden Emperor Internat Ltd | System and method for testing memories |
| KR20160045506A (en) * | 2014-10-17 | 2016-04-27 | 삼성전자주식회사 | Memory deviece test device and memory system test device |
| KR20170034166A (en) * | 2015-09-18 | 2017-03-28 | 삼성전자주식회사 | Semiconductor chip and semiconductor package having the same |
-
2022
- 2022-09-22 TW TW111135872A patent/TWI835306B/en active
- 2022-11-03 CN CN202211372361.XA patent/CN117789806A/en active Pending
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| TWI835306B (en) | 2024-03-11 |
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