CN117785743A - Peripheral interface timing parameter adaptive adjustment method and timing parameter adjustment device - Google Patents
Peripheral interface timing parameter adaptive adjustment method and timing parameter adjustment device Download PDFInfo
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Abstract
本申请涉及一种外设接口时序参数自适应调整方法及时序参数调整装置，通过根据对外设部件的初始化信号，按照预设调整步骤对外设部件的接口时序参数进行自适应调整，其中，预设调整步骤依次包括：按照预设的时序参数值对接口时序参数进行调整、通过对时序参数值中的建立时间参数值进行调整实现对接口时序参数的调整、通过对时序参数值中的保持时间参数值进行调整实现对接口时序参数的调整，在按照预设调整步骤对所述接口时序参数进行调整时，在当前步骤调整后得到的接口时序参数下进行一次数据读写操作，若成功，则将当前步骤得到的工作频率作为候选接口时序参数，若失败，则进行下一步骤的调整，并记录每一步骤的数据读写操作结果，在候选接口时序参数下，再进行数据读写操作，若成功，则完成外设部件的接口时序参数自适应调整，若失败，则返回记录为成功对应的步骤，并重新按照预设调整步骤对接口时序参数进行调整。采用本方法可实现对外设部件进行接口时序参数的自适应调整，从而避免人工操作，以提高效率。
The present application relates to a peripheral interface timing parameter adaptive adjustment method and a timing parameter adjustment device, which adaptively adjust the interface timing parameters of the peripheral component according to the initialization signal of the peripheral component according to the preset adjustment steps, wherein the preset The adjustment steps include: adjusting the interface timing parameters according to the preset timing parameter values, adjusting the interface timing parameters by adjusting the setup time parameter value in the timing parameter value, and adjusting the hold time parameter in the timing parameter value. Adjust the value to realize the adjustment of the interface timing parameters. When adjusting the interface timing parameters according to the preset adjustment steps, perform a data read and write operation under the interface timing parameters obtained after the adjustment in the current step. If successful, the The working frequency obtained in the current step is used as the candidate interface timing parameter. If it fails, adjust the next step and record the data read and write operation results of each step. Under the candidate interface timing parameters, perform the data read and write operation again. If If it succeeds, the adaptive adjustment of the interface timing parameters of the peripheral component is completed. If it fails, the steps corresponding to success are returned, and the interface timing parameters are adjusted again according to the preset adjustment steps. This method can be used to realize adaptive adjustment of interface timing parameters of peripheral components, thereby avoiding manual operations and improving efficiency.
Description
Technical Field
The present disclosure relates to the field of monolithic integrated circuits, and in particular, to a peripheral interface timing parameter adaptive adjustment method and a timing parameter adjustment device.
Background
With the development of the integrated circuit industry, the main frequency of a DSP (digital signal processing) chip is higher and higher, and for a peripheral interface, a general design is to work in a divide-by-N state of the main frequency. (e.g., DSP 400MHz for main frequency, and slow peripheral device operates in a divide-by-four state for main frequency, i.e., 100 MHz). When the DSP needs to perform over-frequency or down-frequency operation, the working frequency of the corresponding peripheral equipment is also changed, so that the actual time controlled by the time sequence parameter register is changed, the time change can cause the interface time sequence to not meet the requirement of a standard protocol, and the data transmission is failed. The timing parameter register is used to control the setup time and hold time of the data signal of the peripheral interface relative to the clock signal, and is generally used to record the number of cycles of the setup/hold time, for example, if the setup time is configured to be 4 and the hold time is configured to be 3, the setup time on the peripheral interface is 5T, and the hold time is 4T, where T represents the working clock cycle of the peripheral component, i.e., the value +1 cycles in the register.
However, the conventional processing manner is that when the DSP main frequency is changed, the user needs to modify the values of the peripheral interface timing register parameters through software to meet the timing requirement under the current peripheral operating frequency. In another case, when the chip and the corresponding peripheral component are connected together through the PCB board, the user needs to continuously attempt to adjust the value of the timing parameter register of the interface, even use the oscilloscope/logic analyzer to grasp the waveform of the interface, then analyze the waveform of the interface, and modify the value of the timing parameter register of the peripheral interface to meet the timing requirement of the current peripheral interface due to external interference conditions such as unequal length which may exist in the design process of the PCB board. This results in a deviation in the timing of the peripheral interface due to whatever reason as described above, requiring the user to continually try to modify the timing parameter registers by software to meet the timing requirements, although this problem can be solved, requiring the user to manually configure and adjust, and being cumbersome in steps, and not able to achieve adaptive adjustment.
Disclosure of Invention
Accordingly, it is desirable to provide a method and a device for adaptively adjusting timing parameters of a peripheral interface with timing parameters in a DSP chip.
A method for adaptively adjusting timing parameters of a peripheral interface, the method comprising:
acquiring an initialization signal of a peripheral component;
according to the initialization signal, performing self-adaptive adjustment on interface time sequence parameters of the peripheral component according to a preset adjustment step, wherein the preset adjustment step sequentially comprises the following steps: adjusting the time sequence of the peripheral component interface signal line according to a preset time sequence parameter value, adjusting the time sequence of the peripheral component interface signal line by adjusting the set time parameter value in the time sequence parameter value, and adjusting the time sequence of the peripheral component interface signal line by adjusting the hold time parameter value in the time sequence parameter value;
after the interface time sequence parameters are adjusted according to the preset adjustment step, performing data read-write operation once under the interface time sequence obtained after the adjustment of the current step, if the adjustment is successful, taking the interface time sequence parameters obtained in the current step as candidate time sequence parameters, if the adjustment is failed, performing adjustment of the next step according to the preset adjustment step, and recording the data read-write operation result of each step;
and under the candidate time sequence parameters, performing two times of data read-write operations, if the data read-write operations are successful, completing the self-adaptive adjustment of the interface time sequence parameters of the peripheral component, if the data read-write operations are failed, returning to the step of recording the data read-write operations as successful correspondence, and readjusting the peripheral interface time sequence according to the preset adjustment step.
In one embodiment, in the preset adjustment step, before the working frequency is adjusted according to the preset time sequence parameter value, performing data read-write operation on the peripheral component at the chip main frequency, if successful, taking the default interface time sequence parameter as the candidate time sequence parameter, if unsuccessful, performing adaptive adjustment of the interface time sequence parameter according to the preset adjustment step, and recording the data read-write operation result.
In one embodiment, when the interface timing is adjusted according to a preset timing parameter value:
adjusting the interface time sequence according to a preset first time sequence parameter value, performing data read-write operation for one time under the adjusted interface time sequence, and taking the interface time sequence parameter obtained in the current step as a candidate interface time sequence parameter if the data read-write operation is successful;
if the interface timing sequence is successful, the interface timing sequence parameter obtained in the current step is used as a candidate interface timing sequence parameter;
if the interface timing sequence is successful, the interface timing sequence parameter obtained in the current step is used as a candidate interface timing sequence parameter;
If the time of the data is not longer than the set time, the data read-write operation result is recorded, and the set time parameter value in the sequence parameter values is adjusted.
In one embodiment, the preset third timing parameter value is a timing parameter value after the last adaptive adjustment of the interface timing parameter is successful.
In one embodiment, the time-of-establishment parameter values among the time-of-order parameter values are adjusted:
on the basis of the third time sequence parameter value, gradually increasing the time setting parameter value according to a preset step length, and performing data read-write operation once after each time of increasing the time setting parameter value, and if successful, taking the interface time sequence parameter obtained in the current step as a candidate interface time sequence parameter;
if the data read-write operation fails, recording the data read-write operation result, gradually decreasing the set-up time parameter value according to a preset step length on the basis of the third time sequence parameter value, and performing data read-write operation once after decreasing the set-up time parameter value every time, and if the data read-write operation succeeds, taking the interface time sequence parameter obtained in the current step as a candidate interface time sequence parameter;
if the time of the data is not longer than the preset time, the data read-write operation result is recorded, and the retention time parameter value in the sequence parameter values is adjusted.
In one embodiment, the hold time parameter values of the timing parameter values are adjusted by:
on the basis of the third time sequence parameter value, gradually increasing the holding time parameter value according to a preset step length, and performing data read-write operation once after each time of increasing the holding time parameter value, and if successful, taking the interface time sequence parameter obtained in the current step as a candidate interface time sequence parameter;
if the data read-write operation fails, recording the data read-write operation result, gradually reducing the holding time parameter value according to a preset step length on the basis of the third time sequence parameter value, and performing data read-write operation once after reducing the holding time parameter value every time, wherein if the data read-write operation is successful, the interface time sequence parameter obtained in the current step is used as a candidate interface time sequence parameter;
if the time sequence parameter fails, recording the read-write operation result of the time sequence, outputting the time sequence parameter adjustment failure result, and sending out an interrupt program signal.
The application also provides a time sequence parameter adjusting device which is arranged in the DSP chip and comprises a frequency self-adaptive adjusting module, a time sequence parameter register, a transmission detection register and a time sequence shadow register module;
The interface time sequence parameter self-adaptive adjustment module is used for acquiring an initialization signal of the peripheral component, and carrying out self-adaptive adjustment on the interface time sequence parameter of the peripheral component according to a preset adjustment step according to the initialization signal, wherein the preset adjustment step sequentially comprises the following steps: loading a preset time sequence parameter value from the time sequence shadow register module to the time sequence parameter register to adjust interface time sequence parameters, adjusting the interface time sequence parameters by adjusting the setup time parameter value in the time sequence parameter register, and adjusting the interface time sequence parameters by adjusting the hold time parameter value in the time sequence parameter register;
when the time sequence parameters in the time sequence parameter register are adjusted according to the preset adjustment step, performing data read-write operation once under the interface time sequence parameters obtained after the adjustment of the current step, if the operation is successful, taking the interface time sequence parameters obtained in the current step as candidate interface time sequence parameters, if the operation is failed, performing adjustment of the next step according to the preset adjustment step, and recording the data read-write operation result of each step in the transmission detection register;
And under the candidate working frequency, performing two times of data read-write operations, if the operation is successful, completing the self-adaptive adjustment of the interface time sequence parameters of the peripheral component, and if the operation is failed, returning to the step of recording the data read-write operation result recorded in the transmission detection register as the successful correspondence, and readjusting the interface time sequence parameters according to the preset adjustment step.
In one embodiment, the timing shadow register module includes three timing shadow registers, each storing a predetermined different timing parameter value.
In one embodiment, the timing shadow register module and the timing parameter register belong to the same register set.
According to the interface time sequence parameter self-adaptive adjustment method and the time sequence parameter adjustment device for the peripheral, the interface time sequence parameters of the peripheral are subjected to self-adaptive adjustment according to the preset adjustment steps according to the initialization signals of the peripheral, wherein the preset adjustment steps sequentially comprise: adjusting the interface time sequence parameter according to a preset time sequence parameter value, adjusting the interface time sequence parameter by adjusting the set-up time parameter value in the time sequence parameter value, adjusting the interface time sequence parameter by adjusting the hold time parameter value in the time sequence parameter value, when the interface time sequence parameter is adjusted according to a preset adjusting step, performing data read-write operation under the interface time sequence parameter obtained after the adjustment of the current step, if successful, taking the interface time sequence parameter obtained in the current step as a candidate interface time sequence parameter, if unsuccessful, performing the adjustment of the next step, recording the data read-write operation result of each step, under the candidate interface time sequence parameter, performing two times of read-write operations again, if successful, completing the self-adaptive adjustment of the interface time sequence parameter of the peripheral component, if unsuccessful, returning to the step recorded as successful correspondence according to the data read-write operation result, and re-adjusting the interface time sequence parameter according to the preset adjusting step. By adopting the method, the self-adaptive adjustment of interface time sequence parameters of the peripheral component can be automatically realized, so that the efficiency is improved.
Drawings
FIG. 1 is a schematic diagram of an external device connected to a DSP chip in one embodiment;
FIG. 2 is a flow chart of a method for adaptively adjusting timing parameters of an external interface according to an embodiment;
FIG. 3 is a block diagram illustrating steps of a method for adaptively adjusting interface timing parameters in one embodiment;
fig. 4 is an internal structural diagram of a computer device in one embodiment.
Detailed Description
In order to make the objects, technical solutions and advantages of the present application more apparent, the present application will be further described in detail with reference to the accompanying drawings and examples. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the present application.
As shown in fig. 1, when a peripheral component (external device) is connected to a DSP chip through a peripheral interface, the timing sequence of the peripheral interface needs to be adjusted to match with the working frequency of the peripheral component, so as to solve the problems in the prior art that the timing sequence parameters of the interface provided to the peripheral component by the DSP chip need to be manually configured and adjusted, and the steps are complicated, as shown in fig. 2, the method for adaptively adjusting the timing sequence parameters of the peripheral interface is provided, and specifically comprises the following steps:
step S100, an initialization signal of the peripheral component is acquired.
Step S110, according to the initialization signal, performing self-adaptive adjustment on interface time sequence parameters of the peripheral component according to a preset adjustment step, wherein the preset adjustment step sequentially comprises: adjusting the interface time sequence parameter according to a preset time sequence parameter value, adjusting the interface time sequence parameter by adjusting the set-up time parameter value in the time sequence parameter value, and adjusting the interface time sequence parameter by adjusting the hold time parameter value in the time sequence parameter value.
Step S120, when the interface time sequence parameters are adjusted according to the preset adjustment step, performing data read-write operation once under the interface time sequence parameters obtained after the adjustment of the current step, if successful, taking the interface time sequence parameters obtained in the current step as candidate interface time sequence parameters, if unsuccessful, performing adjustment of the next step according to the preset adjustment step, and recording the data read-write operation result of each step.
Step S130, under the candidate interface time sequence parameters, two times of data read-write operations are performed, if the data read-write operations are successful, the interface time sequence parameters of the peripheral component are self-adaptively adjusted, if the data read-write operations are failed, the step of recording the data read-write operations as successful corresponding is returned, and the interface time sequence parameters are adjusted again according to the preset adjustment step.
In this embodiment, in the initialization stage of the external interface, the peripheral connectivity is checked, and when the timing sequence is found to be unsatisfied, that is, the data read-write operation cannot be performed, the adaptive adjustment is performed according to the preset steps until the correct read-write transmission can be performed, so as to reduce the process of requiring the manual configuration adjustment.
In step S100, an initialization signal of the peripheral component is obtained, that is, after the peripheral component is connected to the DSP chip through the peripheral interface, the DSP chip senses that the peripheral interface has a device connection, that is, performs an initialization operation on the peripheral interface.
In step S110-120, before adjusting the interface timing parameter according to the preset timing parameter value in the preset adjustment step, performing data read-write operation on the external component under the chip main frequency, if successful, using the default interface timing parameter as the candidate working frequency, if unsuccessful, performing adaptive adjustment on the interface timing parameter according to the preset adjustment step, and recording the data read-write operation result.
In this embodiment, in the preset adjustment step, the relevant timing parameters in the timing register are adjusted according to the preset timing parameter value, the external device is not successfully subjected to data read-write operation under the interface timing parameters obtained after the adjustment, and then the setup time parameter value and the hold time parameter value in the timing parameters are adjusted.
In this embodiment, the timing parameter value in the timing register is actually adjusted, so that the setup/hold time of the peripheral interface signal line is adjusted to obtain different interface timing parameters, and the DSP chip and the peripheral device are in data communication through the timing parameters.
In this embodiment, when the interface timing parameter is adjusted according to the preset timing parameter value, the interface timing parameter is adjusted according to the preset first timing parameter value, second timing parameter value, and third timing parameter value in sequence.
Specifically, the interface timing parameters are adjusted according to the preset first timing parameter value, the data read-write operation is performed once under the adjusted interface timing parameters, if successful, the interface timing parameters obtained in the current step are used as candidate interface timing parameters, and then the subsequent operation is performed according to the step S130.
Specifically, after the adjustment is failed according to the first time sequence parameter value, the data read-write operation result is recorded, the working frequency is adjusted according to the preset second time sequence parameter value, the data read-write operation is performed once under the adjusted interface time sequence parameter, if the adjustment is successful, the working frequency obtained in the current step is used as the candidate interface time sequence parameter, and then the subsequent operation is performed according to the step S130.
Specifically, after the adjustment is failed according to the second time sequence parameter value, the data read-write operation result is recorded, the interface time sequence parameter is adjusted according to the preset third time sequence parameter value, the data read-write operation is performed once under the adjusted working frequency, if the adjustment is successful, the interface time sequence parameter obtained in the current step is used as the candidate interface time sequence parameter, and then the subsequent operation is performed according to the step S130.
Specifically, after the adjustment according to the third time sequence parameter value fails, the data read-write operation result is recorded, and then the setup time parameter value in the time sequence parameter values is adjusted.
In this embodiment, the first timing parameter value and the second timing parameter value may be preset according to experience, and when the first timing parameter value is adjusted, it may be assumed that the current error condition is that the main frequency of the chip exceeds the operating frequency of the peripheral component, which is equivalent to that the operating frequency of the peripheral interface is higher than the operating frequency of the peripheral component, and the first timing parameter value may be preset as the timing parameter value capable of reducing the main frequency of the chip. In contrast, when the adjustment is performed according to the second timing parameter value, it may be assumed that the current error condition is that the chip main frequency is lower than the operating frequency of the peripheral component, which is equivalent to that the operating frequency of the peripheral interface is lower than the operating frequency of the peripheral component, and the second timing parameter may be preset to a timing parameter value capable of raising the chip main frequency.
In this embodiment, the third timing parameter value may be preset as the timing parameter value after the last adaptive adjustment of the interface timing parameter is successful. And when the setup time parameter value and the hold time parameter value are adjusted, the third time sequence parameter value is used as an initial value for adjustment.
In the present embodiment, when the setup time parameter value among the timing parameter values is adjusted: on the basis of the third time sequence parameter value, the time setting parameter value is gradually increased according to a preset step length, and after the time setting parameter value is increased each time, data read-write operation is carried out once, if successful, the interface time sequence parameter obtained in the current step is used as a candidate interface time sequence parameter, and then follow-up operation is carried out according to step S130.
In this embodiment, if the adjustment of the setup time parameter value for enlarging fails, the result of the data read-write operation is recorded, and on the basis of the third time sequence parameter value, the setup time parameter value is gradually decreased according to a preset step length, after each time the setup time parameter value is decreased, the data read-write operation is performed once, and if successful, the interface time sequence parameter obtained in the current step is used as a candidate interface time sequence parameter. If the adjustment of the set-up time parameter value fails for two times, recording the read-write operation result of the data, and then adjusting the retention time parameter value in the time sequence parameter values.
In this embodiment, when the setup time parameter value is adjusted, the setup time parameter value is adjusted for multiple times according to a preset step length, and a read-write operation result is performed after each adjustment, if the setup time parameter value fails, the setup time parameter value is adjusted up or down again according to the step length until the setup time parameter value reaches a preset adjustment maximum value or adjustment minimum value, or if the setup time parameter value fails, the adjustment result of the step is recorded as failure.
In the present embodiment, when the hold time parameter value among the time parameter values is adjusted: similarly, on the basis of the third time sequence parameter value, the holding time parameter value is gradually increased according to a preset step length, and after the holding time parameter value is increased each time, data read-write operation is performed once, if successful, the interface time sequence parameter obtained in the current step is used as a candidate interface time sequence parameter, and then subsequent operation is performed according to step S130.
In this embodiment, if the adjustment of the hold time parameter value to increase fails, the result of the data read-write operation is recorded, and on the basis of the third time sequence parameter value, the hold time parameter value is stepped down according to a preset step length, after each time the hold time parameter value is stepped down, the data read-write operation is performed once, if successful, the interface time sequence parameter obtained in the current step is used as a candidate interface time sequence parameter, and then the subsequent operation is performed according to step S130. If the two times of adjustment of the retention time parameter value are failed, recording the read-write operation result of the times of data, outputting the time sequence parameter adjustment failure result, and sending out an interrupt program signal.
Similarly, when the holding time parameter value is adjusted, the holding time parameter value is adjusted for a plurality of times according to a preset step length, and a read-write operation result is carried out after each adjustment, if the holding time parameter value fails, the holding time parameter value is adjusted up or down again according to the step length until the holding time parameter value reaches a preset maximum adjustment value or a preset minimum adjustment value, or if the holding time parameter value fails, the adjustment result of the step is recorded as failure.
In this embodiment, the whole preset adjustment step actually includes 10 steps, which are in turn:
step1: taking the main frequency as the working frequency, performing data read-write operation on the external component once, if successful, implementing step S120, and if failed, implementing step2;
step2: setting a time sequence parameter register according to a first time sequence parameter value, performing data read-write operation on an external component for one time under the adjusted working frequency, if successful, implementing step S120, and if failed, implementing step3;
step3: setting a time sequence parameter register according to the second time sequence parameter value, performing data read-write operation on the external component for one time under the adjusted working frequency, if successful, implementing step S120, and if failed, implementing step4;
step4: setting a time sequence parameter register according to the third time sequence parameter value, performing data read-write operation on the external component for one time under the adjusted working frequency, if successful, implementing step S120, and if failed, implementing step5;
step5: on the basis of the third time sequence parameter value, gradually increasing the set-up time parameter value, performing data read-write operation on the external component once under the adjusted working frequency, if successful, implementing step S120, and if failed, implementing step6;
step6: on the basis of the third time sequence parameter value, the set-up time parameter value is gradually reduced, the external component is subjected to data read-write operation once under the adjusted working frequency, if successful, the step S120 is implemented, and if failed, the step7 is implemented;
step7: on the basis of the third time sequence parameter value, gradually increasing the holding time parameter value, performing data read-write operation on the external component once under the adjusted working frequency, if successful, implementing step S120, and if failed, implementing step8;
step8: on the basis of the third time sequence parameter value, the holding time parameter value is gradually reduced, the external component is subjected to data read-write operation once under the adjusted working frequency, if successful, step S120 is implemented, and if failed, step10 is implemented.
Specifically, step10 is that the timing parameter adjustment fails, the initialization is not completed, and the recording is performed, and at the same time, an interrupt is sent to the interrupt response program.
In step S120, in order to avoid the occurrence of sporadic correct data transmission, the situation is not repeatable, so that under the candidate operating frequency, 2 more times of read-write verification of different types of data are required, if all the transmissions are correct, the timing parameter adjustment can be considered successful, the initialization of the peripheral component is completed, and the recording is performed, and meanwhile, the parameter in the current timing register is reserved as the third timing parameter for the next adaptive adjustment of the peripheral component. If the transmission fails, the sporadic primary data transmission is considered to be correct, but the repeatability is not realized, the current time sequence parameter configuration is still in an unreasonable state, and a plurality of corresponding steps in the recorded data read-write operation result are required to be returned, and the time sequence parameter adjustment is carried out again according to the preset adjustment step.
As shown in fig. 3, the whole adaptive adjustment process is shown, wherein step S120 is step9.
According to the peripheral interface time sequence parameter self-adaptive adjustment method, after the peripheral component is connected to the DSP chip, the interface time sequence parameters provided by the main chip for the peripheral component are adjusted according to the given time sequence parameter adjustment step, meanwhile, under the condition that candidate interface time sequence parameters are obtained, data of different types are read and written for transmission, and on the basis of realizing the peripheral component interface time sequence parameter self-adaptive adjustment, the fact that the finally obtained interface time sequence parameters are effective is also ensured.
It should be understood that, although the steps in the flowchart of fig. 1 are shown in sequence as indicated by the arrows, the steps are not necessarily performed in sequence as indicated by the arrows. The steps are not strictly limited to the order of execution unless explicitly recited herein, and the steps may be executed in other orders. Moreover, at least some of the steps in fig. 1 may include multiple sub-steps or stages that are not necessarily performed at the same time, but may be performed at different times, nor do the order in which the sub-steps or stages are performed necessarily performed in sequence, but may be performed alternately or alternately with at least a portion of other steps or sub-steps of other steps.
The application also provides a time sequence parameter adjusting device which is arranged in the DSP chip and comprises an interface time sequence parameter self-adaptive adjusting module, a time sequence parameter register, a transmission detection register and a time sequence shadow register module.
The interface time sequence parameter self-adaptive adjustment module is used for acquiring an initialization signal of the peripheral component, and carrying out self-adaptive adjustment on the interface time sequence parameter of the peripheral component according to a preset adjustment step according to the initialization signal, wherein the preset adjustment step sequentially comprises the following steps: and loading a preset time sequence parameter value into the time sequence parameter register from the time sequence shadow register module, adjusting the interface time sequence parameter by adjusting the setup time parameter value in the time sequence parameter register, and adjusting the interface time sequence parameter by adjusting the hold time parameter value in the time sequence parameter register.
When the time sequence parameters in the time sequence parameter register are adjusted according to the preset adjustment step, performing data read-write operation once under the interface time sequence parameters obtained after the adjustment of the current step, if the operation is successful, taking the working frequency obtained in the current step as the candidate interface time sequence parameters, if the operation is failed, performing adjustment of the next step according to the preset adjustment step, and recording the data read-write operation result of each step in the transmission detection register.
And under the candidate interface time sequence parameters, performing two times of data read-write operations, if the interface time sequence parameters of the peripheral component are successful, completing the self-adaptive adjustment of the interface time sequence parameters of the peripheral component, if the interface time sequence parameters of the peripheral component are failed, returning to the step of recording the data read-write operation results recorded in the transmission detection register as successful correspondence, and readjusting the interface time sequence parameters according to the preset adjustment step.
In this embodiment, the interface timing parameter adaptive adjustment module may be a part of a control module in the DSP chip, and the interface timing parameter adaptive adjustment module adjusts the timing parameter in the timing parameter register according to the above-mentioned peripheral interface timing parameter adaptive adjustment method, that is, adaptively adjusts the setup/hold time of the interface signal provided by the chip to the peripheral component, and the process thereof is explained with reference to the above-mentioned interface timing parameter adaptive adjustment method for the peripheral component, which is not described herein.
In this embodiment, the timing shadow register module includes three timing shadow registers, which respectively store preset different timing parameter values.
Preferably, the timing shadow register module includes a first timing shadow register, a second timing shadow register, and a third timing shadow register, which store a first timing parameter value, a second timing parameter value, and a third timing parameter value, respectively, that is, the timing parameter value obtained after the last adaptive adjustment is successful.
In this embodiment, according to the peripheral components, the timing shadow register module and the timing parameter register belong to the same register group. For the peripheral with simple general interface, the time sequence shadow register and the time sequence parameter register comprise 1 set-up time register and 1 hold time register, and the time sequence shadow register and the time sequence parameter register are in one-to-one correspondence, and a preset value is loaded from the set-up time register of the time sequence shadow register to the set-up time register in the time sequence parameter register each time. For peripherals with complex interfaces, the timing shadow register and the timing parameter register may include multiple sets of setup time registers and hold time registers, and then one-to-one correspondence is required.
In this embodiment, the transmission detection register is used to record whether the timing parameter in each step is successfully adjusted, and a certain position fixed in the register records the result of the corresponding step. Thus, when the read-write verification of the different data is failed for 2 more times when Step9 is implemented, the corresponding Step can be returned to be readjusted according to the numerical value recorded in the transmission detection register.
Specifically, the setting of the transmission detection register is shown in table 1.
Table 1 transmission detection register bit specification
In this embodiment, according to the method for adaptively adjusting the timing parameters of the peripheral interface, the frequency adaptive adjustment module specifically implements the following steps:
step1: when the external part is initialized, the external part firstly performs data writing and reading operation through the transmission detection register, if the external part is successful, the external part directly jumps to step9, if the read data is wrong, the external part marks the transmission detection register, and step2 is performed.
Step2: the current error condition is assumed to be that the main frequency of the chip exceeds the preset working frequency, at the moment, the working frequency of the peripheral interface is equivalent to being higher than the preset working frequency, at the moment, the establishment and maintenance time calculated according to the initial value of the time sequence parameter register does not meet the requirement of an interface protocol. Then the timing parameter values are loaded from the timing shadow register 1 into the timing parameter registers, preferably based on empirical values. And re-performing a data write-read operation, if successful, directly jumping to step9, if failed, marking in the transmission detection register, and performing step3.
Step3: the current error condition is assumed to be that the main frequency of the chip is obviously lower than the preset working frequency, at the moment, the working frequency of the peripheral interface is equivalent to being lower than the preset working frequency, at the moment, the establishment and maintenance time calculated according to the initial value of the time sequence parameter register does not meet the requirement of an interface protocol. Then the timing parameter values are loaded from the timing shadow register 2 into the timing parameter registers, preferably based on empirical values. And re-performing a data write-read operation, if successful, directly jumping to step9, if failed, marking in the transmission detection register, and performing step4.
Step4: the timing parameter values are loaded from the timing shadow register 3 into the timing parameter registers. And re-performing a data write-read operation, if successful, directly jumping to step9, if failed, marking in the transmission detection register, and performing step5.
Step5: resetting the value of the time sequence parameter register, carrying out fixed retention time parameter value, gradually adjusting the set time parameter value according to the record in the transmission detection register, then carrying out read-write detection again, if successful, directly jumping to step9, if unsuccessful, carrying out record in the transmission detection register, and carrying out step6.
Step6: resetting the value of the time sequence parameter register, carrying out fixed retention time parameter value, gradually reducing the set time parameter value according to the record in the transmission detection register, then carrying out read-write detection again, if successful, directly jumping to step9, if unsuccessful, carrying out record in the transmission detection register, and carrying out step7.
Step7: resetting the value of the time sequence parameter register, carrying out fixed establishment of the time parameter value, gradually adjusting the value of the holding time parameter according to the record in the transmission detection register, then carrying out read-write detection again, if successful, directly jumping to step9, if unsuccessful, carrying out record in the transmission detection register, and carrying out step8.
Step8: resetting the value of the time sequence parameter register, carrying out fixed establishment of the time parameter value, gradually reducing the holding time parameter value according to the record in the transmission detection register, then carrying out read-write detection again, if successful, directly jumping to step9, if unsuccessful, carrying out record in the transmission detection register, and carrying out step10.
Step9: performing writing, reading and checking of different data for 2 times, if all the data are transmitted correctly, successfully adjusting the time sequence parameters, finishing initialization, recording in a transmission detection register, and simultaneously, storing the configuration of the time sequence parameter register in the current state to a shadow register 3; if the transmission fails, recording is carried out in a transmission detection register, and the time sequence parameter of the next stage is adaptively adjusted according to the value of the transmission detection register.
Step10: the time sequence parameter is failed to be adjusted, the initialization is not completed, the record is carried out in the transmission detection register, and meanwhile, the interrupt is sent to the interrupt response program.
In the above-mentioned interface time sequence parameter self-adaptive adjustment module, a transmission detection register is newly added in the hardware design, when the peripheral component is initialized, according to the transmission detection register, the initialization control logic starts working, and makes write-read access detection on the external device, and self-adaptively adjusts the value of the time sequence parameter register, so as to ensure that the data communication between the peripheral component and the external device is normal. The new timing parameter shadow register set can improve the efficiency of self-adaptive adjustment of the timing parameters according to experience, 3 timing parameter shadow registers can be designed in advance according to theory and experience values, and normally, the timing shadow registers 1 and 2 are non-writable read-only registers used for storing the preset timing parameters of the peripheral interface. The timing shadow register 3 can store the timing parameter value of the normal transmission after the last self-adaptive adjustment, or can be configured by a user before the self-adaptive adjustment of the timing parameter, and the register is only controlled by the reset of the chip and is not controlled by the reset of the peripheral component. The module can carry out self-adaptive adjustment on the peripheral interface time sequence parameters, reduces the complicated manual adjustment process of a user, can set the time sequence parameter shadow register according to experience, and improves the self-adaptive adjustment efficiency.
In one embodiment, a computer device is provided, which may be a terminal, and the internal structure of which may be as shown in fig. 4. The computer device includes a processor, a memory, a network interface, a display screen, and an input device connected by a system bus. Wherein the processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage media. The network interface of the computer device is used for communicating with an external terminal through a network connection. The computer program, when executed by a processor, implements a method for adaptively adjusting interface timing parameters for a peripheral component. The display screen of the computer equipment can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer equipment can be a touch layer covered on the display screen, can also be keys, a track ball or a touch pad arranged on the shell of the computer equipment, and can also be an external keyboard, a touch pad or a mouse and the like.
Those skilled in the art will appreciate that the structures shown in FIG. 4 are block diagrams only and do not constitute a limitation of the computer device on which the present aspects apply, and that a particular computer device may include more or less components than those shown, or may combine some of the components, or have a different arrangement of components.
In one embodiment, a computer device is provided comprising a memory and a processor, the memory having stored therein a computer program, the processor when executing the computer program performing the steps of:
acquiring an initialization signal of a peripheral component;
according to the initialization signal, the working frequency of the peripheral component is adaptively adjusted according to a preset adjusting step, wherein the preset adjusting step sequentially comprises the following steps: adjusting interface time sequence parameters according to preset time sequence parameter values, adjusting the interface time sequence parameters by adjusting the established time parameter values in the time sequence parameter values, and adjusting the interface time sequence parameters by adjusting the retention time parameter values in the time sequence parameter values;
when the interface time sequence parameters are adjusted according to the preset adjustment step, performing data read-write operation once under the interface time sequence parameters obtained after the adjustment of the current step, if the interface time sequence parameters obtained in the current step are successful, taking the interface time sequence parameters obtained in the current step as candidate interface time sequence parameters, if the interface time sequence parameters fail, performing adjustment of the next step according to the preset adjustment step, and recording the data read-write operation result of each step;
And under the candidate interface time sequence parameters, performing two times of data read-write operations, if the data read-write operations are successful, completing the self-adaptive adjustment of the interface time sequence parameters of the peripheral component, if the data read-write operations are failed, returning to the step recorded as successful correspondence according to the data read-write operation results, and readjusting the interface time sequence parameters according to the preset adjustment step.
In one embodiment, a computer readable storage medium is provided having a computer program stored thereon, which when executed by a processor, performs the steps of:
acquiring an initialization signal of a peripheral component;
according to the initialization signal, performing self-adaptive adjustment on interface time sequence parameters of the peripheral component according to a preset adjustment step, wherein the preset adjustment step sequentially comprises the following steps: adjusting interface time sequence parameters according to preset time sequence parameter values, adjusting the interface time sequence parameters by adjusting the established time parameter values in the time sequence parameter values, and adjusting the interface time sequence parameters by adjusting the retention time parameter values in the time sequence parameter values;
when the interface time sequence parameters are adjusted according to the preset adjustment step, performing data read-write operation once under the interface time sequence parameters obtained after the adjustment of the current step, if the interface time sequence parameters obtained in the current step are successful, taking the interface time sequence parameters obtained in the current step as candidate interface time sequence parameters, if the interface time sequence parameters fail, performing adjustment of the next step according to the preset adjustment step, and recording the data read-write operation result of each step;
And under the candidate interface time sequence parameters, performing two times of data read-write operations, if the data read-write operations are successful, completing the self-adaptive adjustment of the interface time sequence parameters of the peripheral component, if the data read-write operations are failed, returning to the step recorded as successful correspondence according to the data read-write operation results, and readjusting the interface time sequence parameters according to the preset adjustment step.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the various embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few embodiments of the present application, which are described in more detail and are not to be construed as limiting the scope of the invention. It should be noted that it would be apparent to those skilled in the art that various modifications and improvements could be made without departing from the spirit of the present application, which would be within the scope of the present application. Accordingly, the scope of protection of the present application is to be determined by the claims appended hereto.
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