CN116127888A - Method, device and storage medium for automatically generating simulation excitation - Google Patents

Abstract

The embodiment of the disclosure discloses a method, a device and a storage medium for automatically generating simulation excitation, wherein the method for automatically generating the simulation excitation comprises the following steps: obtaining simulation configuration information of a circuit to be simulated, wherein the simulation configuration information comprises: product basic configuration information, mode register configuration information and function command configuration information; setting a simulation configuration table of a circuit to be simulated based on the simulation configuration information, and generating a test pattern based on the simulation configuration table; generating a test code according to the test pattern conforming to the rule; simulating the test code to obtain a corresponding simulation result; based on the simulation result, a simulation excitation file is generated. Thus, compared with the related art, the embodiment of the invention effectively ensures the correctness of the test pattern and reduces the error rate; meanwhile, the test code and the simulation environment can be automatically generated, the development time of simulation excitation is shortened, and the verification efficiency of the chip is improved.

Description

Method, device and storage medium for automatically generating simulation excitation

Technical Field

The embodiment of the disclosure relates to the technical field of semiconductors, in particular to a method, a device and a storage medium for automatically generating simulation excitation.

Background

The ever-increasing scale of integrated circuits and the ever-increasing abundance of integrated circuit functions present greater challenges to the quality and efficiency of chip verification. To ensure the sufficiency of chip verification, a large number of different stimuli (Stimulus) need to be applied to the chip at the time of simulation to verify the functionality and timing errors of the chip. The simulation stimulus development process in the related art requires a special verifier to manually perform through a series of complicated steps, which is very time-consuming and error-prone. Therefore, it is necessary to shorten the development time of simulation excitation and improve the efficiency of chip verification.

Disclosure of Invention

In view of this, the embodiments of the present disclosure provide a method, an apparatus, and a storage medium for automatically generating a simulation excitation, so as to shorten development time of the simulation excitation and improve efficiency of chip verification.

The technical scheme of the invention is realized as follows:

the embodiment of the disclosure provides a method for automatically generating simulation excitation, which comprises the following steps: obtaining simulation configuration information of a circuit to be simulated, wherein the simulation configuration information comprises: product basic configuration information, mode register configuration information and function command configuration information; setting a simulation configuration table of a circuit to be simulated based on the simulation configuration information, and generating a test pattern based on the simulation configuration table; generating a test code according to the test pattern conforming to the rule; simulating the test code to obtain a corresponding simulation result; based on the simulation result, a simulation excitation file is generated.

In the above scheme, generating the test code according to the test pattern includes: checking whether the test pattern accords with the rule according to a preset rule file; if the test pattern meets the rule, generating a test code based on the test pattern.

In the above scheme, after checking whether the test pattern accords with the rule according to the preset rule file, the method further comprises: and if the test pattern does not accord with the rule, re-acquiring simulation configuration information of the circuit to be simulated, setting a simulation configuration table, and generating a new test pattern until the new test pattern accords with the rule.

In the above scheme, the rule file includes: a mode register configuration rule and a function command configuration rule.

In the above scheme, generating the test code based on the test pattern further includes: and generating test patterns by an automatic script according to the code grammar and the corresponding rules, and applying the test patterns to the simulated test codes.

In the above scheme, the simulation of the test code to obtain the corresponding simulation result includes: determining a standard model corresponding to a circuit to be simulated; according to the standard model, automatically establishing a simulation environment of the verification platform; and loading the test code into a simulation environment to perform verilog simulation so as to obtain a corresponding simulation result.

In the above scheme, the simulation result includes: an input waveform and an output waveform; the input waveform corresponds to the input signal waveform corresponding to the test code; the output waveform is the output signal waveform after simulation is performed on the standard model.

In the above scheme, after loading the test code into the simulation environment to perform verilog simulation to obtain the corresponding simulation result, the method further includes: obtaining a log file of the verilog simulation, and checking whether the verilog simulation is successful or not according to the log file; if the verilog simulation is successful, generating a simulation excitation file based on a simulation result; if the verilog simulation is unsuccessful, ending the current flow.

In the above scheme, generating the simulation excitation file based on the simulation result includes: generating an original excitation file according to part of waveforms in a simulation result based on a simulation configuration table; and carrying out post-processing on the original excitation file to generate a simulation excitation file.

In the above scheme, post-processing the original excitation file includes: the vector mode definition and waveform parameter settings are added to the original excitation file.

In the above scheme, the basic configuration information of the product includes: product type, frequency, and composition pattern; the mode register configuration information includes: burst length, burst type, column address strobe delay, mode of operation, and write burst mode; the function command configuration information includes: read command, write command, activate command, bank address, row address, column address.

The embodiment of the disclosure also provides a device for automatically generating the simulation excitation, which comprises: a simulation configuration interface configured to acquire simulation configuration information of a circuit to be simulated, set a simulation configuration table of the circuit to be simulated based on the simulation configuration information, and generate a test pattern based on the simulation configuration table; the simulation configuration information comprises: product basic configuration information, mode register configuration information and function command configuration information; a test code generation module configured to receive a test pattern conforming to a rule from the simulation configuration interface; and generating a test code according to the test pattern conforming to the rule; a verification platform configured to receive test code from the test code generation module; and simulating the test code to obtain a corresponding simulation result; the system comprises an excitation generation module, a verification platform and a simulation module, wherein the excitation generation module is configured to receive simulation results from the verification platform; and generating a simulation excitation file based on the simulation result.

In the above scheme, the device for automatically generating the simulation excitation further comprises a checking module, wherein the checking module is configured to check whether the test pattern accords with the rule according to a preset rule file.

The embodiment of the disclosure also provides a device for automatically generating the simulation excitation, which comprises: a memory for storing executable instructions; and the processor is used for realizing the method in the scheme when executing the executable instructions stored in the memory.

The disclosed embodiments also provide a storage medium storing executable instructions for causing a processor to execute the method in the above scheme.

In an embodiment of the present disclosure, a method for automatically generating a simulation stimulus includes: obtaining simulation configuration information of a circuit to be simulated, wherein the simulation configuration information comprises: product basic configuration information, mode register configuration information and function command configuration information; setting a simulation configuration table of a circuit to be simulated based on the simulation configuration information, and generating a test pattern based on the simulation configuration table; generating a test code according to the test pattern conforming to the rule; simulating the test code to obtain a corresponding simulation result; based on the simulation result, a simulation excitation file is generated. Thus, compared with the related art, the embodiment of the invention effectively ensures the correctness of the test pattern and reduces the error rate; meanwhile, the test code and the simulation environment can be automatically generated, the development time of simulation excitation is shortened, and the verification efficiency of the chip is improved.

Drawings

FIG. 1 is a flow chart of a method for automatically generating simulated stimulus according to an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of an apparatus for automatically generating simulated stimulus according to an embodiment of the present disclosure;

FIG. 3 is a second flow chart of a method for automatically generating simulated stimulus according to an embodiment of the present disclosure;

FIG. 4 is a flowchart illustrating a method for automatically generating simulated stimulus according to an embodiment of the present disclosure;

FIG. 5 is a second schematic structural diagram of an apparatus for automatically generating simulated stimulus according to an embodiment of the present disclosure;

FIG. 6 is a flowchart illustrating a method for automatically generating simulated stimulus according to an embodiment of the present disclosure;

FIG. 7 is a schematic diagram III of an apparatus for automatically generating simulated stimulus according to an embodiment of the present disclosure;

FIG. 8 is a flowchart of a method for automatically generating simulated stimulus according to an embodiment of the present disclosure;

fig. 9 is a schematic structural diagram of an apparatus for automatically generating simulation stimulus according to an embodiment of the present disclosure.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present disclosure more apparent, the technical solutions of the present disclosure are further elaborated below in conjunction with the drawings and the embodiments, and the described embodiments should not be construed as limiting the present disclosure, and all other embodiments obtained by those skilled in the art without making inventive efforts are within the scope of protection of the present disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.

If a similar description of "first/second" appears in the application document, the following description is added, in which the terms "first/second/third" merely distinguish similar objects and do not represent a specific ordering of the objects, it being understood that "first/second/third" may, where allowed, interchange a specific order or precedence, to enable embodiments of the disclosure described herein to be practiced otherwise than as illustrated or described herein.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.

In the related art, the simulation excitation development process needs a special verifier to manually complete through a series of complicated steps, including: configuration of product-related parameters, such as setting Mode registers (Mode registers) and function commands (Command sequences), etc.; writing and checking test codes; building a Verilog verification environment; and Spice (Simulation program with integrated circuit emphasis) simulating the extraction of the excitation. The process is very time-consuming and error-prone, and is not beneficial to the research and development of the whole project; the complex flow also increases the difficulty of quickly customizing simulation incentives that contain certain functional commands.

FIG. 1 is a schematic flow chart of an alternative method for automatically generating simulated stimulus provided by an embodiment of the present disclosure, which will be described in connection with the steps shown in FIG. 1.

S101, acquiring simulation configuration information of a circuit to be simulated; the simulation configuration information comprises: product basic configuration information, mode register configuration information, and function command configuration information.

In an embodiment of the present disclosure, simulation configuration information includes: product basic configuration information, mode register configuration information, function command configuration information and the like. The circuit to be emulated may be a dynamic random access memory (Dynamic Random Access Memory, DRAM). Accordingly, the product basic configuration information includes: information on product type, DRAM frequency and composition pattern, etc. The product type may be a specification of dynamic random access memory; e.g., DDR4 and DDR5, etc. The DRAM Frequency may be a dynamic random access memory Frequency (Frequency); for example, DDR4 has frequencies of 1600MHz, 2400MHz, 2800MHz, 3200MHz, etc. The composition mode may refer to the number of data channels of the dynamic random access memory; for example, modes such as X4, X8, and X16.

In the embodiment of the disclosure, the product specifications corresponding to different product types are different, so that the test patterns (patterns) corresponding to the products are different; products with different frequencies and different corresponding simulation environments; the different pin and signal numbers of the products used in different composition modes can affect the final simulation excitation. Therefore, when generating simulation excitation, the basic configuration information of the product such as the product type, frequency and composition mode of the circuit to be simulated needs to be acquired.

In the embodiment of the disclosure, each product needs to formulate a mode register configuration according to the product specification, and configuration options of each mode register are defined. Each product needs to make a function command list according to the product specification, and defines all supported commands and parameters of the product. Therefore, it is necessary to select product basic configuration information of a product, thereby determining a corresponding product specification, setting a mode register and a function command, and thereby acquiring the mode register configuration information and the function command configuration information of a circuit to be emulated.

FIG. 2 is a schematic diagram of an alternative configuration of an apparatus for automatically generating simulated stimulus provided in an embodiment of the present disclosure, where the method for automatically generating simulated stimulus shown in FIG. 1 may be implemented using the apparatus for automatically generating simulated stimulus 100 shown in FIG. 2.

In embodiments of the present disclosure, referring to fig. 2, a user interface for customizing test patterns may be provided at a simulation configuration interface, namely: providing an input end for setting basic configuration information of a product (corresponding to the basic configuration information of the product in fig. 2), an input end for setting configuration information of a mode register (corresponding to the mode register in fig. 2) and an input end for setting configuration information of a function command (corresponding to the function command in fig. 2) at the simulation configuration interface, and providing preset configuration options, so that a user can select and determine the simulation configuration information of the product through the simulation configuration interface. Thus, the error writing information or the missing information can be avoided, and the error rate is reduced; meanwhile, interference to subsequent operation can be avoided.

S102, setting a simulation configuration table of the circuit to be simulated based on the simulation configuration information, and generating a test pattern based on the simulation configuration table.

In the embodiments of the present disclosure, the test pattern means: a series of functional commands applied to the memory chip, namely: different combinations of functional commands such as read and write commands. The test pattern is mainly used to verify the functional errors of the memory chip.

In the embodiment of the disclosure, the simulation configuration table comprises a product basic configuration table, a mode register configuration table, a function command configuration list and the like. With continued reference to FIG. 2, the information contained in the simulation configuration table has a hierarchy and a precedence order. The user needs to select the product type first, then select the corresponding frequency from a plurality of frequencies determined by the product type, and select the corresponding composition mode from a plurality of composition modes determined by the product type; thus, the basic configuration information of the product is obtained, and a corresponding basic configuration table of the product is generated. For example, DDR4 has frequencies of 1600MHz, 2400MHz, 2800MHz, 3200MHz, etc. After determining that the product type is DDR4, the user selects one frequency from 1600MHz, 2400MHz, 2800MHz, 3200MHz and the like as the frequency of the product.

In the disclosed embodiment, the basic configuration information of the product is in a hierarchy. The mode register and the function command are at the same level and are at the level next to the level at which the basic configuration information of the product is located. After the basic configuration information of the product is selected by a user, other configurations such as a mode register, a function command and the like of the circuit to be simulated can be set according to the product specification corresponding to the basic configuration information of the product, and the configuration information of the mode register and the configuration information of the function command of the product are obtained, so that a corresponding mode register configuration table and a corresponding function command configuration list are generated. For example, after the user sets the product type to DDR4, the seven mode registers MR0-MR6 can be configured separately according to the product specification corresponding to DDR4, and different function commands and parameters corresponding to the function commands can be configured.

It should be noted that, the test pattern is in error due to the error mode register or illegal function command, so that all simulation configuration tables of the circuit to be simulated are obtained according to the hierarchy and the sequence in the embodiment of the disclosure. In this way, in the process of setting the simulation configuration table, missed matching or mismatching can be effectively avoided, and the error rate is reduced; in addition, the simulation configuration tables are set one by one according to the hierarchy, so that all configuration information can be prevented from being traversed, and the efficiency of acquiring the simulation configuration tables is improved; therefore, the verification efficiency of the chip is improved. Meanwhile, the embodiment of the disclosure can provide an input end for setting the function command, and is more convenient for customizing products with specific function commands.

S103, generating a test code according to the test pattern conforming to the rule.

In the embodiment of the disclosure, whether the test pattern accords with the rule is checked according to a preset rule file; after the test pattern meets the rule, generating a test code according to the test pattern meeting the rule.

It should be noted that, the rule file is generated by the product specification, and the rule file may include rules such as a register rule and a function command configuration rule. For example, the rule file content may include: some function commands cannot occur after another function command; at a particular frequency, the partial mode register must be defined according to particular requirements.

That is, it is possible to determine whether the test pattern meets the product specification by checking whether the information such as the definition of the pattern register of the test pattern and the sequence of the function command meets the rule file, thereby ensuring the accuracy of the test pattern.

Further, if the test pattern does not accord with the rule, the simulation configuration information of the circuit to be simulated is obtained again, a simulation configuration table is set, and a new test pattern is generated until the new test pattern accords with the rule. Therefore, the generated test pattern is ensured to be in accordance with the product specification, and the correctness of the pattern is effectively ensured, so that the error rate is reduced, and the verification efficiency of the chip is improved.

In the embodiment of the disclosure, the test pattern needs to be converted into a code row which can be loaded by the Verilog simulation environment, so that the test pattern needs to be generated and applied to simulated test codes through an automatic script according to the code grammar and the corresponding rules. For example, the code grammar may be a System Verilog language, a C language, a Verilog language, etc., which is illustrated in this disclosure as an example. The corresponding rule refers to the corresponding relation between the function command and the code grammar in the simulation configuration table of the product. The corresponding relation between the function command and the System Verilog grammar can be defined according to different products, and the corresponding code template is determined; thus, with automation scripts, the function commands are replaced by lines of code, namely: and automatically generating a corresponding test code according to the test pattern of the product. Compared with the related art, the embodiment of the invention can automatically generate the test code, reduce the error rate, shorten the development time of simulation excitation and improve the verification efficiency of the chip.

S104, simulating the test code to obtain a corresponding simulation result.

In the embodiment of the disclosure, a standard Model (Golden Model) corresponding to a circuit to be simulated is determined; and according to the standard model, automatically establishing a simulation environment of the verification platform. For example, the verification platform automatically establishes a standard model corresponding to the test pattern according to the product type and the DRAM frequency, and generates a corresponding simulation environment. Compared with the related art, the method and the device have the advantages that the corresponding simulation environment can be automatically established, development time of simulation excitation is shortened, and verification efficiency of the chip is improved.

In the embodiment of the disclosure, a test code is loaded to a simulation environment to perform verilog simulation so as to obtain a corresponding simulation result. For example, using an EDA tool, verilog simulation is performed on test codes corresponding to test patterns, and then the generated simulation results and the test codes corresponding to the test patterns are transferred into a Waveform (Waveform) file.

S105, generating a simulation excitation file based on the simulation result.

In the embodiment of the disclosure, according to the composition mode of the product, a corresponding plurality of signals in the waveform file are exported to the CSV text, namely: based on the simulation results, an original excitation file is generated. For example, the raw stimulus file may be generated by exporting a portion of the signal in the waveform file through the command line interface simvisdbutil of the EDA tool Sim Vison. That is, based on the simulation configuration table, an original excitation file is generated from a partial waveform in the simulation result.

In the disclosed embodiment, a standard simulation stimulus file typically contains vector pattern definitions (Vector Pattern Definition), waveform parameter settings (Waveform Parameter Setting), and list Data (Tabular Data). The following description is given of an example of a simulated stimulus file intercepted:

；Vector Pattern Definition

Radix

1 1 4 4 4 4 1 4 4

nodename

clk out addr[15-0]R data[7:0]

io

i o i i i i x b b

；Waveform Parameter Setting

Slope 2.1

VIH 5

；Tabular Data

；pwl_type 0(or 1)

；Default is 0 1.0L H 1 1a e 1 0 0

In combination with the truncated simulation excitation file example, vector modes define vector names, vector sizes and vector types for defining signals; the vector type is used for defining the signal as an input signal or an output signal, and the vector size is used for defining the bit number of the signal. Waveform parameter settings are used to define various properties of the signal; for example, time units, rise and fall times, drive strength, logic high threshold or low threshold, and the like. The table data lists the input signals for a specified time. The specified time may be set in the first column of the cis sequence in accordance with the nodenam statement defined by the vector pattern, with the corresponding signal value following the specified time. When the signal toggles between 1 and 0, the FineSim Pro tool provides a pwl _type definition in the form of annotation characters, pwl _type definition preceding list data, in order to take into account rise and fall times.

In the disclosed embodiment, the original stimulus file derived from the waveform file is CSV text. The CSV text comprises a signal name and a data sequence; wherein the data sequence has only a sequence of values of 1 and 0, and a start time and an end time. Spice cannot identify the signal name and the data sequence in the CSV text; wherein the data sequence has only a sequence of values of 1 and 0, and a start time and an end time. Thus, the original stimulus file cannot be used for Spice simulation verification, and post-processing is necessary; for example, defining signals in a CSV text through vector mode definition to obtain a vector name, a vector size and a vector type corresponding to the signals; meanwhile, corresponding attributes are set for signals in the CSV text through waveform parameter setting, so that specific attributes such as time units, rising and falling time, driving strength and the like of the signals are obtained, namely: and performing operations of supplementary vector mode definition and waveform parameter setting on the original excitation file. Thus, a standard Spice simulation incentive file is obtained. That is, the original excitation file is post-processed to generate a standard Spice simulation excitation file.

It can be understood that the simulation configuration information of the circuit to be simulated and the simulation configuration table of the circuit to be simulated are obtained according to the hierarchy and the sequence; then, generating test patterns corresponding to the simulation configuration table and judging whether the test patterns accord with rules or not; and finally, generating test codes by utilizing the automatic script according with the rule, automatically generating a simulation environment to simulate the test codes, and generating a standard simulation excitation file based on related signal waveforms in a simulation result. Thus, compared with the related art, the embodiment of the invention effectively ensures the correctness of the test pattern and reduces the error rate; meanwhile, the test code and the simulation environment can be automatically generated, the development time of simulation excitation is shortened, and the verification efficiency of the chip is improved.

In some embodiments of the present disclosure, S103 shown in fig. 1 may be implemented by S201 to S202 shown in fig. 3, and each step will be described.

S201, checking whether the test pattern accords with the rule according to a preset rule file.

In the embodiment of the disclosure, when the user sets the simulation configuration information, a mismatch or mismatching problem may occur, and thus, the test pattern may have a problem. Therefore, it is necessary to check whether the test pattern meets the rule according to a preset rule file to generate an accurate test pattern.

S202, if the test pattern meets the rule, generating a test code based on the test pattern.

In the embodiment of the disclosure, the rule file may include rules such as a register rule and a function command configuration rule. The information such as the definition of the mode register of the test pattern and the sequence of the function command accords with the rule file, and then the test pattern can be judged to accord with the rule. Then, a corresponding test code is generated based on the test pattern, that is: and generating a test code according to the test pattern conforming to the rule. Compared with the related art, the embodiment of the invention effectively ensures the correctness of the test pattern, reduces the error rate and improves the verification efficiency of the chip.

In other embodiments of the present disclosure, S103 shown in fig. 1 may be implemented by S201 and S203 shown in fig. 3, and the steps will be described in connection.

S203, if the test pattern does not accord with the rule, the simulation configuration information of the circuit to be simulated is obtained again, a simulation configuration table is set, and a new test pattern is generated until the new test pattern accords with the rule.

In the embodiment of the disclosure, after the operation of checking whether the test pattern accords with the rule according to the preset rule file, if the test pattern does not accord with the rule, it is indicated that mismatch or mismatching occurs in the process of setting the simulation configuration information. Therefore, the simulation configuration information of the circuit to be simulated needs to be acquired again, and the simulation configuration table of the circuit to be simulated is set until the new test pattern accords with the rule.

In some embodiments of the present disclosure, the rule file includes: a mode register configuration rule and a function command configuration rule.

In the embodiment of the disclosure, the rule file includes specific rules such as a mode register configuration rule (Mode Register Setting Rule) and a function command configuration rule (Command Sequence Rule).

In some embodiments of the present disclosure, generating test code based on the test pattern further comprises: and generating test patterns by an automatic script according to the code grammar and the corresponding rules, and applying the test patterns to the simulated test codes.

In the embodiment of the disclosure, the corresponding relation between the function command and the System Verilog grammar can be defined according to products with different configuration information; thus, different code templates corresponding to different configuration information products are generated. In the process of generating test codes, the code templates can be utilized to replace corresponding functional commands with code lines loadable by a Verilog simulation environment through an automation script, so that test pattern generation is applied to the simulated test codes. Therefore, the test code can be automatically generated, the development time of simulation excitation is shortened, and the verification efficiency of the chip is improved.

In some embodiments of the present disclosure, S104 shown in fig. 1 may be implemented by S301 to S303 shown in fig. 4, and each step will be described.

S301, determining a standard model corresponding to a circuit to be simulated.

FIG. 5 is a schematic diagram of an alternative architecture of an apparatus for automatically generating simulated stimulus provided by an embodiment of the present disclosure, where the method for automatically generating simulated stimulus shown in FIG. 4 may be implemented using the apparatus for automatically generating simulated stimulus shown in FIG. 5.

In the embodiment of the present disclosure, referring to fig. 5, a standard Model (Golden Model) corresponding to a circuit to be simulated may be determined according to a simulation configuration table. For example, the verification platform automatically establishes a standard model corresponding to the test pattern according to the product type and the DRAM frequency.

S302, automatically establishing a simulation environment of the verification platform according to the standard model.

In the embodiment of the disclosure, the verification platform can automatically establish the Verilog simulation environment corresponding to the current test pattern according to the standard model. Compared with the related art, the method and the device have the advantages that the corresponding simulation environment can be automatically established, development time of simulation excitation is shortened, and verification efficiency of the chip is improved.

S303, loading the test code into a simulation environment to perform verilog simulation so as to obtain a corresponding simulation result.

In the embodiment of the disclosure, with continued reference to fig. 5, a test code is loaded into a simulation environment set up by a verification platform to perform verilog simulation, and the test code is correspondingly converted into an input signal waveform through the verification platform and is used as a part of a simulation result, so that a simulation excitation file of Spice is generated finally.

In the embodiment of the disclosure, the simulation excitation file also needs to include an idealized output signal waveform corresponding to the standard model, so that when the actual output signal waveform is obtained by executing the Spice simulation according to the simulation excitation file, the idealized output signal waveform is used as a reference to be compared with the actual output signal waveform of the Spice simulation, and a Spice simulation result is generated. Therefore, when generating a simulation result, the output signal waveform of the corresponding ideal model needs to be transferred; thus, a simulation result including the output waveform and the input waveform is generated.

In some embodiments of the present disclosure, the simulation results include: an input waveform and an output waveform; the input waveform corresponds to the input signal waveform corresponding to the test code; the output waveform is the output signal waveform after simulation is performed on the standard model.

In the embodiment of the disclosure, the simulation result includes: an input waveform and an output waveform. The test code is correspondingly converted into the input signal waveform through the verification platform. The idealized output signal waveform corresponding to the standard model can be used for comparison with the results of the Spice simulation, and thus the output signal waveform is also required as part of the simulated stimulus file.

In some embodiments of the present disclosure, after S301 to S303 are performed, S104 shown in fig. 1 may be further implemented through S304 to S305 shown in fig. 4, and each step will be described in connection with the description.

S304, acquiring a log file of the verilog simulation, and checking whether the verilog simulation is successful or not according to the log file.

In the embodiment of the disclosure, the steps of verilog simulation are recorded in the corresponding log files, so that the log files of the verilog simulation can be obtained, and whether the verilog simulation is successful or not can be checked according to the log files.

S305, if verilog simulation is successful, generating a simulation excitation file based on a simulation result.

In the embodiment of the disclosure, after the log file is acquired, whether the verilog simulation is successful is checked according to the log file. If the verilog simulation is successful, a simulation excitation file is generated based on the output simulation result.

S306, if the verilog simulation is unsuccessful, ending the current flow.

In other embodiments of the present disclosure, S104 shown in fig. 1 may be further implemented by S306 shown in fig. 4 after S301 to S304 are performed.

In the embodiment of the disclosure, after the log file of the verilog simulation is obtained, whether the verilog simulation is successful is checked according to the log file. If the verilog simulation is unsuccessful, ending the current flow. Therefore, the progress of verilog simulation can be known in time, so that the development time of simulation excitation can be shortened, and the verification efficiency of a chip can be improved.

In some embodiments of the present disclosure, S105 shown in fig. 1 may be implemented through S401 to S402 shown in fig. 6, and each step will be described.

S401, generating an original excitation file according to part of waveforms in a simulation result based on a simulation configuration table.

In the embodiment of the disclosure, according to the definition of the composition mode in the basic configuration table of the product, a corresponding plurality of signals in the input waveform and the output waveform are exported to the CSV text, namely: and generating an original excitation file according to the partial waveforms in the simulation result based on the simulation configuration table. For example, the original stimulus file may be generated by the EDA tool Sim Vison, described in connection with the code lines intercepted below:

simvisdbutil<waveform>

-range<start_time>:<stop_time>

-radix bin

-showx

-csv

-signal<signal_list>

-output stimulus_raw.csv

from the intercepted code line, the command line interface (corresponding to simvisdbutil) of the EDA tool Sim Vison derives part of the signal (corresponding to signal_list) in the waveform file (corresponding to waveform) to generate the original stimulus file (corresponding to stimulus_raw.

S402, performing post-processing on the original excitation file to generate a simulation excitation file.

In the embodiment of the disclosure, the original excitation file derived from the waveform file only contains list data, so the original excitation file cannot be used for Spice simulation verification, and therefore, vector mode definition and waveform parameter setting need to be supplemented in the original excitation file, namely: and carrying out post-processing on the original excitation file to generate a simulation excitation file.

In some embodiments of the present disclosure, post-processing an original stimulus file includes: the vector mode definition and waveform parameter settings are added to the original excitation file.

In the disclosed embodiments, the simulated stimulus file generally contains vector pattern definitions, waveform parameter settings, and list data. The original excitation file only contains list data, and supplementary vector mode definition and waveform parameter setting are required to be carried out on the original excitation file, so that the original excitation file is converted into a simulation excitation file.

In the disclosed embodiment, the waveform parameter setting can convert the numerical sequence (0 and 1 changes) in the CSV text into a continuously changing majority value waveform (which can be approximated as a continuously changing analog voltage waveform), namely: the digitally represented excitation file is converted to an excitation file of continuously varying representation. The vector mode definition enables all input signals to be partitioned by functional definition or type. Description is made with division by type: the delays of different types of inputs may differ and thus all input signals need to be divided by type using a vector pattern definition. For example, the input signal types include DQ0-DQ7, CA0-CA13, CS/CK, etc.

In some embodiments of the present disclosure, the product basic configuration information includes: product type, frequency, and composition pattern; the mode register configuration information includes: burst length, burst type, column address strobe delay, mode of operation, and write burst mode; the function command configuration information includes: read command, write command, activate command, bank address, row address, column address.

FIG. 7 is a schematic diagram of an alternative configuration of a simulation configuration interface of an apparatus for automatically generating a simulation stimulus provided by an embodiment of the present disclosure. In the disclosed embodiment, in conjunction with fig. 2 and 7, the circuit to be emulated may be a dynamic random access memory product. Accordingly, the product basic configuration information includes: product type, frequency, and composition pattern. The Mode register configuration information includes configuration information of a plurality of Mode registers, and the configuration information of each Mode register may include Burst Length (BL), burst Type (Burst Type), column address strobe delay (Column Address Strobe Latency, CL), operation Mode (Operating Mode), and write Burst Mode (Read Burst Mode); the function command configuration information may include a plurality of commands such as a Read command (Read), a Write command (Write), an activate command (actve), and the like, and parameters of each function command include information such as a Bank Group Address (BG), a Bank Address (BA), a Data Mask (DM), a Row Address (Row Address), a Column Address (Column Address), a Data I/O channel (DQ), and the like.

FIG. 8 is a schematic flow chart of an alternative method for automatically generating simulated stimulus provided by an embodiment of the present disclosure, in which, referring to FIG. 8, the method for automatically generating simulated stimulus includes:

s501, setting basic parameters of products.

In embodiments of the present disclosure, the article may be a dynamic random access memory. Accordingly, the basic parameters of the product may include: product type, frequency, and composition mode, etc. Setting basic parameters of the product to obtain basic configuration information of the product, and generating a corresponding basic configuration table of the product.

S502, configuring a mode register according to the product specification.

In the embodiment of the disclosure, the product specification is determined according to the basic configuration information of the product, so that the mode register is configured according to the product specification, and the mode register configuration table of the product is obtained.

S503, applying a function command sequence and parameters thereof.

In the embodiment of the disclosure, a function command configuration list of a product is obtained, function commands of different functions are applied to the product, and parameter configuration of each function command is set.

S504, checking the accuracy of the test pattern.

In the embodiment of the present disclosure, the definition of the test pattern in the steps S501 to S503 is obtained, that is: and obtaining a simulation configuration table of the product. Checking whether the test pattern is correct according to the rule file, namely: checking whether the test pattern conforms to the rule file.

S505, judging whether the test pattern is correct.

In the embodiment of the present disclosure, if the test pattern is correct, step S506 is performed. If the test pattern is incorrect, the process returns to step S502, namely: and re-acquiring simulation configuration information of the product, and setting a corresponding simulation configuration table.

S506, generating a test code.

In the disclosed embodiments, test code is generated using an automation script. The test code is typically a command line described in the System Verilog language.

S507, simulating and storing waveforms.

In the embodiment of the disclosure, according to the product type and the DRAM frequency, the verification environment of the Verilog simulation is automatically loaded, the test code generated in the step S506 is simulated through a standard model, and part of the input signal waveform and part of the output signal waveform are transferred into a waveform file.

S508, judging whether the simulation is successful.

In the embodiment of the disclosure, a log file of the Verilog simulation is called to check whether the Verilog simulation is successful. If the simulation is successful, entering into S509; if the simulation fails, reporting errors and ending the flow.

S509, generating an original excitation file.

In the embodiment of the disclosure, according to the composition mode, partial waveforms are derived from simulation results to CSV text, so that original excitation is obtained. For example, this can be achieved by means of the relevant interface of the EDA tool Sim Vision.

S510, post-processing and generating a simulation excitation file.

In the embodiment of the disclosure, an automation script is used to perform post-processing operation on an original excitation file, so as to convert the excitation file represented by a number into an excitation file represented by a continuous variable, namely: supplementing the vector mode definition and waveform parameter setting to an original excitation file by using an automation script; thus, a simulated stimulus file is generated.

The embodiment of the present disclosure further provides an apparatus 100 for automatically generating a simulated stimulus, referring to fig. 2, the apparatus 100 for automatically generating a simulated stimulus includes:

a simulation configuration interface configured to acquire simulation configuration information of a circuit to be simulated, set a simulation configuration table of the circuit to be simulated based on the simulation configuration information, and generate a test pattern based on the simulation configuration table; the simulation configuration information comprises: product basic configuration information, mode register configuration information, and function command configuration information.

A test code generation module configured to receive a test pattern conforming to a rule from the simulation configuration interface; and generating a test code according to the test pattern conforming to the rule.

A verification platform configured to receive test code from the test code generation module; and simulating the test code to obtain a corresponding simulation result.

The system comprises an excitation generation module, a verification platform and a simulation module, wherein the excitation generation module is configured to receive simulation results from the verification platform; and generating a simulation excitation file based on the simulation result.

In the embodiment of the disclosure, referring to fig. 7, a simulation configuration interface is provided with a plurality of input ends, and a user can set product basic configuration information, mode register configuration information and function command configuration information in the simulation configuration interface; thus, the user can select and determine the simulation configuration information of the product through the simulation configuration interface.

In the embodiment of the present disclosure, with continued reference to fig. 7, the information contained in the simulation configuration information has a hierarchy and a sequence. The user needs to select the product type first, and then, select the corresponding frequency from a plurality of frequencies determined by the product type, and select the corresponding composition mode from a plurality of composition modes determined by the product type, namely: and obtaining basic configuration information of the product. After the basic configuration information of the product is selected, other configurations such as a mode register, a function command and the like of the circuit to be simulated can be set according to the product specification corresponding to the basic configuration information of the product, namely: and acquiring the configuration information of the mode register and the configuration information of the function command of the product. For example, the product type is selected to be DDR4, the frequency is selected to be 3200MHz, and the composition mode is selected to be X8. After the user sets the product type to DDR4, the seven mode registers MR0-MR6 can be independently configured according to the product specification corresponding to DDR4, and different function commands and parameters corresponding to the function commands are configured. Parameters corresponding to a portion of the functional commands may be randomly generated, for example, data I/O channels (DQs) in the write commands may be randomly set using the emulation configuration interface.

Accordingly, the simulation configuration table also has a hierarchy and a precedence order. The product basic configuration table is at one level. The mode register configuration table and the function command configuration list are at one level and at a level next to the level at which the product base configuration table is located. After the corresponding product basic configuration table is generated, the corresponding mode register configuration table and function command configuration list can be generated.

That is, the simulation configuration interface provides a user interface that can be used to obtain simulation configuration information for the circuit to be simulated. Each piece of simulation configuration information has a hierarchy, and further, the simulation configuration table can be obtained according to the sequence. In this way, in the process of setting the simulation configuration table, missed matching or mismatching can be effectively avoided, and the error rate is reduced; in addition, the simulation configuration tables are set one by one according to the hierarchy, so that all configuration information can be prevented from being traversed, and the efficiency of acquiring the simulation configuration tables is improved; therefore, the verification efficiency of the chip is improved. Meanwhile, the embodiment of the disclosure can provide a port for setting the function command, and is more convenient for customizing a product with a specific function command.

In some embodiments of the present disclosure, the apparatus further comprises a checking module configured to check whether the test pattern meets the rule according to a preset rule file.

In an embodiment of the present disclosure, with continued reference to fig. 2, the apparatus 100 for automatically generating simulated stimulus further includes an inspection module. The checking module is configured to check whether the test pattern accords with the rule according to a preset rule file. Compared with the related art, the embodiment of the invention effectively ensures the correctness of the test pattern, reduces the error rate and improves the verification efficiency of the chip.

In some embodiments of the present disclosure, the simulation configuration interface is further configured to: and if the test pattern does not accord with the rule, re-acquiring simulation configuration information of the circuit to be simulated, setting a simulation configuration table, and generating a new test pattern until the new test pattern accords with the rule.

In some embodiments of the present disclosure, the test code generation module is further configured to: and generating test patterns by an automatic script according to the code grammar and the corresponding rules, and applying the test patterns to the simulated test codes.

In some embodiments of the present disclosure, the verification platform is further configured to: determining a standard model corresponding to a circuit to be simulated; according to the standard model, automatically establishing a simulation environment of the verification platform; and loading the test code into a simulation environment to perform verilog simulation so as to obtain a corresponding simulation result.

In some embodiments of the present disclosure, the verification platform is further configured to: obtaining a verilog simulation log, and checking whether the verilog simulation is successful or not according to a log file; if the verilog simulation is successful, generating a simulation excitation file based on a simulation result; if the verilog simulation is unsuccessful, ending the current flow.

In some embodiments of the present disclosure, the incentive generation module is further configured to: generating an original excitation file according to part of waveforms in a simulation result based on a simulation configuration table; and carrying out post-processing on the original excitation file to generate a simulation excitation file.

In some embodiments of the present disclosure, the incentive generation module is further configured to: the vector mode definition and waveform parameter settings are added to the original excitation file.

Fig. 9 is a schematic structural diagram of an alternative apparatus 100 for automatically generating a simulated stimulus according to an embodiment of the present application, and referring to fig. 9, hardware entities of the apparatus 100 for automatically generating a simulated stimulus include: a processor 101, a memory 102 and a communication interface 103. The processor 101 generally controls the overall operation of the apparatus 100 for automatically generating simulated stimuli. The communication interface 103 may enable the apparatus 100 for automatically generating simulated stimuli to communicate with other apparatuses or devices over a network. The memory 102 is configured to store instructions and applications executable by the processor 101, and may also cache data (e.g., image data, audio data, voice communication data, and video communication data) to be processed or processed by the various modules in the processor 101 and the apparatus 100 for automatically generating simulated stimuli, which may be implemented by FLASH memory (FLASH) or random access memory (Random Access Memory, RAM).

It should be noted that, in the embodiment of the present application, if the above-mentioned chip testing method is implemented in the form of a software functional module, and sold or used as a separate product, the chip testing method may also be stored in a computer readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present disclosure may be embodied essentially or in a part contributing to the related art in the form of a software product stored in a storage medium, including several instructions for causing the apparatus 100 (which may be a personal computer, a server, or a network device, etc.) for automatically generating simulation incentives to perform all or part of the methods described in the embodiments of the present disclosure. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read Only Memory (ROM), a magnetic disk, an optical disk, or other various media capable of storing program codes. Thus, embodiments of the present application are not limited to any specific combination of hardware and software.

The disclosed embodiments provide a storage medium having stored thereon a computer program which, when executed by a processor, implements steps in a method corresponding to the detection apparatus described above.

It should be noted that, in this document, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments. The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment. The features disclosed in the several product embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new product embodiments. The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.

The foregoing is merely specific embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it is intended to cover the scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims (15)

1. A method for automatically generating simulated stimuli comprising:

obtaining simulation configuration information of a circuit to be simulated, wherein the simulation configuration information comprises: product basic configuration information, mode register configuration information and function command configuration information;

setting a simulation configuration table of the circuit to be simulated based on the simulation configuration information, and generating a test pattern based on the simulation configuration table;

generating a test code according to the test pattern conforming to the rule;

simulating the test code to obtain a corresponding simulation result;

and generating a simulation excitation file based on the simulation result.

2. The method of claim 1, wherein generating the test code from the test pattern comprises:

checking whether the test pattern accords with a rule according to a preset rule file;

And if the test pattern meets the rule, generating the test code based on the test pattern.

3. The method of claim 2, wherein the step of determining the position of the substrate comprises,

after checking whether the test pattern accords with the rule according to the preset rule file, the method further comprises:

and if the test pattern does not accord with the rule, re-acquiring the simulation configuration information of the circuit to be simulated, setting the simulation configuration table, and generating a new test pattern until the new test pattern accords with the rule.

4. A method according to claim 2 or 3, wherein the rule file comprises: a mode register configuration rule and a function command configuration rule.

5. The method of claim 2, wherein the generating the test code based on the test pattern further comprises: and generating the test pattern into the test code applied to simulation through an automatic script according to the code grammar and the corresponding rule.

6. The method of claim 1, wherein simulating the test code to obtain the corresponding simulation result comprises:

determining a standard model corresponding to the circuit to be simulated;

According to the standard model, automatically establishing a simulation environment of the verification platform;

and loading the test code into the simulation environment to perform verilog simulation so as to obtain the corresponding simulation result.

7. The method of claim 6, wherein the simulation results comprise: an input waveform and an output waveform; wherein the input waveform corresponds to the corresponding input signal waveform in the test code; the output waveform is an output signal waveform after simulation is executed on the standard model.

8. The method of claim 7, wherein after loading the test code into the simulation environment for verilog simulation to obtain the corresponding simulation result, further comprising:

obtaining a log file of verilog simulation, and checking whether the verilog simulation is successful or not according to the log file;

if verilog simulation is successful, generating the simulation excitation file based on the simulation result;

if the verilog simulation is unsuccessful, ending the current flow.

9. The method of claim 1, wherein generating a simulated stimulus file based on the simulation results comprises:

generating an original excitation file according to part of waveforms in the simulation result based on the simulation configuration table;

And carrying out post-processing on the original excitation file to generate the simulation excitation file.

10. The method of claim 9, wherein post-processing the original stimulus file comprises:

adding vector mode definitions and waveform parameter settings to the original excitation file.

11. The method of claim 1, wherein the product basic configuration information comprises: product type, frequency, and composition pattern; the mode register configuration information includes: burst length, burst type, column address strobe delay, mode of operation, and write burst mode; the function command configuration information includes: read command, write command, activate command, bank address, row address, column address.

12. An apparatus for automatically generating simulated stimuli comprising:

a simulation configuration interface configured to acquire simulation configuration information of a circuit to be simulated, set a simulation configuration table of the circuit to be simulated based on the simulation configuration information, and generate a test pattern based on the simulation configuration table; the simulation configuration information comprises: product basic configuration information, mode register configuration information and function command configuration information;

A test code generation module configured to receive the test pattern conforming to a rule from the simulation configuration interface; generating test codes from the test patterns conforming to the rules;

a verification platform configured to receive the test code from the test code generation module; and simulating the test code to obtain a corresponding simulation result;

an excitation generation module configured to receive the simulation results from the verification platform; and generating a simulation excitation file based on the simulation result.

13. The apparatus of claim 12, further comprising a checking module configured to check whether the test pattern complies with a rule according to a preset rule file.

14. An apparatus for automatically generating simulated stimuli comprising:

a memory for storing executable instructions;

a processor for implementing the method of any one of claims 1 to 11 when executing executable instructions stored in said memory.

15. A storage medium having stored thereon executable instructions for causing a processor to perform the method of any one of claims 1 to 11.

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