CN117766618A - Luminous and high-performance photoelectric detection integrated double-gate device and manufacturing method thereof - Google Patents
Luminous and high-performance photoelectric detection integrated double-gate device and manufacturing method thereof Download PDFInfo
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Abstract
The invention discloses a double-gate device integrating light emission and high-performance photoelectric detection and a manufacturing method thereof, wherein the double-gate device comprises a photodiode, a first transistor and a second transistor, the photodiode comprises a sixth electrode, a first carrier transmission layer, a light emitting layer, a second carrier transmission layer and an eighth electrode which are arranged from top to bottom, the first transistor is positioned at one side below the photodiode, the second transistor is of a double-gate structure with a top gate, and the second transistor is positioned at the other side below the photodiode. In the invention, the first transistor in the double-gate device can drive the photodiode to emit light and is matched with the photodiode to realize photocurrent detection, and the second transistor can be matched with the photodiode to realize high-performance photovoltage detection, so that the light emitting diode and the photodetection diode are integrated into a single-chip device, and the electroluminescence is realized and the high-performance photodetection is realized. The embodiment is widely applied to the technical field of photoelectricity.
Description
Technical Field
The embodiment relates to the technical field of photoelectricity, in particular to a dual-gate device integrating light emission and high-performance photoelectric detection and a manufacturing method thereof.
Background
The photoelectric detection device and the light-emitting diode device have important application in national defense and people life, and meanwhile, the development is very rapid. With the continuous innovation and breakthrough of photoelectric materials and the continuous improvement of manufacturing processes, the performances of the photoelectric detector and the light-emitting diode are greatly improved. However, discrete individual photodetector devices and light emitting diode devices have failed to meet system requirements in many cases. There is a growing demand for photodetectors and light emitting diodes, which are desired to be integrated, miniaturized, and reduced in cost, etc.
The photodetectors currently in use are photodiodes, the simplified structure of which is shown in fig. 1: the main structure of the device is as follows: a top electrode, a hole transport layer, a photosensitive layer, an electron transport layer, and a bottom electrode. The working principle is as follows: the photosensitive layer absorbs photons transmitted through the transparent electrode and generates electron-hole pairs, the electron-hole pairs are separated under the action of a built-in electric field, and finally the electron-hole pairs are respectively transmitted to the electrodes at two sides under external reverse bias voltage to form current and photo-generated voltage.
The simplified architecture of the presently applied led is shown in fig. 2: the main structure of the device is as follows: a top electrode, a hole transport layer, a light emitting layer, an electron transport layer, and a bottom electrode. The working principle is as follows: and applying forward voltage on two sides of the electrode to enable electrons and holes to be injected from the electrode, pass through the transmission layer and finally enter the light-emitting layer to perform compound light emission.
For the photodiode, the photosensitive layer should have a certain thickness in order to sufficiently absorb incident light without affecting separation and transmission of photogenerated carriers; at the same time, the electron (hole) transport layer should be selected to have good energy level matching to facilitate extraction of electrons (holes). For light emitting diodes, the light emitting layer should be thin in order to ensure high light transmittance; at the same time, the electron (hole) transport layer should be selected to have a good energy level matching to facilitate electron (hole) injection. Therefore, the device structure and materials adopted by the general photoelectric detection diode are unfavorable for realizing electroluminescence, and the device structure and materials adopted by the light-emitting diode are also unfavorable for photoelectric detection, so that the contradiction is unfavorable for realizing the function requirement of the photoelectric detection and electroluminescence integration.
Disclosure of Invention
Aiming at the technical problem that the high-efficiency photoelectric detection and electroluminescence integrated device is difficult to realize at present, the embodiment aims to provide a double-gate device integrating light emission and high-performance photoelectric detection and a manufacturing method thereof.
On one hand, the embodiment of the invention comprises a double-grid device integrating light emission and high-performance photoelectric detection,
a photodiode; the photodiode comprises a sixth electrode, a first carrier transmission layer, a light emitting layer, a second carrier transmission layer and an eighth electrode which are arranged from top to bottom; wherein the sixth electrode is a transparent electrode, and the eighth electrode is a bottom electrode of the photodiode;
a first transistor; the first transistor is positioned on one side below the photodiode, and the drain electrode of the first transistor is connected with the eighth electrode;
a second transistor; the second transistor is of a double-gate structure with a top gate, the second transistor is located on the other side below the photodiode, and the top gate of the second transistor is connected with the eighth electrode.
Further, the first transistor includes:
a first dielectric layer; the first dielectric layer is positioned below the eighth electrode and connected with the eighth electrode;
a first semiconductor layer, a third electrode, and a seventh electrode; the first semiconductor layer, the third electrode and the seventh electrode are all positioned in the first dielectric layer, the third electrode is connected with one end of the first semiconductor layer, and the seventh electrode is respectively connected with the other end of the first semiconductor layer and the eighth electrode;
a second dielectric layer; the second dielectric layer is positioned below the first dielectric layer and connected with the first dielectric layer;
a first electrode; the first electrode is positioned in the second dielectric layer and below the first semiconductor layer
The first electrode is used as a grid electrode of the first transistor, the third electrode is used as a source electrode of the first transistor, and the seventh electrode is used as a drain electrode of the first transistor.
Further, the second transistor includes:
a first dielectric layer; the first dielectric layer is positioned below the eighth electrode and connected with the eighth electrode;
a second semiconductor layer, a fourth electrode, and a fifth electrode; the second semiconductor layer, the fourth electrode and the fifth electrode are all positioned in the first dielectric layer, the fifth electrode is connected with one end of the second semiconductor layer, and the fourth electrode is connected with the other end of the second semiconductor layer;
a top gate electrode; the top gate electrodes are all positioned in the first dielectric layer, and the top gate electrodes are positioned above the second semiconductor layer;
a second dielectric layer; the second dielectric layer is positioned below the first dielectric layer and connected with the first dielectric layer;
a second electrode; the second electrode is positioned in the second dielectric layer, and the second electrode is positioned below the second semiconductor layer;
the second electrode is used as a grid electrode of the second transistor, the fifth electrode is used as a source electrode of the second transistor, and the fourth electrode is used as a drain electrode of the second transistor.
Further, the dual gate device further includes:
a buffer layer; the buffer layer is positioned below the second dielectric layer and connected with the second dielectric layer.
Further, the dual gate device further includes:
a transparent substrate; the transparent substrate is positioned below the buffer layer and connected with the buffer layer.
Further, the first carrier transport layer is an electron transport layer, and the second carrier transport layer is a hole transport layer; or alternatively
The first carrier transport layer is a hole transport layer, and the second carrier transport layer is an electron transport layer.
Further, the sixth electrode is made of LiF/Al or Au, and the light-emitting layer is made of 45% PEOxA:CsPbBr 0.6 I 2.4 The eighth electrode is made of ITO, the first carrier transmission layer is made of TPBi, the second carrier transmission layer is made of Poly-TPD, or the first carrier transmission layer is made of Poly-TPD, and the second carrier transmission layer is made of TPBi.
Further, the materials of the first dielectric layer and the second dielectric layer are high dielectric constant oxides, the materials of the first electrode, the second electrode, the third electrode, the fourth electrode, the fifth electrode and the top gate electrode are Mo, and the materials of the first semiconductor layer and the second semiconductor layer are IGZO or poly-Si.
Further, the buffer layer is made of SiO 2 The transparent substrate is made of glass.
On the other hand, the embodiment of the invention also comprises a manufacturing method of the double-gate device integrating light emission and high-performance photoelectric detection, and the manufacturing method comprises the following steps:
obtaining a transparent substrate, sequentially carrying out ultrasonic cleaning on the transparent substrate by using a cleaning agent, then placing the transparent substrate in an oven for drying, and cleaning the transparent substrate by using a plasma surface cleaning instrument;
depositing a buffer layer over the transparent substrate by plasma enhanced chemical vapor deposition;
performing photoetching patterning on the buffer layer, and depositing a layer of electrode serving as a grid electrode of the first transistor and a grid electrode of the second transistor in a thermal evaporation mode;
depositing a second dielectric layer on the buffer layer by using a plasma enhanced chemical vapor deposition method, and flattening the second dielectric layer;
depositing a first semiconductor layer and a second semiconductor layer on the second dielectric layer by magnetron sputtering, patterning by photoetching, and carrying out wet etching by using hydrochloric acid;
annealing the device obtained in the steps;
performing photoetching patterning on the second dielectric layer, and depositing a layer of electrode serving as a source electrode and a drain electrode of the first transistor and a source electrode and a drain electrode of the second transistor respectively by using a thermal evaporation mode;
depositing a first dielectric layer on the second dielectric layer by using a plasma enhanced chemical vapor deposition method, and flattening the first dielectric layer;
performing photoetching patterning on the first dielectric layer, and depositing a layer of electrode serving as a top gate electrode of the second transistor in a thermal evaporation mode;
continuing to deposit the second dielectric layer by using a plasma enhanced chemical vapor deposition method, and flattening the second dielectric layer;
manufacturing through holes at the drain electrode of the first transistor and the top gate electrode of the second transistor, and depositing a bottom electrode of the photodiode in a magnetron sputtering mode;
spin-coating a second carrier transport layer of the photodiode on the bottom electrode, and then annealing;
spin-coating a light-emitting layer of the photodiode on the second carrier transport layer, and then annealing;
and depositing a first carrier transmission layer and a transparent electrode of the photodiode on the light-emitting layer in sequence by using a thermal evaporation mode.
The beneficial effects in this embodiment are: in the embodiment, the light-emitting and high-performance photoelectric detection integrated double-gate device is characterized in that the first transistor can drive the photodiode to emit light and is matched with the photodiode to realize photoelectric current detection, and the second transistor can be matched with the photodiode to realize high-performance photoelectric voltage detection, so that the light-emitting diode and the photoelectric detection diode are integrated into a single-chip device, and the electroluminescence is realized and the high-performance photoelectric detection is realized.
Drawings
FIG. 1 is a schematic diagram of a photodetector currently in use;
FIG. 2 is a schematic diagram of a light emitting diode in use;
fig. 3 is a schematic structural diagram of a dual gate device in an embodiment;
fig. 4 is a schematic diagram of a dual gate device in an embodiment;
fig. 5 is a schematic diagram of the working principle of the dual-gate device in the light emitting mode in the embodiment;
fig. 6 is a schematic diagram of the working principle of the dual-gate device in the photocurrent detection mode in the embodiment;
fig. 7 is a schematic diagram of the working principle of the dual-gate device in the photovoltage floating gate detection mode when the second transistor is N-type in the embodiment;
fig. 8 is a schematic diagram of the working principle of the dual-gate device in the photovoltage floating gate detection mode when the second transistor is P-type in the embodiment;
FIG. 9 is a schematic diagram of a dual gate device fabricated using a combination of materials in an embodiment;
fig. 10 is a schematic diagram of a dual gate device fabricated using another material combination in an embodiment.
Detailed Description
In this embodiment, a dual-gate device integrating light emission and high-performance photoelectric detection is provided. The structure of the dual gate device is shown in fig. 3. Referring to fig. 3, in describing the structure of the dual-gate device, the positional relationships between the different components in the dual-gate device are indicated by terms such as "upper", "lower", "left" and "right", which are relative, for example, when the dual-gate device is placed as shown in fig. 1, the first dielectric layer is located above the second dielectric layer, and these terms do not limit the absolute positions of the components in the dual-gate device, for example, when the dual-gate device is actually used, the dual-gate device may be placed in different orientations, so that the terms such as "upper", "lower", "left" and "right" in this embodiment also change accordingly, but it may still be assumed that the relative positional relationships between the different components in the dual-gate device are described by terms such as "upper", "lower", "left" and "right" when the dual-gate device is placed as shown in fig. 3.
Referring to fig. 3, the dual gate device includes a sixth electrode 6, a first carrier transport layer, a light emitting layer, a second carrier transport layer, an eighth electrode 8, a first dielectric layer, a second dielectric layer, a first electrode 1, a second electrode 2, a third electrode 3, a fourth electrode 4, a fifth electrode 5, a top gate electrode, a first semiconductor layer, a second semiconductor layer, and the like.
Referring to fig. 3, the sixth electrode 6, the first carrier transport layer, the light emitting layer, the second carrier transport layer, the eighth electrode 8, the first dielectric layer and the second dielectric layer are sequentially arranged in the order from top to bottom, and adjacent two layers are connected to each other.
Referring to fig. 3, the third electrode 3, the first semiconductor layer, the seventh electrode 7, the fifth electrode 5, the second semiconductor layer, the fourth electrode 4 and the top gate electrode are all located in the first dielectric layer, and the third electrode 3 is connected to one end of the first semiconductor layer, the seventh electrode 7 is connected to the other end of the first semiconductor layer, and the seventh electrode 7 is also connected to the eighth electrode 8; the fifth electrode 5 is connected to one end of the second semiconductor layer, the fourth electrode 4 is connected to the other end of the second semiconductor layer, and the top gate electrode is connected not to the second semiconductor layer but to the eighth electrode 8.
Referring to fig. 3, both the first electrode 1 and the second electrode 2 are located in the second dielectric layer, and the first electrode 1 is not connected to the first semiconductor layer, and the second electrode 2 is not connected to the second semiconductor layer.
In this embodiment, one of the first carrier transport layer and the second carrier transport layer is an electron transport layer, and the other is a hole transport layer. That is, one of the following two cases: the first carrier transport layer is an electron transport layer, and the second carrier transport layer is a hole transport layer; alternatively, the first carrier transport layer is a hole transport layer and the second carrier transport layer is an electron transport layer.
Referring to fig. 4, the sixth electrode 6, the first carrier transport layer, the light emitting layer, the second carrier transport layer, and the eighth electrode 8 constitute a photodiode. The sixth electrode 6 is a transparent electrode, and the eighth electrode 8 is a bottom electrode of the photodiode. The light emitting layer in the photodiode is capable of recombining electrons and holes from the sixth electrode 6 and the eighth electrode 8, respectively, so as to emit light, and the emitted photons can be emitted outwards through the sixth electrode 6, i.e., the transparent electrode; the first carrier transport layer and the second carrier transport layer in the photodiode can receive photons emitted from the outside from the sixth electrode 6, that is, the transparent electrode, and act to generate electrons and holes, thereby generating an electric field between the sixth electrode 6 and the eighth electrode 8, and realizing photoelectric conversion. Therefore, the photodiode composed of the sixth electrode 6, the first carrier transport layer, the light emitting layer, the second carrier transport layer, and the eighth electrode 8 has both functions of electroluminescence and photodetection.
Referring to fig. 4, the left-hand portion of the photodiode, i.e., the left-hand portion of the first dielectric layer, the left-hand portion of the second dielectric layer, and the first semiconductor layer, the first electrode 1, the third electrode 3, and the seventh electrode 7 thereof constitute a first transistor, wherein the first electrode 1 serves as the gate electrode of the first transistor, the third electrode 3 serves as the source electrode (which may also be regarded as the drain electrode) of the first transistor, and the seventh electrode 7 serves as the drain electrode (which may also be regarded as the source electrode) of the first transistor.
Referring to fig. 4, the right-side portion of the photodiode, that is, the right-side portion of the first dielectric layer, the right-side portion of the second dielectric layer, and the second semiconductor layer, the second electrode 2, the fourth electrode 4, the fifth electrode 5, and the top gate electrode thereof constitute a second transistor, wherein the second electrode 2 serves as a gate electrode of the second transistor, the fifth electrode 5 serves as a source electrode of the second transistor (may also be regarded as a drain electrode of the second transistor), and the fourth electrode 4 serves as a drain electrode of the second transistor (may also be regarded as a source electrode of the second transistor). The top gate electrode is located above the second semiconductor layer and can also function similarly to the second electrode 2 (gate electrode) located below the second semiconductor layer, and thus the second transistor is a double gate structure.
In this embodiment, referring to fig. 3 or fig. 4, a buffer layer and a transparent substrate are further provided in the dual-gate device, where the buffer layer is located below the second dielectric layer and connected to the second dielectric layer, and the transparent substrate is located below the buffer layer and connected to the buffer layer. The transparent substrate can provide a base and a protection function for other components of the double-gate device, and the buffer layer can play a role in buffering between the transparent substrate and the other components of the double-gate device.
In this embodiment, the working principle of the dual-gate device is as follows: the first transistor can drive the photodiode to emit light and is matched with the photodiode to realize photocurrent detection, and the second transistor can be matched with the photodiode to realize high-performance photovoltage detection, so that the light emitting diode and the photodiode are integrated into a single-chip device, and the electroluminescence is realized and the high-performance photoelectric detection is realized.
In this embodiment, according to the bias voltage applied by the relevant electrode in the dual-gate device and whether light from the outside is incident into the dual-gate device through the transparent electrode, the dual-gate device can operate in different operation modes such as a light emitting mode, a photocurrent detection mode, and a photovoltage detection mode, and the principles of each operation mode are shown in fig. 5, 6, 7, and 8, respectively.
1. Light emitting mode
As shown in fig. 5, if the first transistor is N-type (i.e., electrons are used as carriers), then a positive bias voltage can be applied to the first electrode 1 and the third electrode 3, and a voltage V can be applied to the sixth electrode 6 (transparent electrode of the photodiode) 6 =0v. At this time, the first transistor is in a conducting state, the photodiode is in a forward bias state, holes and electrons are respectively injected into the light-emitting layer from the eighth electrode 8 (the bottom electrode of the photodiode) and the sixth electrode 6 (the transparent electrode of the photodiode) to perform compound light emission, photons generated by the compound light emission are emitted from the transparent electrode, and at this time, the whole double-gate device is in a light-emitting mode; if the first transistor is P-type (i.e. holes are used as carriers), then a negative bias can be applied to the first electrode 1, a positive bias can be applied to the third electrode 3, and a voltage V can be applied to the sixth electrode 6 (transparent electrode of the photodiode) 6 =0v, the dual gate device can also be put in a light emitting mode.
2. Photocurrent detection mode
As shown in fig. 6, if the first transistor is of N-type, a positive bias may be applied to the first electrode 1, a negative bias may be applied to the third electrode 3, and a positive bias may be applied to the sixth electrode 6 (transparent electrode of the photodiode). At this time, the photodiode is in a reverse bias state, and the first transistor is in an off state. When the photodiode is irradiated by an external light source, electron-hole pairs are generated by the light emitting layer, and electrons and holes respectively flow to the sixth electrode 6 (a transparent electrode of the photodiode) and the eighth electrode 8 (a bottom electrode of the photodiode) under the action of reverse bias voltage, so that photocurrent detection is realized, and at the moment, the whole double-gate device is in a photocurrent detection mode. If the first transistor is P-type, the double gate device can be placed in the photocurrent detection mode by applying a negative bias to the first electrode 1, a negative bias to the third electrode 3, and a positive bias to the sixth electrode 6 (transparent electrode of the photodiode).
3. Photovoltage floating gate detection mode
As shown in fig. 7, if the second transistor is N-type (the first carrier transport layer in the photodiode is an electron transport layer and the second carrier transport layer is a hole transport layer), a positive bias voltage may be applied to the second electrode 2, a certain voltage difference may be applied to the fourth electrode 4 and the fifth electrode 5 (the source of the second transistor), and a positive bias voltage may be applied to the sixth electrode 6 (the transparent electrode of the photodiode). When an external light source penetrates through the transparent substrate and enters the double-gate device, photons enter the photodiode, the potential of a top gate electrode in the second transistor is changed by the photovoltage generated by the photodiode (between the first carrier transmission layer and the second carrier transmission layer), the current of the second semiconductor layer in the second transistor is regulated and controlled, so that detection is realized by converting the photovoltage floating gate effect into photocurrent, and at the moment, the whole double-gate device is in a photovoltage floating gate detection mode.
As shown in fig. 8, if the second transistor is P-type (the direction of the photodiode is opposite to that of the case when the second transistor is N-type, that is, the first carrier transport layer in the photodiode is a hole transport layer and the second carrier transport layer is an electron transport layer at this time), then a negative bias voltage may be applied to the second electrode 2, a certain voltage difference may be applied to the fourth electrode 4 and the fifth electrode 5, a negative bias voltage may be applied to the sixth electrode 6 (the transparent electrode of the photodiode), and similar to the principle of fig. 7, when an external light source penetrates the transparent substrate to inject into the dual-gate device, a photon enters the photodiode, the generated photo voltage of the photodiode (between the first carrier transport layer and the second carrier transport layer) will change the potential of the top gate electrode in the second transistor, and regulate the current magnitude of the second semiconductor layer in the second transistor, so that detection is achieved by converting the photo voltage floating gate effect into a floating gate, at this time, the whole dual-gate device is in a photo voltage detection mode.
In summary, the dual-gate device in this embodiment can not only drive the light emitting diode to emit light in the light emitting mode, but also be used as a photo-detection diode to perform photo-current detection in the photo-current detection mode or to perform photo-voltage detection in the photo-voltage floating gate detection mode.
Compared with a single photodiode and a light emitting diode device, the dual-gate device integrating light emission and high-performance photoelectric detection in the embodiment has the following advantages:
1. has photoelectric detection and electroluminescence functions. Electroluminescence is performed in a light emission mode, and photoelectric detection is performed in a photocurrent detection mode and a photovoltage floating gate detection mode.
2. In the photovoltage detection mode, the second transistor has an amplifying function of an extremely high photovoltaic signal by using a double-gate structure, and the amplifying effect can be adjusted by adjusting the bottom gate voltage.
In this embodiment, an ultrathin metal film, a patterned metal film, a metal nanowire, a metal oxide, or the like may be used as the sixth electrode 6 (transparent electrode of the photodiode). The transparent electrode can be formed into a film by spin coating, knife coating, drop coating, spray coating, vapor deposition, ink jet printing, roll-to-roll printing, or the like. The transparent electrode is mainly characterized by high transmittance and low resistivity. The high transmittance enables light to pass through the electrode material without being blocked or reflected, and meanwhile, the low resistivity ensures that current can smoothly pass through the electrode material, thereby reducing energy loss and heating, improving the performance and service life of the electronic device. For example, the sixth electrode 6 may be LiF/Al or Au, and the eighth electrode 8 may be ITO.
In this embodiment, a conductive organic polymer and a conductive small organic molecule (a polymer material having a hole transporting function, generally having a linear or planar large conjugated system, commonly such as PEDOT: PSS, poly-TPD, PVK, etc.), a metal oxide, an inorganic semiconductor material, or the like may be used as the hole transporting layer (depending on the direction of the photodiode, specifically, the first carrier transporting layer or the second carrier transporting layer). The hole transport layer can be formed by spin coating, knife coating, drop coating, spray coating, vapor deposition, ink jet printing, roll-to-roll printing, or the like. For example, when the first carrier transport layer is a hole transport layer, the material of the first carrier transport layer may be Poly-TPD; when the second carrier transport layer is a hole transport layer, the material of the second carrier transport layer may be Poly-TPD.
In this embodiment, an organic light-emitting material, a quantum dot and a nanocrystalline material, an inorganic light-emitting material, an organic-inorganic hybrid material, or the like may be used as the light-emitting layer in the photodiode. The luminescent layer can be formed by spin coating, knife coating, drop coating, spray coating, vapor deposition, ink jet printing, roll-to-roll printing, or the like. For example, the material of the light emitting layer may be 45% PEOxA:CsPbBr 0.6 I 2.4 。
In this embodiment, a conductive organic polymer and a conductive small organic molecule (a polymer material having an electron transport function, generally having a linear or planar large conjugated system, such as TPBi, PCBM, BCP, which is common), a metal oxide, an inorganic semiconductor material, or the like may be used as the electron transport layer (specifically, the first carrier transport layer or the second carrier transport layer depending on the direction of the photodiode). The electron transport layer can be formed into a film by spin coating, knife coating, drop coating, spray coating, vapor deposition, ink jet printing, roll-to-roll printing, or the like. For example, when the first carrier transport layer is an electron transport layer, the material of the first carrier transport layer may be TPBi; when the second carrier transport layer is an electron transport layer, the material of the second carrier transport layer may be TPBi.
In this embodiment, the transparent substrate is a transparent non-conductive substrate, and may be a rigid inorganic substrate or a flexible organic substrate. For example, the transparent substrate may be made of glass.
In this embodiment, the first electrode 1, the second electrode 2, the third electrode 3, the fourth electrode 4, the fifth electrode 5, the top gate electrode, and the like are used as electrodes of source, drain, and gate electrodes, and may be made of an inorganic semiconductor material such as metal, metal oxide, silicon, or iii-v compound, and may be formed into a film by vapor deposition, sputtering, or the like. For example, the materials of the first electrode 1, the second electrode 2, the third electrode 3, the fourth electrode 4, the fifth electrode 5, and the top gate electrode may be Mo.
In this embodiment, the buffer layer, the first dielectric layer, and the second dielectric layer may be formed using a material such as an organic polymer, a metal oxide, or a non-metal oxide. Film formation may be by spin coating, knife coating, drop coating, spray coating, sputtering, CVD, ALD, evaporation, ink jet printing, or roll-to-roll printing. For example, the buffer layer, the first dielectric layer and the second dielectric layer may all be made of high dielectric constant oxide, wherein the high dielectric constant oxide may be SiO 2 Or Al 2 O 3 Etc.
In this embodiment, as the first semiconductor layer and the second semiconductor layer, a material such as an inorganic semiconductor, an organic semiconductor, or an organic-inorganic hybrid semiconductor can be used. The first semiconductor layer and the second semiconductor layer may be formed by spin coating, knife coating, drop coating, spray coating, sputtering, CVD, ALD, mechanical lift-off and transfer, evaporation, ink jet printing, roll-to-roll printing, or the like. For example, the first semiconductor layer and the second semiconductor layer may be made of IGZO or poly-Si.
In this embodiment, a dual-gate device integrating light emission and high-performance photoelectric detection can be manufactured by:
s1, acquiring a transparent substrate, sequentially carrying out ultrasonic cleaning on the transparent substrate by using a cleaning agent, then placing the transparent substrate in an oven for drying, and cleaning the transparent substrate by using a plasma surface cleaning instrument;
s2, depositing a buffer layer above the transparent substrate by utilizing a plasma enhanced chemical vapor deposition method;
s3, photoetching and patterning are carried out on the buffer layer, and a layer of electrode is deposited in a thermal evaporation mode and used as a grid electrode of the first transistor and a grid electrode of the second transistor;
s4, depositing a second dielectric layer on the buffer layer by utilizing a plasma enhanced chemical vapor deposition method, and flattening the second dielectric layer;
s5, depositing a first semiconductor layer and a second semiconductor layer on the second dielectric layer through magnetron sputtering, patterning through photoetching, and carrying out wet etching by using hydrochloric acid;
s6, annealing the device obtained in the steps;
s7, photoetching and patterning are carried out on the second dielectric layer, and a layer of electrode is deposited in a thermal evaporation mode and is respectively used as a source electrode and a drain electrode of the first transistor and a source electrode and a drain electrode of the second transistor;
s8, depositing a second dielectric layer on the second dielectric layer by utilizing a plasma enhanced chemical vapor deposition method, and flattening the second dielectric layer;
s9, photoetching and patterning are carried out on the first dielectric layer, and a layer of electrode is deposited in a thermal evaporation mode and used as a top gate electrode of the second transistor;
s10, continuing to deposit the second dielectric layer by using a plasma enhanced chemical vapor deposition method, and flattening the second dielectric layer;
s11, manufacturing through holes at the drain electrode of the first transistor and the top gate electrode of the second transistor, and depositing the bottom electrode of the photodiode in a magnetron sputtering mode;
s12, spin-coating a second carrier transmission layer of the photodiode on the bottom electrode, and then annealing;
s13, spin-coating a light-emitting layer of the photodiode on the second carrier transmission layer, and then annealing;
s14, depositing a first carrier transmission layer and a transparent electrode of the photodiode on the light-emitting layer in a thermal evaporation mode in sequence.
In this embodiment, the materials used for the components in the dual gate device may be as shown in fig. 9 or fig. 10.
In FIG. 9, the semiconductor layer is IGZO, the source and drain electrodes and gate electrode of the transistor are Mo, and the buffer layer and dielectric layer are SiO 2 The bottom electrode of the top light-emitting diode is ITO, the hole transport layer is Poly-TPD, and the light-emitting layer is 45% PEOXA:CsPbBr 0.6 I 2.4 The electron transport layer is TPBi and the transparent electrode is LiF/Al. When the dual gate device shown in fig. 9 is to be fabricated, the following steps may be performed:
and 1A, ultrasonically cleaning a glass substrate by using isopropanol, a detergent, deionized water and isopropanol in sequence, and then placing the glass substrate in an oven to be dried. Before use, the glass substrate was cleaned in a plasma surface cleaner for 5 minutes.
2A, depositing SiO by utilizing a plasma enhanced chemical vapor deposition method at 180 DEG C 2 As a buffer layer.
And 3A, performing photoetching patterning on the substrate, and depositing a layer of 60nm Mo electrode serving as a grid electrode of the bottom transistor in a thermal evaporation mode.
4A, depositing SiO by utilizing a plasma enhanced chemical vapor deposition method at 180 DEG C 2 As a dielectric oxide layer, and is planarized.
And 5A, continuing to deposit the IGZO of 40nm on the substrate by magnetron sputtering. The sputtering gas being O 2 And carrying out wet etching on Ar and hydrochloric acid through photoetching patterning.
The device was annealed at 350 ℃ for 1.5 hours.
And 7A, performing photoetching patterning on the substrate, and depositing a layer of 60nm Mo electrode serving as a source electrode and a drain electrode of the transistor by using a thermal evaporation mode.
8A, depositing SiO by utilizing a plasma enhanced chemical vapor deposition method at 180 DEG C 2 As a dielectric oxide layer, and is planarized.
And 9A, carrying out photoetching patterning on the substrate, and depositing a layer of 60nm Mo electrode serving as a top gate electrode of the right transistor in a thermal evaporation mode.
10A deposition of SiO by plasma enhanced chemical vapor deposition at 180deg.C 2 As a dielectric oxide layer, and is planarized.
And 11A, manufacturing through holes at the drain electrode of the left transistor and the top gate electrode of the right transistor, and depositing a layer of ITO with the thickness of 50nm by using a magnetron sputtering mode as the bottom electrode of the light-emitting diode.
Poly-TPD was obtained by spin-coating a solution of Poly-TPD (8 mg/mL, dissolved in chlorobenzene) on bottom electrode ITO at 2000rpm for 30 seconds, followed by annealing at 100deg.C in a nitrogen-protected glove box for 15 minutes.
And 13A, continuously spin-coating a light-emitting layer on the prepared substrate. Red perovskite layer solution was prepared by dissolving 0.25M (Pb-based 2+ ) 45% PEOxA in DMSO: csPbBr 0.6 I 2.4 Solution (45% peoxa=mpeoxa/mpspbbr) 0.6 I 2.4 ) Spin coating. Spin coating conditions were 6000rpm for 30 seconds followed by annealing at 150℃for 30 minutes.
TPBi (35 nm), liF/Al (1 nm/20 nm) is deposited on the substrate by thermal evaporation in sequence.
In FIG. 10, the semiconductor layer is poly-Si, the source and drain electrodes and gate electrode of the transistor are Mo, and the buffer layer and dielectric layer are SiO 2 The bottom electrode of the top light-emitting diode is ITO, the hole transport layer is Poly-TPD, and the light-emitting layer is 45% PEOXA:CsPbBr 0.6 I 2.4 The electron transport layer is TPBi and the transparent electrode is Au. When the dual gate device shown in fig. 10 is to be fabricated, the following steps may be performed:
and 1B, ultrasonically cleaning the glass substrate by using isopropanol, a detergent, deionized water and isopropanol in sequence, and then placing the glass substrate in an oven to be dried. Before use, the glass substrate was cleaned in a plasma surface cleaner for 5 minutes.
2B, depositing SiO by utilizing a plasma enhanced chemical vapor deposition method at 180 DEG C 2 As a buffer layer.
And 3B, performing photoetching patterning on the substrate, and depositing a layer of 60nm Mo electrode serving as a grid electrode of the bottom transistor in a thermal evaporation mode.
4B, depositing SiO by utilizing a plasma enhanced chemical vapor deposition method at 180 DEG C 2 As a dielectric oxide layer, and is planarized.
And 5B, depositing 45nm amorphous silicon, performing dehydrogenation annealing at 450 ℃, and performing excimer laser annealing to form polycrystalline silicon serving as an active layer. And performing wet etching by using hydrofluoric acid through photoetching patterning.
And 6B, performing photoetching patterning on the substrate, and depositing a layer of 60nm Mo electrode serving as a source electrode and a drain electrode of the transistor by using a thermal evaporation mode.
7B, depositing SiO by utilizing a plasma enhanced chemical vapor deposition method at 180 DEG C 2 As a dielectric oxide layer, and is planarized.
And 8B, performing photoetching patterning on the substrate, and depositing a layer of 60nm Mo electrode serving as the top gate of the right transistor in a thermal evaporation mode.
9B, depositing SiO by utilizing a plasma enhanced chemical vapor deposition method at 180 DEG C 2 As a dielectric oxide layer, and is planarized.
And 10B, manufacturing through holes at the drain electrode of the left transistor and the top gate electrode of the right transistor, and depositing a layer of ITO with the thickness of 50nm by using a magnetron sputtering mode as the bottom electrode of the light-emitting diode.
And 11B, depositing TPBi (35 nm) on the substrate by thermal evaporation.
And 12B, continuously spin-coating a light-emitting layer on the prepared substrate. Red perovskite layer solution was prepared by dissolving 0.25M (Pb-based 2+ ) 45% PEOxA in DMSO: csPbBr 0.6 I 2.4 Solution (45% peoxa=mpeoxa/mpspbbr) 0.6 I 2.4 ) Spin coating. Spin coating conditions were 6000rpm for 30 seconds followed by annealing at 150℃for 30 minutes.
Poly-TPD was obtained by spin coating a solution of Poly-TPD (8 mg/mL, dissolved in chlorobenzene) on the luminescent layer at 2000rpm for 30 seconds, followed by annealing at 100deg.C in a nitrogen-protected glove box for 15 minutes.
14B. Deposition of the top electrode Au (20 nm) by thermal evaporation.
By executing steps S1 to S14, a dual-gate device integrating light emission and high-performance photoelectric detection in this embodiment can be manufactured, thereby realizing high-performance photoelectric detection while realizing electroluminescence.
It should be noted that, unless otherwise specified, when a feature is referred to as being "fixed" or "connected" to another feature, it may be directly or indirectly fixed or connected to the other feature. Further, the descriptions of the upper, lower, left, right, etc. used in this disclosure are merely with respect to the mutual positional relationship of the various components of this disclosure in the drawings. As used in this disclosure, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. In addition, unless defined otherwise, all technical and scientific terms used in this example have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in the description of the embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of the embodiments. The term "and/or" as used in this embodiment includes any combination of one or more of the associated listed items.
It should be understood that although the terms first, second, third, etc. may be used in this disclosure to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element of the same type from another. For example, a first element could also be termed a second element, and, similarly, a second element could also be termed a first element, without departing from the scope of the present disclosure. The use of any and all examples, or exemplary language ("e.g.," such as ") provided herein, is intended merely to better illuminate embodiments of the present embodiment and does not pose a limitation on the scope of the present embodiment unless otherwise claimed.
The present invention is not limited to the above embodiments, and any modifications, equivalent substitutions, improvements, etc. within the spirit and principle of the present invention should be included in the scope of the present invention as long as the technical effects of the present invention are achieved by the same means. Various modifications and variations are possible in the technical solutions and/or embodiments within the scope of the protection in the present embodiments.
Claims (10)
1. A dual-gate device integrating light emission and high performance photoelectric detection, the dual-gate device comprising:
a photodiode; the photodiode comprises a sixth electrode, a first carrier transmission layer, a light emitting layer, a second carrier transmission layer and an eighth electrode which are arranged from top to bottom; wherein the sixth electrode is a transparent electrode, and the eighth electrode is a bottom electrode of the photodiode;
a first transistor; the first transistor is positioned on one side below the photodiode, and the drain electrode of the first transistor is connected with the eighth electrode;
a second transistor; the second transistor is of a double-gate structure with a top gate, the second transistor is located on the other side below the photodiode, and the top gate of the second transistor is connected with the eighth electrode.
2. The dual gate device of claim 1, wherein the first transistor comprises:
a first dielectric layer; the first dielectric layer is positioned below the eighth electrode and connected with the eighth electrode;
a first semiconductor layer, a third electrode, and a seventh electrode; the first semiconductor layer, the third electrode and the seventh electrode are all positioned in the first dielectric layer, the third electrode is connected with one end of the first semiconductor layer, and the seventh electrode is respectively connected with the other end of the first semiconductor layer and the eighth electrode;
a second dielectric layer; the second dielectric layer is positioned below the first dielectric layer and connected with the first dielectric layer;
a first electrode; the first electrode is positioned in the second dielectric layer and below the first semiconductor layer
The first electrode is used as a grid electrode of the first transistor, the third electrode is used as a source electrode of the first transistor, and the seventh electrode is used as a drain electrode of the first transistor.
3. The dual gate device of claim 2, wherein the second transistor comprises:
a first dielectric layer; the first dielectric layer is positioned below the eighth electrode and connected with the eighth electrode;
a second semiconductor layer, a fourth electrode, and a fifth electrode; the second semiconductor layer, the fourth electrode and the fifth electrode are all positioned in the first dielectric layer, the fifth electrode is connected with one end of the second semiconductor layer, and the fourth electrode is connected with the other end of the second semiconductor layer;
a top gate electrode; the top gate electrodes are all positioned in the first dielectric layer, and the top gate electrodes are positioned above the second semiconductor layer;
a second dielectric layer; the second dielectric layer is positioned below the first dielectric layer and connected with the first dielectric layer;
a second electrode; the second electrode is positioned in the second dielectric layer, and the second electrode is positioned below the second semiconductor layer;
the second electrode is used as a grid electrode of the second transistor, the fifth electrode is used as a source electrode of the second transistor, and the fourth electrode is used as a drain electrode of the second transistor.
4. The dual-gate device of claim 3, further comprising:
a buffer layer; the buffer layer is positioned below the second dielectric layer and connected with the second dielectric layer.
5. The dual-gate device of claim 4, further comprising:
a transparent substrate; the transparent substrate is positioned below the buffer layer and connected with the buffer layer.
6. The dual gate device of any of claims 1-5, wherein:
the first carrier transport layer is an electron transport layer, and the second carrier transport layer is a hole transport layer;
or alternatively
The first carrier transport layer is a hole transport layer, and the second carrier transport layer is an electron transport layer.
7. The device of any one of claims 1-5, wherein the sixth electrode is LiF/Al or Au, and the light emitting layer is 45% peoxa:cspbbr 0.6 I 2.4 The eighth electrode is made of ITO, the first carrier transmission layer is made of TPBi, the second carrier transmission layer is made of Poly-TPD, or the first carrier transmission layer is made of Poly-TPD, and the second carrier transmission layer is made of TPBi.
8. The dual-gate device of any of claims 3-5, wherein the first dielectric layer and the second dielectric layer are made of high dielectric constant oxide, the first electrode, the second electrode, the third electrode, the fourth electrode, the fifth electrode, and the top gate electrode are made of Mo, and the first semiconductor layer and the second semiconductor layer are made of IGZO or poly-Si.
9. The dual-gate device of claim 5, wherein the buffer layer is made of SiO 2 The transparent substrate is made of glass.
10. A method for manufacturing a dual-gate device integrating light emission and high-performance photoelectric detection, the method comprising the steps of:
obtaining a transparent substrate, sequentially carrying out ultrasonic cleaning on the transparent substrate by using a cleaning agent, then placing the transparent substrate in an oven for drying, and cleaning the transparent substrate by using a plasma surface cleaning instrument;
depositing a buffer layer over the transparent substrate by plasma enhanced chemical vapor deposition;
performing photoetching patterning on the buffer layer, and depositing a layer of electrode serving as a grid electrode of the first transistor and a grid electrode of the second transistor in a thermal evaporation mode;
depositing a second dielectric layer on the buffer layer by using a plasma enhanced chemical vapor deposition method, and flattening the second dielectric layer;
depositing a first semiconductor layer and a second semiconductor layer on the second dielectric layer by magnetron sputtering, patterning by photoetching, and carrying out wet etching by using hydrochloric acid;
annealing the device obtained in the steps;
performing photoetching patterning on the second dielectric layer, and depositing a layer of electrode serving as a source electrode and a drain electrode of the first transistor and a source electrode and a drain electrode of the second transistor respectively by using a thermal evaporation mode;
depositing a first dielectric layer on the second dielectric layer by using a plasma enhanced chemical vapor deposition method, and flattening the first dielectric layer;
performing photoetching patterning on the first dielectric layer, and depositing a layer of electrode serving as a top gate electrode of the second transistor in a thermal evaporation mode;
continuing to deposit the second dielectric layer by using a plasma enhanced chemical vapor deposition method, and flattening the second dielectric layer;
manufacturing through holes at the drain electrode of the first transistor and the top gate electrode of the second transistor, and depositing a bottom electrode of the photodiode in a magnetron sputtering mode;
spin-coating a second carrier transport layer of the photodiode on the bottom electrode, and then annealing;
spin-coating a light-emitting layer of the photodiode on the second carrier transport layer, and then annealing;
and depositing a first carrier transmission layer and a transparent electrode of the photodiode on the light-emitting layer in sequence by using a thermal evaporation mode.
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