CN117766388A - Method for forming heterojunction bipolar transistor - Google Patents

Method for forming heterojunction bipolar transistor Download PDF

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Publication number
CN117766388A
CN117766388A CN202311373416.3A CN202311373416A CN117766388A CN 117766388 A CN117766388 A CN 117766388A CN 202311373416 A CN202311373416 A CN 202311373416A CN 117766388 A CN117766388 A CN 117766388A
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layer
forming
base
material layer
region
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赵亚楠
李新宇
丁帼君
姜清华
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Changzhou Chengxin Semiconductor Co Ltd
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Changzhou Chengxin Semiconductor Co Ltd
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Priority to CN202311373416.3A priority Critical patent/CN117766388A/en
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Abstract

A method of forming a heterojunction bipolar transistor, comprising: providing a substrate; forming a current collecting layer, a base material layer, a base protection material layer and an emitting material layer on a substrate; forming a first protective material layer on the emissive material layer; forming an emission layer and a first protective layer on the base protective material layer of the first region based on the emission material layer and the first protective material layer; forming a second protective material layer on the second region and the third region; etching the first protective layer and the second protective material layer on the emission layer, and forming a first groove penetrating the first protective layer and the second protective material layer on the emission layer; etching the second protective material layer and the base protective material layer on the second region, and forming a second groove which penetrates through the second protective material layer and the bottom of which is positioned in the base protective material layer on the second region; forming an emitter electrode layer in the first recess; and forming a base electrode layer in the second groove, wherein the emitting electrode layer and the base electrode layer are formed synchronously. The process flow is simplified.

Description

Method for forming heterojunction bipolar transistor
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for forming a heterojunction bipolar transistor.
Background
Gallium arsenide heterojunction bipolar transistor (GaAs Heterojunction Bipolar Transistors) is a commonly used power amplifier device and has the advantages of high-frequency characteristic, high working efficiency and good linearity.
The heterojunction transistor is made of semiconductors with different doping degrees in three parts, and the emitter region and the base region of the heterojunction transistor are made of two different semiconductor materials, so that the emitter junction forms a heterojunction, the heterojunction transistor has better high-frequency signal and base region emission efficiency than a general bipolar transistor, the heterojunction bipolar transistor is characterized by the emitter region with a wide band gap, the carrier injection efficiency of the emitter junction can be greatly improved, the series resistance of the base region is reduced, and the heterojunction bipolar transistor is widely applied to the fields of microwave millimeter waves, high-speed digital circuits, analog-to-digital converters, optical communication, mobile communication and the like.
However, the existing heterojunction bipolar transistor formation process has yet to be improved.
Disclosure of Invention
The invention provides a method for forming a heterojunction bipolar transistor to improve the forming process of the heterojunction bipolar transistor.
In order to solve the above technical problems, the technical solution of the present invention provides a method for forming a heterojunction bipolar transistor, including: providing a substrate, wherein the substrate sequentially comprises a first region, a second region and a third region in a first direction, the second region is positioned between the first region and the third region, and the first direction is parallel to the surface of the substrate; forming a current collecting layer, a base material layer positioned on the current collecting layer, a base protection material layer positioned on the base material layer and an emitting material layer positioned on the base protection material layer on the substrate; forming a first protective material layer on the emissive material layer; forming an emission layer and a first protective layer on the emission layer on the base protective material layer of the first region based on the emission material layer and the first protective material layer; forming a second protective material layer on the base protective material layers of the second region and the third region, the sidewall surfaces of the emission layer, the sidewall surfaces of the first protective layer, and the top surface of the first protective layer; etching the first protective layer and the second protective material layer on the emitting layer, and forming a first groove penetrating through the first protective layer and the second protective material layer on the emitting layer; etching the second protective material layer and the base protective material layer on the second region, forming a second groove on the second region, wherein the second groove penetrates through the second protective material layer, the bottom of the second groove is positioned in the base protective material layer, and the first groove and the second groove are synchronously formed; forming a transmitting electrode layer in the first groove, wherein the top surface of the transmitting electrode layer is higher than or flush with the top opening of the first groove; forming a base electrode layer in the second groove, wherein the emitting electrode layer and the base electrode layer are formed synchronously, and the top surface of the base electrode layer is higher than or flush with the top opening of the second groove; removing the second protective material layer and the base material layer on the third region, and forming a base layer and a second protective layer on the base layer on the first region and the collector layer on the second region; a collector layer is formed on the collector layer of the third region.
Optionally, the forming method of the first groove and the second groove includes: forming a patterned layer on the second protective material layer, wherein the patterned layer exposes part of the surfaces of the second protective material layer on the first area and the second area; etching the first protective layer and the second protective material layer on the first region by taking the patterned layer as a mask, exposing the top surface of the emitting layer, and forming a first groove on the first region; and etching the second protective material layer and the base protective material layer on the second region until the top surface of the base protective material layer is exposed, and forming a second groove on the second region.
Optionally, the forming method of the emitter electrode layer and the base electrode layer includes: forming an initial emitter electrode layer in the first groove and forming an initial base electrode layer in the second groove; and annealing the initial emitter electrode layer and the initial base electrode layer to form the emitter electrode layer and the base electrode layer, wherein the bottom of the base electrode layer is positioned in the base material layer, and the bottom of the emitter electrode layer is positioned in the emitter layer.
Optionally, the process of forming the initial base electrode layer and the initial emitter electrode layer includes an evaporation process.
Optionally, the initial base electrode layer and the initial emission electrode layer are formed synchronously, and the materials and the structures of the initial base electrode layer and the initial emission electrode layer are the same; the material and the structure of the emitting electrode layer and the base electrode layer are the same.
Optionally, the initial base electrode layer and the initial emitter electrode layer comprise a multilayer metal structure comprising: and a plurality of metal layers sequentially stacked in a direction perpendicular to the substrate, wherein a plurality of metal layers are sequentially formed.
Optionally, the process parameters of annealing the initial emitter electrode layer and the initial base electrode layer include: the temperature ranges from 360 degrees celsius to 400 degrees celsius and the time ranges from 110 seconds to 130 seconds.
Optionally, the method further comprises: forming an emission protection material layer on the emission material layer; forming an emission protection layer between the emission layer and the first protection layer on the base protection material layer of the first region based on the emission protection material layer; the first groove exposes the surface of the emission protection layer.
Optionally, the thickness of the base protective material layer is greater than the thickness of the first protective layer.
Optionally, the first groove and the second groove have the same depth.
Optionally, the material of the base layer protection material layer includes gallium indium phosphide.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
according to the technical scheme, the first protective layer and the second protective material layer on the emission layer are etched, a first groove penetrating through the first protective layer and the second protective material layer is formed, the second protective material layer and the base layer protective material layer on the second area are etched, a second groove penetrating through the second protective material layer and the bottom of the second groove is located in the base layer protective material layer is formed, and the process of forming the second groove and the first groove is the same photoetching process, so that one photomask and one etching process are saved; and forming an emission electrode layer in the first groove and a base electrode layer in the second groove synchronously, wherein the top surface of the emission electrode layer is higher than or flush with the top opening of the first groove, and the top surface of the base electrode layer is higher than or flush with the top opening of the second groove, so that a metal forming process is saved, the process steps are simplified, the cost is saved, and the production efficiency is improved.
Furthermore, the forming process of the emitting electrode layer and the base electrode layer further comprises annealing treatment, and the emitting electrode layer and the base electrode layer are formed by synchronous annealing, so that an annealing process is saved, the process steps are simplified, the cost is saved, and the production efficiency is improved.
Drawings
FIG. 1 is a schematic diagram of a heterojunction bipolar transistor according to an embodiment;
fig. 2 to 7 are schematic structural views of a heterojunction bipolar transistor forming process according to an embodiment of the present invention;
fig. 8 is a flow chart of a method for forming a heterojunction bipolar transistor according to an embodiment of the invention.
Detailed Description
As described in the background, the performance of heterojunction bipolar transistors has yet to be improved. The analysis will now be described with reference to specific examples.
Fig. 1 is a schematic diagram of a heterojunction bipolar transistor according to an embodiment.
Referring to fig. 1, the heterojunction bipolar transistor includes: a substrate 100; the substrate 100 sequentially comprises a first region I, a second region II and a third region III in a first direction X, wherein the second region II is positioned between the first region I and the third region III, and the first direction X is parallel to the surface of the substrate 100; a collector layer 101 on the substrate 100; a base layer 103 on the collector layer 101 of the first region I and the second region II; a base layer protective layer 104 on the base layer 103; an emission layer 105 on the base protective layer 104 of the first region I; a capping layer 106 on the emission layer 105; a emitter electrode layer 107 on the cap layer 106, the emitter electrode layer 107 being in electrical contact with the emitter layer 105; a protective layer 108 on the top surface and sidewall surface of the emitter electrode layer 107, the top cap layer 106, the sidewall surface of the emitter layer 105, and the base protective layer 104; a base electrode layer 109 on the base layer 103 of the second region II, the base electrode layer 109 penetrating the protective layer 108 and the base layer protective layer 104 to be in electrical contact with the base layer 103; and a collector layer 110 on the collector layer 101 of the third region III.
In the heterojunction bipolar transistor, the emitter electrode layer 107 and the base electrode layer 109 are formed in different process steps, and the method for forming the emitter electrode layer 107 and the base electrode layer 109 comprises: forming a first recess on the first region I exposing the cap top layer 106; forming an initial emitter electrode layer in a first groove, wherein the top surface of the initial emitter electrode layer is higher than or flush with the top opening of the first groove; annealing the initial emitter electrode layer to diffuse metal ions of the initial emitter electrode layer into the emitter layer 105 to contact the emitter layer 105, thereby forming the emitter electrode layer 107; forming a second recess exposing the base protective layer 104 on the second region II, the second recess penetrating the protective layer 108 and the base protective layer 104; forming an initial base electrode layer in the second groove, wherein the top surface of the initial base electrode layer is higher than or flush with the top opening of the second groove; the initial base electrode layer is annealed to diffuse metal ions of the initial base electrode layer into the base layer 103 to contact the base layer 103, forming a base electrode layer 109.
The emitter electrode layer 107 and the base electrode layer 109 are required to be formed by two etching processes and two annealing processes, two photomasks are required for the two etching processes, the processes are complex and repeated, and the cost of the photomasks is consumed.
In order to solve the above problems, the technical solution of the present invention provides a method for forming a heterojunction bipolar transistor, which comprises forming a first groove penetrating through a first protective layer and a second protective material layer on an emission layer by etching the first protective layer and the second protective material layer, forming a second groove penetrating through the second protective material layer and having a bottom located in the base protective material layer by etching the second protective material layer and the base protective material layer on a second region, wherein the process of forming the second groove and the first groove is the same lithography process, thereby saving a photomask and an etching process; and forming an emission electrode layer in the first groove and a base electrode layer in the second groove synchronously, wherein the top surface of the emission electrode layer is higher than or flush with the top opening of the first groove, and the top surface of the base electrode layer is higher than or flush with the top opening of the second groove, so that a metal forming process is saved, the process steps are simplified, the cost is saved, and the production efficiency is improved.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 8 is a flow chart of a method for forming a heterojunction bipolar transistor according to an embodiment of the invention.
Referring to fig. 8, the method for forming the heterojunction bipolar transistor includes:
step S10: providing a substrate, wherein the substrate sequentially comprises a first region, a second region and a third region in a first direction, the second region is positioned between the first region and the third region, and the first direction is parallel to the surface of the substrate;
step S20: forming a current collecting layer, a base material layer positioned on the current collecting layer, a base protection material layer positioned on the base material layer and an emitting material layer positioned on the base protection material layer on the substrate;
step S30: forming a first protective material layer on the emissive material layer;
step S40: forming an emission layer and a first protective layer on the emission layer on the base protective material layer of the first region based on the emission material layer and the first protective material layer;
step S50: forming a second protective material layer on the base protective material layers of the second region and the third region, the sidewall surfaces of the emission layer, the sidewall surfaces of the first protective layer, and the top surface of the first protective layer;
step S60: etching the first protective layer and the second protective material layer on the emitting layer, and forming a first groove penetrating through the first protective layer and the second protective material layer on the emitting layer;
step S70: etching the second protective material layer and the base protective material layer on the second region, forming a second groove on the second region, wherein the second groove penetrates through the second protective material layer, the bottom of the second groove is positioned in the base protective material layer, and the first groove and the second groove are synchronously formed;
step S80: forming a transmitting electrode layer in the first groove, wherein the top surface of the transmitting electrode layer is higher than or flush with the top opening of the first groove;
step S90: forming a base electrode layer in the second groove, wherein the emitting electrode layer and the base electrode layer are formed synchronously, and the top surface of the base electrode layer is higher than or flush with the top opening of the second groove;
step S100: removing the second protective material layer and the base material layer on the third region, and forming a base layer and a second protective layer on the base layer on the first region and the collector layer on the second region; a collector layer is formed on the collector layer of the third region.
The heterojunction bipolar transistor is formed by etching a first protective layer and a second protective material layer on an emission layer to form a first groove penetrating the first protective layer and the second protective material layer, etching the second protective material layer and a base layer protective material layer on a second area to form a second groove penetrating the second protective material layer and the bottom of the second groove is located in the base layer protective material layer, and the process of forming the second groove and the first groove is the same photoetching process, so that one photomask and one etching process are saved; and the emitter electrode layer positioned in the first groove and the base electrode layer positioned in the second groove are synchronously formed, so that a metal forming process is saved, the process steps are simplified, the cost is saved, and the production efficiency is improved.
Next, the steps will be described with reference to fig. 2 to 7. Fig. 2 to 7 are schematic structural views of a heterojunction bipolar transistor according to an embodiment of the present invention.
Referring to fig. 8 in conjunction with fig. 2, step S10 is performed: a substrate 200 is provided, the substrate 200 comprising a first region I, a second region II and a third region III in sequence in a first direction X, the second region II being located between the first region I and the third region III, the first direction X being parallel to the surface of the substrate 200.
In this embodiment, the material of the substrate 200 is silicon.
In other embodiments, the material of the substrate comprises silicon carbide, silicon germanium, a multi-component semiconductor material of group III-v elements, silicon-on-insulator (SOI), or germanium-on-insulator (GOI). Wherein the III-v element comprising multi-component semiconductor material comprises InP, gaAs, gaP, inAs, inSb, inGaAs or InGaAsP.
Please continue referring to fig. 8 in conjunction with fig. 2, step S20 is executed: forming a collector layer 201, a base material layer 203 on the collector layer 201, a base protective material layer 204 on the base material layer 203, and an emission material layer 205 on the base protective material layer 204 on the substrate 200; step S30: a first protective material layer 207 is formed on the emissive material layer 205.
In this embodiment, further comprising: an emission protection material layer 206 is formed on the emission material layer 205, and the first protection material layer 207 is on the emission protection material layer 206. In other embodiments, the emission protection material layer can be excluded.
The base layer material layer 203 is used for forming a base layer later, and the emitting material layer 205 is used for forming an emitting layer later.
In this embodiment, the material of the current collecting layer 201 includes N-type gallium arsenide; the material of the base material layer 203 comprises P-type gallium arsenide; the material of the emitting material layer 205 includes N-type gallium indium phosphide or gallium aluminum arsenide. The process of forming the collector layer 201 includes an epitaxial process, and the process of forming the emitter material layer 205 includes an epitaxial process.
The base protective material layer 204 is used for forming a base protective layer later, the emission protective material layer 206 is used for forming an emission protective layer later, and the first protective material layer 207 is used for forming a first protective layer later.
The material of the base protective material layer 204 includes gallium indium phosphide.
The material of the emission protection material layer 206 includes N-type gallium indium arsenide (InGaAs). The formation process of the emission protection material layer 206 includes an epitaxial process.
The material of the first protective material layer 207 includes a dielectric material including one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbide, and silicon oxycarbonitride.
In this embodiment, the material of the first protective material layer 207 includes silicon nitride. The forming process of the first protective material layer 207 includes a deposition process.
In this embodiment, the thickness range of the first protective material layer 207 is: 190 angstroms to 210 angstroms.
Referring to fig. 8 in conjunction with fig. 3, step S40 is performed: based on the emission material layer 205, the emission protection material layer 206, and the first protection material layer 207, an emission layer 208, an emission protection layer 209 on the emission layer 208, and a first protection layer 210 on the emission protection layer 209 are formed on the base protection material layer 203 of the first region I.
The forming method of the emission layer 208, the emission protection layer 209 and the first protection layer 210 includes: forming a patterned photoresist layer on the first protective material layer 207, the emission protective material layer 206, and the emission material layer 205; and etching the first protective material layer 207, the emission protective material layer 206 and the emission material layer 205 by using the patterned photoresist layer as a mask until the surface of the base protective material layer 204 is exposed, and forming the emission layer 208, the emission protective layer 209 and the first protective layer 210 on the first region I.
The process of etching the first protective material layer 207, the emission protective material layer 206, and the emission material layer 205 includes a dry etching process.
Referring to fig. 8 in conjunction with fig. 4, step S50 is performed: a second protective material layer 211 is formed on the base protective material layer 204 of the second and third regions II and III, the sidewall surface of the emission layer 208, the sidewall surface of the emission protective layer 209, the sidewall surface of the first protective layer 210, and the top surface of the first protective layer 210.
The material of the second protective material layer 211 includes a dielectric material including one or more of silicon oxide, silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, aluminum oxide, aluminum nitride, silicon oxycarbide, and silicon oxycarbonitride.
In this embodiment, the material of the second protective material layer 211 includes silicon nitride. The forming process of the second protective material layer 211 includes a deposition process.
In this embodiment, the thickness range of the second protective material layer 211 is: 190 angstroms to 210 angstroms.
Referring to fig. 8 in conjunction with fig. 5, step S60 is performed: etching the first protective layer 210 and the second protective material layer 211 on the emission layer 208 until the top surface of the emission protective layer 209 is exposed, and forming a first groove 212 penetrating the first protective layer 210 and the second protective material layer 211 on the emission protective layer 209; step S70: the second protective material layer 211 and the base protective material layer 204 on the second region II are etched, a second groove 213 is formed on the second region II, the second groove 213 penetrates through the second protective material layer 211, and the bottom of the second groove 213 is located in the base protective material layer 204.
The forming method of the first groove 212 and the second groove 213 includes: forming a patterned layer (not shown) on the second protective material layer 211, the patterned layer exposing a portion of the surface of the second protective material layer 211 on the first region I and the second region II; and etching the first protective layer 210 and the second protective material layer 211 on the first region I by taking the patterned layer as a mask until the top surface of the emission protective layer 209 is exposed, forming a first groove 212 on the first region I, synchronously etching the second protective material layer 211 and the base protective material layer 204 on the second region II by taking the patterned layer as a mask, and forming a second groove 213 on the second region II.
In this embodiment, the material of the patterned layer includes photoresist. The forming process of the patterned layer includes an exposure process and a developing process.
The process of etching the second protective material layer 211 and the base protective material layer 204 on the second region II, and the process of etching the first protective layer 210 and the second protective material layer 211 on the first region I includes a dry etching process.
In this embodiment, the first groove 212 and the second groove 213 are formed simultaneously. The first recess 212 and the second recess 213 can be formed using one mask and one etching process, thereby saving one mask and one etching process.
In this embodiment, the first recess 212 exposes the surface of the emission protection layer 209. The emission protection layer 209 can protect the emission layer 208 from damage to the surface of the emission layer 208 caused by the process of etching the first recess 212.
In other embodiments, the first recess exposes the emissive layer surface without the emissive protection layer.
In this embodiment, the thickness of the base protective material layer 204 is greater than the thickness of the first protective layer 210. Since the etching process for forming the first recess 212 and the second recess 213 is stopped to expose the surface of the emission protection layer 209, and the depth of the second recess 213 depends on the thicknesses of the first protection layer 210 and the second protection material layer 211, so that the thickness of the base protection material layer 204 is greater than that of the first protection layer 210, it can be ensured that the bottom of the formed second recess 213 is located in the base protection material layer 204, and the situation that the electrical property of the subsequently formed base layer is damaged due to the etching process for forming the second recess 213 etching to the base material layer 203 is avoided.
In this embodiment, the material of the emission protection layer 209 is different from the material of the first protection layer 210, so that the process of etching the second protection material layer 211 and the first protection layer 210 can stop on the emission protection layer 209 with a larger etching selectivity ratio of the first protection layer 210 to the emission protection layer 209.
In this embodiment, the first groove 212 and the second groove 213 have the same depth. By adjusting the parameters of the dry etching process, the etching rates of the dry etching process on the first protective layer 210 and the base protective material layer 204 with different materials are basically the same, so that the depths of the formed first groove 212 and second groove 213 are the same, and the depth of the second groove 213 located on the second area II is further precisely controlled.
In other embodiments, the first and second grooves can be different depths.
Referring to fig. 8 in conjunction with fig. 6, step S80 is performed: forming a emitter electrode layer 214 within the first recess 212, the top surface of the emitter electrode layer 214 being higher than or flush with the top opening of the first recess 212; step S90: a base electrode layer 215 is formed in the second recess 213, the emitter electrode layer 214 and the base electrode layer 215 are simultaneously formed, and the top surface of the base electrode layer 215 is higher than or flush with the top opening of the second recess 213.
The forming method of the emitter electrode layer 214 and the base electrode layer 215 includes: forming an initial emitter electrode layer (not shown) within the first recess 212, the top surface of the initial emitter electrode layer being above or flush with the first recess 212 top opening; forming an initial base electrode layer (not shown) within the second recess 213, the top surface of the initial base electrode layer being higher than or flush with the second recess 213 top opening; the initial emitter electrode layer and the initial base electrode layer are annealed to form the emitter electrode layer 214 and the base electrode layer 215, wherein the top surface of the emitter electrode layer 214 is higher than or flush with the top opening of the first groove 212, the bottom of the emitter electrode layer 214 is located in the emitter layer 208, the top surface of the base electrode layer 215 is higher than or flush with the top opening of the second groove 213, and the bottom of the base electrode layer 215 is located in the base material layer 203.
In this embodiment, the process parameters of annealing the initial emitter electrode layer and the initial base electrode layer include: the temperature ranges from 360 degrees celsius to 400 degrees celsius and the time ranges from 110 seconds to 130 seconds.
In this embodiment, the top surface of the emitter electrode layer 214 is higher than or flush with the top opening of the first recess 212, and the top surface of the base electrode layer 215 is higher than or flush with the top opening of the second recess 213. In one aspect, the emitter electrode layer 214 is formed by allowing the initial emitter electrode layer to have a thickness sufficient to allow metal ions of the initial emitter electrode layer to diffuse into the base layer 203, and the emitter electrode layer 214 is formed by allowing the initial base electrode layer to have a thickness sufficient to allow metal ions of the initial base electrode layer to diffuse into the emitter layer 208; on the other hand, when other connection structures electrically connected to the emitter electrode layer 214 and the base electrode layer 215 are formed later, the alignment connection with the emitter electrode layer 214 and the base electrode layer 215 is facilitated.
And an annealing process is adopted, so that the metal ions of the initial emitter electrode layer are diffused into the base material layer 203 to form the emitter electrode layer 214, and the metal ions of the initial base electrode layer are diffused into the emitter layer 208 to form the emitter electrode layer 214, thereby saving the cost of the annealing process and being beneficial to improving the production efficiency.
The process of forming the initial base electrode layer and the initial emitter electrode layer includes an evaporation process.
The initial emitter electrode layer and the initial base electrode layer comprise a multi-layer metal structure comprising: the first metal layer, the second metal layer, the third metal layer and the fourth metal layer are sequentially stacked in the direction perpendicular to the substrate, and the first metal layer, the second metal layer, the third metal layer and the fourth metal layer are sequentially formed.
In this embodiment, the material of the first metal layer includes platinum; the material of the second metal layer comprises titanium; the material of the third metal layer comprises platinum; the material of the fourth metal layer comprises copper or gold.
In this embodiment, since the initial emitter electrode layer and the initial base electrode layer are formed simultaneously, the materials and structures of the initial emitter electrode layer and the initial base electrode layer are the same, and the materials and structures of the emitter electrode layer 214 and the base electrode layer 215 are the same, so that a metal forming process is omitted.
Referring to fig. 8 in conjunction with fig. 7, step S100 is performed: removing the second protective material layer 211, the base protective material layer 204 and the base material layer 203 on the third region III, forming a base layer 216, a base protective layer 217 on the surface of the base layer 216, and a second protective layer 219 on the base protective layer 217, the sidewall surface of the emission layer 208, the sidewall surface of the emission protective layer 209, the sidewall surface of the first protective layer 210, and the top surface of the first protective layer 210 on the collector layer 201 on the first region I and on the second region II; a collector layer 218 is formed on the collector layer 201 of the third region III.
The method for forming the collector layer 218 includes: forming an initial collector layer (not shown) on the collector layer 201 of the third region III; the initial collector layer is annealed to form the collector layer 218.
The initial collector layer comprises a structure of multiple layers of metal including a combination of one or more of platinum, titanium, copper, and gold.
In this embodiment, further comprising: conductive structures (not shown) are formed on the collector layer 218, the base electrode layer 215, and the emitter electrode layer 214.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.

Claims (11)

1. A method of forming a heterojunction bipolar transistor, comprising:
providing a substrate, wherein the substrate sequentially comprises a first region, a second region and a third region in a first direction, the second region is positioned between the first region and the third region, and the first direction is parallel to the surface of the substrate;
forming a current collecting layer, a base material layer positioned on the current collecting layer, a base protection material layer positioned on the base material layer and an emitting material layer positioned on the base protection material layer on the substrate;
forming a first protective material layer on the emissive material layer;
forming an emission layer and a first protective layer on the emission layer on the base protective material layer of the first region based on the emission material layer and the first protective material layer;
forming a second protective material layer on the base protective material layers of the second region and the third region, the sidewall surfaces of the emission layer, the sidewall surfaces of the first protective layer, and the top surface of the first protective layer;
etching the first protective layer and the second protective material layer on the emitting layer, and forming a first groove penetrating through the first protective layer and the second protective material layer on the emitting layer;
etching the second protective material layer and the base protective material layer on the second region, forming a second groove on the second region, wherein the second groove penetrates through the second protective material layer, the bottom of the second groove is positioned in the base protective material layer, and the first groove and the second groove are synchronously formed;
forming a transmitting electrode layer in the first groove, wherein the top surface of the transmitting electrode layer is higher than or flush with the top opening of the first groove;
forming a base electrode layer in the second groove, wherein the emitting electrode layer and the base electrode layer are formed synchronously, and the top surface of the base electrode layer is higher than or flush with the top opening of the second groove;
removing the second protective material layer and the base material layer on the third region, and forming a base layer and a second protective layer on the base layer on the first region and the collector layer on the second region; a collector layer is formed on the collector layer of the third region.
2. The method of forming a heterojunction bipolar transistor of claim 1, wherein said method of forming a first recess and a second recess comprises: forming a patterned layer on the second protective material layer, wherein the patterned layer exposes part of the surfaces of the second protective material layer on the first area and the second area; etching the first protective layer and the second protective material layer on the first region by taking the patterned layer as a mask, exposing the top surface of the emitting layer, and forming a first groove on the first region; and etching the second protective material layer and the base protective material layer on the second region until the top surface of the base protective material layer is exposed, and forming a second groove on the second region.
3. The method of forming a heterojunction bipolar transistor of claim 1, wherein said method of forming an emitter electrode layer and a base electrode layer comprises: forming an initial emitter electrode layer in the first groove and forming an initial base electrode layer in the second groove; and annealing the initial emitter electrode layer and the initial base electrode layer to form the emitter electrode layer and the base electrode layer, wherein the bottom of the base electrode layer is positioned in the base material layer, and the bottom of the emitter electrode layer is positioned in the emitter layer.
4. The method of forming a heterojunction bipolar transistor of claim 3, wherein the process of forming the initial base electrode layer and the initial emitter electrode layer comprises an evaporation process.
5. The method of forming a heterojunction bipolar transistor as claimed in claim 3, wherein said initial base electrode layer and initial emitter electrode layer are formed simultaneously, and wherein said initial base electrode layer and initial emitter electrode layer are of the same material and structure; the material and the structure of the emitting electrode layer and the base electrode layer are the same.
6. The method of forming a heterojunction bipolar transistor of claim 5, wherein said initial base electrode layer and initial emitter electrode layer comprise a multi-layer metal structure comprising: and a plurality of metal layers sequentially stacked in a direction perpendicular to the substrate, wherein a plurality of metal layers are sequentially formed.
7. The method of forming a heterojunction bipolar transistor of claim 3, wherein the process parameters of annealing the initial emitter electrode layer and the initial base electrode layer comprise: the temperature ranges from 360 degrees celsius to 400 degrees celsius and the time ranges from 110 seconds to 130 seconds.
8. The method of forming a heterojunction bipolar transistor of claim 1, further comprising: forming an emission protection material layer on the emission material layer; forming an emission protection layer between the emission layer and the first protection layer on the base protection material layer of the first region based on the emission protection material layer; the first groove exposes the surface of the emission protection layer.
9. The method of forming a heterojunction bipolar transistor of claim 1, wherein a thickness of said base protective material layer is greater than a thickness of said first protective layer.
10. The method of forming a heterojunction bipolar transistor of claim 1, wherein the first recess and the second recess have the same depth.
11. The method of forming a heterojunction bipolar transistor of claim 1, wherein the material of said base protective material layer comprises gallium indium phosphide.
CN202311373416.3A 2023-10-20 2023-10-20 Method for forming heterojunction bipolar transistor Pending CN117766388A (en)

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