CN117762846A

CN117762846A - Hot plug system and method for PCIE equipment

Info

Publication number: CN117762846A
Application number: CN202311672737.3A
Authority: CN
Inventors: 徐文波; 王伟伟; 徐晨涛; 陈骏
Original assignee: CETC 52 Research Institute
Current assignee: CETC 52 Research Institute
Priority date: 2023-12-07
Filing date: 2023-12-07
Publication date: 2024-03-26

Abstract

The invention provides a hot plug system and a method for PCIE equipment, comprising the following steps: the PCIE bridge chip is connected with PCIE equipment through the PCIE bridge chip, and an isolation chip is assembled between the PCIE bridge chip and the PCIE equipment; the isolation chip is configured to transmit signals between the PCIE bridge chip and the PCIE device during normal operation of the PCIE device, and isolate signals between the PCIE bridge chip and the PCIE device during hot-pulling of the PCIE device; the power supply is used for supplying power to the main board, the PCIE equipment and the isolation chip; the control chip is used for responding to the detected hot-drawing operation aiming at the PCIE equipment and controlling the power supply to stop supplying power to the PCIE equipment and the isolation chip; and controlling the power supply to resume power supply to the PCIE equipment and the isolation chip in response to the detected hot plug operation for the PCIE equipment.

Description

Hot plug system and method for PCIE equipment

Technical Field

The invention relates to the field of consensus, in particular to a hot plug system and a hot plug method for PCIE equipment.

Background

PCIE (peripheral component interconnect expres, high-speed serial computer expansion bus standard) hot plug technology refers to: the system takes out PCIE equipment or replaces part of PCIE equipment units under the condition of continuous power failure, thereby improving the fault recovery capability, flexibility, expansibility and the like of the equipment. In particular, in an airborne storage system, PCIE devices are part of the system, and after a single task is finished or the device is fully stored, PCIE devices need to be taken out from the device to an unloading device to perform data unloading, and new PCIE devices are inserted at the same time to prepare for performing a next task. At this time, the PCIE hot plug technology may improve efficiency of PCIE device replacement.

In the related art, PCIE devices supporting PCIE hot plug technology are often designed for gold finger long and short pins, and the main advantages of such designs are that: in the plugging process, a static discharge path can be formed, so that devices at two ends are prevented from being damaged due to plugging static. However, the structural form of the golden finger is not suitable for occasions with high requirements on the number of plugging times. Moreover, the long and short pin design is not suitable for all PCIE devices, and for PCIE devices that do not support the long and short pin design, there is no way to perform effective static protection, which may cause damage to devices at two ends due to plugging and unplugging.

Disclosure of Invention

In view of the above, the present invention provides a hot plug system and method for PCIE devices to solve the deficiencies in the related art.

Specifically, the invention is realized by the following technical scheme:

according to a first aspect of the present invention, there is provided a hot plug system for PCIE devices, the system comprising:

the PCIE bridge chip is connected with PCIE equipment through the PCIE bridge chip, and an isolation chip is assembled between the PCIE bridge chip and the PCIE equipment;

the isolation chip is configured to transmit signals between the PCIE bridge chip and the PCIE device during normal operation of the PCIE device, and isolate signals between the PCIE bridge chip and the PCIE device during hot-pulling of the PCIE device;

the power supply is used for supplying power to the main board, the PCIE equipment and the isolation chip;

the control chip is configured to control, in response to the detected hot-plug operation for the PCIE device, the power supply to stop supplying power to the PCIE device and the isolation chip, so that the isolation chip isolates signals between a PCIE bridge chip and the PCIE device; and controlling the power supply to resume power supply to the PCIE equipment and the isolation chip in response to the detected hot plug operation for the PCIE equipment so as to enable the PCIE equipment to normally operate.

According to a second aspect of the present invention, there is provided a hot plug method for PCIE devices, applied to a control chip on a motherboard, where the motherboard is connected to the PCIE devices, a PCIE bridge chip is assembled on the motherboard, and an isolation chip is assembled between the PCIE bridge chip and the PCIE devices, and the system includes:

responding to the detected hot-drawing operation aiming at the PCIE equipment, controlling a power supply connected with the main board to send a power-off instruction to stop supplying power to the PCIE equipment and the isolation chip, so that the isolation chip isolates signals between a PCIE bridging chip and the PCIE equipment;

and controlling the power supply to resume power supply to the PCIE equipment and the isolation chip in response to the detected hot plug operation for the PCIE equipment so as to enable the PCIE equipment to normally operate.

According to a third aspect of the present invention, there is provided an electronic device comprising:

a processor;

a memory for storing processor-executable instructions;

wherein the processor implements the method of the first aspect by executing the executable instructions.

According to a fourth aspect of the present invention there is provided a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of the method of the first aspect.

The technical scheme provided by the embodiment of the invention can comprise the following beneficial effects:

in the embodiment of the invention, on one hand, the isolation chip is arranged on the PCIE equipment and the PCIE bridging chip, and the power supply to the isolation chip is stopped during the hot-drawing of the PCIE equipment, so that the isolation chip can isolate signals between the PCIE bridging chip and the PCIE equipment during the hot-drawing of the PCIE equipment, thereby avoiding the generation of the static electricity for drawing and inserting and protecting the safety of the equipment; on the other hand, during normal operation of the PCIE device, the isolation chip may be used to transmit signals between the PCIE bridge chip and the PCIE device, so that normal operation of the PCIE device is not affected, and thus, the device operation status and the device security are both considered.

Drawings

In order to more clearly illustrate the technical solution of the present invention, the following description will make a brief introduction to the drawings used in the description of the embodiments or the prior art. It is evident that the drawings in the following description are only some embodiments of the present invention and that other drawings may be obtained from these drawings without inventive effort for a person of ordinary skill in the art.

Fig. 1 is a architecture diagram of a hot plug system for PCIE devices according to an embodiment of the disclosure;

FIG. 2 is a schematic diagram of an isolated chip according to an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a detection module according to an embodiment of the present disclosure;

fig. 4 is a flowchart of a hot plug method for PCIE devices according to an embodiment of the disclosure;

FIG. 5 is a schematic block diagram of an electronic device shown in an embodiment of the present disclosure;

fig. 6 is a block diagram of a hot plug apparatus for PCIE devices according to an embodiment of the disclosure.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the invention. Rather, they are merely examples of apparatus and methods consistent with aspects of the invention.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.

It should be understood that although the terms first, second, third, etc. may be used herein to describe various information, these information should not be limited by these terms. These terms are only used to distinguish one type of information from another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the invention. The word "if" as used herein may be interpreted as "at … …" or "at … …" or "responsive to a determination", depending on the context.

Embodiments of a hot plug system and method for PCIE devices according to the present invention are described in detail below with reference to the accompanying drawings.

In the related art, PCIE devices supporting PCIE hot plug technology are designed by golden finger long and short needles, and the design has the main advantages that: in the plugging process, a static discharge path can be formed, so that devices at two ends are prevented from being damaged due to plugging static. However, the structural form of the golden finger is not suitable for occasions with high requirements on the number of plugging times. Moreover, the long and short pin design is not suitable for all PCIE devices, and for PCIE devices that do not support the long and short pin design, there is no way to perform effective static protection, which may cause damage to devices at two ends due to plugging and unplugging.

In order to solve the defects existing in the related art, the specification provides a hot plug system for PCIE devices.

Fig. 1 is an architecture diagram of a hot plug system for PCIE devices according to an exemplary embodiment of the disclosure, as shown in fig. 1, where the architecture diagram includes: motherboard 10, PCIE device 20, isolation chip 30, and power supply 40.

The motherboard 10 may be a motherboard (main board) of a computer, which is one of the most basic and important components of a computer. The motherboard is the core of the computer hardware system, and chips for realizing different functions can be assembled on the motherboard, and different functional logics can be realized based on the assembled chips. The main board 10 is mounted with a control chip. As shown in fig. 1, a control chip 101 and a PCIE bridge chip 102 are mounted on a motherboard 10. The control chip 101 is configured with various processing logic for controlling the device to operate, and the PCIE bridge chip 102 is used for connecting different PCIE buses and converting data transmission between them into a proper format. The motherboard 10 is connected to the PCIE device 20 through the PCIE bridge chip 102.

PCIE device 20 may be a computer external device supporting PCIE, and may include: display cards, solid state drives (in PCIE interface form), wireless network cards, wired network cards, sound cards, video capture cards, and the like, and specific PCIE devices are not limited in this specification.

An isolation chip 30 is mounted between the PCIE bridge chip 102 and the PCIE device 20. In one case, the isolation chip 30 may be mounted on one end of the motherboard 10 as a functional chip on the motherboard 10, and the control chip 101 may control the isolation chip more efficiently; in another case, the isolation chip 30 may be mounted at one end of the PCIE device 20, and used as a functional chip on the PCIE device 20, where the isolation chip 30 may block the communications more effectively. The present description does not limit the specific location of the spacer chip 30.

The isolation chip 30 is configured to transmit signals between the PCIE bridge chip 102 and the PCIE device 20 during normal operation of the PCIE device 20, and isolate signals between the PCIE bridge chip 102 and the PCIE device 20 during hot-pulling of the PCIE device 20.

The power supply 40 is controlled by a control chip 101 mounted on the host 10, and is used for supplying power to the motherboard 10 (including the individual chips mounted on the motherboard 10), the isolation chip 30, and the PCIE device. Specifically, the control chip 101 may send targeted power supply instructions and power-off instructions to the power supply 40, for example: the control chip 101 may send a power-off instruction for the PCIE device 20 to the power supply 40, and the power supply 40 may identify the received instruction and stop supplying power to the PCIE device 20; alternatively, the control chip 101 may send a power supply instruction for the isolated chip 30 to the power supply 40, and the power supply 40 may recognize the received instruction and start supplying power to the isolated chip 30.

The control chip 101 responds to the detected hot-plug operation for the PCIE device 20, and controls the power supply to stop supplying power to the PCIE device 20 and the isolation chip 30, so that the isolation chip 30 isolates signals between the PCIE bridge chip 102 and the PCIE device 20.

In the related art, during hot plug of PCIE devices, there are still signals continuously transmitted between the PCIE bridge chip and the PCIE devices, for example: clock signals, PCIE device bit signals, etc. The transmission of these signals means: during hot plug of PCIE devices, at least part of the PCIE devices and PCIE bridge chips are still powered by power, and based on this, hot plug operations of PCIE devices will cause plug static.

The isolation chip 30 is arranged between the PCIE bridge chip 102 and the PCIE device 20, and power supply to the isolation chip 30 and the PCIE device 20 is stopped during hot plug of the PCIE device 20, so that signals between the PCIE device 20 and the PCIE bridge chip 102 are completely isolated, and conditions for generating plug static do not exist, thereby avoiding damage to devices caused by the plug static.

In response to the detected hot plug operation for the PCIE device 20, the control power supply 40 resumes power supply to the PCIE device 20 and the isolation chip 30, so that the PCIE device 20 operates normally.

After the PCIE device 20 resets, the power supply 40 may resume power supply to the PCIE device 20 and the isolation chip 30, so that the PCIE device 20 obtains power supply, and the isolation chip 30 may transmit signals between the PCIE device 20 and the PCIE bridge chip 102, thereby ensuring normal operation of the PCIE device 20.

On the one hand, the hot plug system of the PCIE equipment is characterized in that an isolation chip is arranged on the PCIE equipment and the PCIE bridging chip, and power supply to the isolation chip is stopped during hot plug of the PCIE equipment, so that the isolation chip can isolate signals between the PCIE bridging chip and the PCIE equipment during hot plug of the PCIE equipment, thereby avoiding the generation of plug static electricity and protecting the safety of the equipment; on the other hand, during normal operation of the PCIE device, the isolation chip may be used to transmit signals between the PCIE bridge chip and the PCIE device, so that normal operation of the PCIE device is not affected, and thus, the device operation status and the device security are both considered.

In an embodiment, the isolation chip includes a PCIE clock driver, a PCIE repeater, and a general purpose input/output isolation chip; the PCIE clock driver is configured to isolate clock signals between the PCIE bridge chip and the PCIE device during the PCIE device hot-pulling period; the PCIE repeater is configured to isolate digital signals between the PCIE bridge chip and the PCIE device during the hot-pulling period of the PCIE device; the general input/output isolation chip is configured to isolate general signals between the PCIE bridge chip and the PCIE device during the hotpull of the PCIE device, where the general signals include the PCIE reset signal and a PCIE device in-place signal.

As shown in fig. 2, the isolation chip 30 includes a PCIE clock driver 301, a PCIE repeater 302, and a general purpose input output isolation chip 303. The PCIE clock driver 301 is configured to isolate clock signals between the PCIE bridge chip 102 and the PCIE device 20 during the hot-pulling of the PCIE device 20, where the clock signals are used for data synchronization between the PCIE device 20 and the motherboard 10. The PCIE repeater 302 is configured to isolate PCIE digital signals between the PCIE bridge chip 102 and the PCIE device 20 during the hot-pulling period of the PCIE device 20. The general input/output isolation chip 303 is configured to isolate general signals between the PCIE bridge chip 102 and the PCIE device 20 during the hot-pulling period of the PCIE device 20, where the general signals include a PCIE reset signal and a PCIE device bit signal. The PCIE reset signal is an initialization signal sent by the motherboard to the PCIE device, and the PCIE device in-place signal is used to characterize whether the PCIE device 20 is connected to the motherboard 10. Of course, the general-purpose signal is not limited thereto, and the present specification does not limit the general-purpose signal.

In this embodiment, three signals (clock signal, digital signal and general signal) between the PCIE device and the PCIE bridge chip are isolated by three different isolation chips (PCIE clock driver, PCIE repeater and general input/output isolation chip), so that no static electricity is generated during hot-plug of the PCIE device, and safety of the device is protected.

In an embodiment, the system further comprises: the shutter is arranged outside the PCIE equipment and used for protecting the PCIE equipment from being interfered by external environments; the shutter is provided with a switch device, and the main board is also provided with a switch detection module and an in-place detection module; the control chip is further configured to determine that a hot-plug operation for the PCIE device is detected when the switch detection module detects that the switch device is turned on and the in-place detection module detects that the PCIE device is in place; the control chip is further configured to determine that a hot plug operation for the PCIE device is detected when the switch detection module detects that the switch device is turned off and the in-place detection module detects that the PCIE device is turned from an out-of-place state to an in-place state.

As shown in fig. 3, the switch detection module 103 may send a switch signal to the control chip 101, so that the control chip 101 may recognize the received switch signal and thereby determine whether the rotary switch on the shutter is turned on.

Further, the switch detection module is a light sensing detection device, and the switch device is a rotary switch; when the rotary switch rotates to an open gear, the light sensing signal detected by the light sensing detection device is changed from 1 to 0; when the rotary switch rotates to the off gear, the light sensing signal detected by the light sensing detection device is changed from 0 to 1. The switch signal is a light sense signal, and the light sense signal may be set to other recognition logic besides 0 and 1, which is not limited in this specification.

The in-place detection module 104 may send an in-place signal to the control chip 101, so that the control chip 101 may identify the received in-place signal, and determine whether the PCIE device is connected to the motherboard 10. Further, the in-place detecting module 104 may be a pin disposed on the motherboard 10, where one end of the pin is grounded, and the other end of the pin is connected to PCIE device. Under the condition that PCIE equipment is in place, the pin grounding circuit is short-circuited, and a low-level signal (in-place signal) is sent to the control chip; in the case that the PCIE device is not in place, the pin-to-ground circuit is not shorted and sends a high level signal (out of place signal) to the control chip.

In this embodiment, the hot plug operation of the PCIE device is determined by two determining conditions, that is, whether the rotary switch on the shutter is turned on and whether the PCIE device is in place, so that a preventive measure is made on plug static generated by hot plug of the PCIE device.

In an embodiment, the control chip is further configured to close application software associated with the PCIE device and offload a file system and an underlying driver associated with the PCIE device in response to the detected hot-pull operation for the PCIE device.

After detecting the hot-plug operation for the PCIE device 20, the control chip 101 may first close application software associated with the PICE device 20, for example: when the PCIE device is a graphics card, the video playing software or the live broadcast software is associated with the graphics card, and if a program corresponding to such software is in an operating state at this time, the operation can be stopped; or, if the PCIE device is a sound card, the sound receiving software or the sound identifying software is associated with the sound card, and if a program corresponding to the sound receiving software is in an operating state at this time, the operation may be stopped.

After closing the application software, the control chip 101 may also uninstall the file system associated with the PCIE device, for example: in the case that the PCIE device is a Solid State Disk (SSD), a database system managed by the SSD needs to be uninstalled.

Both the closing of the application software and the unloading of the file system belong to the unloading process of the application layer, and after the unloading process of the application layer is completed, the control chip 101 may control the unloading process that is completed and obtained by the bottom layer, for example, unloading NVME (Non Volatile Memory Host Controller Interface Specification Express, non-volatile memory host controller interface specification) drivers and PCIE drivers, etc.

After the above-described tray unloading process is completed, the control chip 101 may control the power supply 40 to stop supplying power to the PCIE device 20 and the isolation chip 30.

In this embodiment, before the power of the PCIE device is turned off, the disk unloading process is completed in advance, so that the running program, system, and drive are not affected by the unplugging of the PCIE device.

In an embodiment, the system further comprises: the indicator lamp is used for receiving the light signals of the control chip and displaying light according to the received light signals; the control chip is further configured to send a red light flashing signal to the indicator light in response to the detected hot-plug operation or hot-plug operation for the PCIE device; in response to detecting that the PCIE device is out of place, sending a turn-off signal to the indicator light; and in response to detecting that the PCIE equipment normally operates, sending a green light normally-on signal to the indicator light.

The embodiment displays different lights under different conditions so that a user can know the operation condition of PCIE equipment conveniently. Of course, the display effect of the light is not limited thereto, for example: yellow light can be displayed when the PCIE device is out of place, or red normally-on light can be displayed during hot plug of the PCIE device, and the specification does not limit the yellow light.

In one embodiment, the PCIE device is equipped with pin-length air connectors.

As described above, in the related art, PCIE devices supporting PCIE hot-plug technology are often designed for gold fingers with long pins and short pins, but the structural form of gold fingers is not suitable for occasions with high requirements on the number of plug-in times. The structure form of the equal-length stitch is suitable for occasions with high plugging times. Because the hot plug system provided by the invention isolates signals between the PCIE bridge chip and the PCIE equipment, plug static electricity can not be generated, and a static electricity discharge path is not required to be set. Compared with the design of the long and short pins of the golden finger, the aviation plug-in component with equal length stitch is more applicable occasions.

Fig. 4 is a flowchart of a hot plug method for PCIE devices according to an exemplary embodiment of the disclosure, where the method is applied to a control chip on a motherboard, the motherboard is connected to PCIE devices, a PCIE bridge chip is assembled on the motherboard, and an isolation chip is assembled between the PCIE bridge chip and the PCIE devices; the method specifically comprises the following steps:

step 402, in response to the detected hot-plug operation for the PCIE device, controlling a power supply connected to the motherboard to send a power-off instruction to stop supplying power to the PCIE device and the isolation chip, so that the isolation chip isolates signals between a PCIE bridge chip and the PCIE device;

and step 404, controlling the power supply to resume the power supply to the PCIE device and the isolation chip in response to the detected hot plug operation for the PCIE device, so that the PCIE device operates normally.

In the embodiment, on one hand, by arranging the isolation chip on the PCIE device and the PCIE bridge chip and stopping supplying power to the isolation chip during the hot-pull of the PCIE device, the isolation chip can isolate signals between the PCIE bridge chip and the PCIE device during the hot-pull of the PCIE device, thereby avoiding the generation of pull-plug static electricity and protecting the safety of the device; on the other hand, during normal operation of the PCIE device, the isolation chip may be used to transmit signals between the PCIE bridge chip and the PCIE device, so that normal operation of the PCIE device is not affected, and thus, the device operation status and the device security are both considered.

As described above, the isolation chip includes a PCIE clock driver, a PCIE repeater, and a general purpose input/output isolation chip; the PCIE clock driver is configured to isolate clock signals between the PCIE bridge chip and the PCIE device during the PCIE device hot-pulling period; the PCIE repeater is configured to isolate digital signals between the PCIE bridge chip and the PCIE device during the hot-pulling period of the PCIE device; the general input/output isolation chip is configured to isolate general signals between the PCIE bridge chip and the PCIE device during the hotpull of the PCIE device, where the general signals include the PCIE reset signal and a PCIE device in-place signal.

As mentioned above, a shutter may be disposed outside the PCIE device, where the shutter is used to protect the PCIE device from being interfered by an external environment; the shutter is provided with a switch device, and the main board is also provided with a switch detection module and an in-place detection module; the control chip is further configured to determine that a hot-plug operation for the PCIE device is detected when the switch detection module detects that the switch device is turned on and the in-place detection module detects that the PCIE device is in place; the control chip is further configured to determine that a hot plug operation for the PCIE device is detected when the switch detection module detects that the switch device is turned off and the in-place detection module detects that the PCIE device is turned from an out-of-place state to an in-place state.

As mentioned above, the switch detection module is a light sensing detection device, and the switch device is a rotary switch; when the rotary switch rotates to an open gear, the light sensing signal detected by the light sensing detection device is changed from 1 to 0; when the rotary switch rotates to the off gear, the light sensing signal detected by the light sensing detection device is changed from 0 to 1.

As described above, the control chip is further configured to close application software associated with the PICE device and offload a file system and an underlying driver associated with the PCIE device in response to the detected hot-pull operation for the PCIE device.

As mentioned above, the main board or the PCIE device may further be provided with an indicator light, which is configured to receive a light signal of the control chip, and display light according to the received light signal; the control chip is further configured to send a red light flashing signal to the indicator light in response to the detected hot-plug operation or hot-plug operation for the PCIE device; in response to detecting that the PCIE device is out of place, sending a turn-off signal to the indicator light; and in response to detecting that the PCIE equipment normally operates, sending a green light normally-on signal to the indicator light.

As previously described, the PCIE devices are equipped with pin-length air connectors.

The invention also provides an embodiment of the electronic equipment and the device corresponding to the embodiment of the method.

Fig. 5 is a schematic structural diagram of an electronic device shown in an embodiment of the present invention. Referring to fig. 5, at the hardware level, the device includes a processor 501, a network interface 502, a memory 503, a nonvolatile memory 504, and an internal bus 505, and may include hardware required by other services. One or more embodiments of the invention may be implemented on a software basis, such as by the processor 501 reading a corresponding computer program from the non-volatile storage 504 into the memory 503 and then running. Of course, in addition to software implementation, one or more embodiments of the present invention do not exclude other implementation, such as a logic device or a combination of software and hardware, etc., that is, the execution subject of the following process flows is not limited to each logic unit, but may also be hardware or a logic device.

Fig. 6 is a block diagram of a hot plug device for PCIE devices according to an embodiment of the present invention. Referring to fig. 6, the device may be applied to the apparatus shown in fig. 6 and applied to a control chip on a motherboard, where the motherboard is connected to a PCIE device, a PCIE bridge chip is assembled on the motherboard, and an isolation chip is assembled between the PCIE bridge chip and the PCIE device, so as to implement the technical scheme of the present invention, the device includes:

the first control unit 602 is configured to control, in response to the detected hot-plug operation for the PCIE device, a power supply connected to the motherboard to send a power-off instruction to stop supplying power to the PCIE device and the isolation chip, so that the isolation chip isolates signals between a PCIE bridge chip and the PCIE device;

and the second control unit 604 is configured to control, in response to the detected hot plug operation for the PCIE device, the power supply to resume power supply to the PCIE device and the isolation chip, so that the PCIE device operates normally.

While this invention contains many specific implementation details, these should not be construed as limitations on the scope of any invention or of what may be claimed, but rather as features of specific embodiments of particular inventions. Certain features that are described in this invention in the context of separate embodiments can also be implemented in combination in a single embodiment. On the other hand, the various features described in the individual embodiments may also be implemented separately in the various embodiments or in any suitable subcombination. Furthermore, although features may be acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination, and the claimed combination may be directed to a subcombination or variation of a subcombination.

Similarly, although operations are depicted in the drawings in a particular order, this should not be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In some cases, multitasking and parallel processing may be advantageous. Moreover, the separation of various system modules and components in the embodiments described above should not be understood as requiring such separation in all embodiments, and it should be understood that the described program components and systems can generally be integrated together in a single software product or packaged into multiple software products.

Thus, particular embodiments of the subject matter have been described. Other embodiments are within the scope of the following claims. In some cases, the actions recited in the claims can be performed in a different order and still achieve desirable results. Furthermore, the processes depicted in the accompanying drawings are not necessarily required to be in the particular order shown, or sequential order, to achieve desirable results. In some implementations, multitasking and parallel processing may be advantageous.

The foregoing description of the preferred embodiments of the invention is not intended to be limiting, but rather to enable any modification, equivalent replacement, improvement or the like to be made within the spirit and principles of the invention.

Claims

1. A hot plug system for PCIE devices, the system comprising:

2. The system of claim 1, wherein the isolation chip comprises a PCIE clock driver, a PCIE repeater, and a general purpose input output isolation chip;

the PCIE clock driver is configured to isolate clock signals between the PCIE bridge chip and the PCIE device during the PCIE device hot-pulling period;

the PCIE repeater is configured to isolate digital signals between the PCIE bridge chip and the PCIE device during the hot-pulling period of the PCIE device;

the general input/output isolation chip is configured to isolate general signals between the PCIE bridge chip and the PCIE device during the hotpull of the PCIE device, where the general signals include the PCIE reset signal and a PCIE device in-place signal.

3. The system of claim 1, wherein the system further comprises:

the shutter is arranged outside the PCIE equipment and used for protecting the PCIE equipment from being interfered by external environments; the shutter is provided with a switch device, and the main board is also provided with a switch detection module and an in-place detection module;

the control chip is further configured to determine that a hot-plug operation for the PCIE device is detected when the switch detection module detects that the switch device is turned on and the in-place detection module detects that the PCIE device is in place;

the control chip is further configured to determine that a hot plug operation for the PCIE device is detected when the switch detection module detects that the switch device is turned off and the in-place detection module detects that the PCIE device is turned from an out-of-place state to an in-place state.

4. A system according to claim 3, wherein the switch detection module is a light sensing detection device and the switch device is a rotary switch; when the rotary switch rotates to an open gear, the light sensing signal detected by the light sensing detection device is changed from 1 to 0; when the rotary switch rotates to the off gear, the light sensing signal detected by the light sensing detection device is changed from 0 to 1.

5. The system of claim 1, wherein the system further comprises a controller configured to control the controller,

the control chip is further configured to close application software associated with the PICE device and offload a file system and a bottom driver associated with the PCIE device in response to the detected hot-pull operation for the PCIE device.

6. The system of claim 1, wherein the system further comprises:

the indicator lamp is used for receiving the light signals of the control chip and displaying light according to the received light signals;

the control chip is further configured to send a red light flashing signal to the indicator light in response to the detected hot-plug operation or hot-plug operation for the PCIE device; in response to detecting that the PCIE device is out of place, sending a turn-off signal to the indicator light; and in response to detecting that the PCIE equipment normally operates, sending a green light normally-on signal to the indicator light.

7. The system of claim 1, wherein the PCIE device is equipped with pin-length air connectors.

8. The hot plug method for the PCIE equipment is characterized by being applied to a control chip on a main board, wherein the main board is connected with the PCIE equipment, a PCIE bridging chip is assembled on the main board, and an isolation chip is assembled between the PCIE bridging chip and the PCIE equipment, and the system comprises:

9. An electronic device, comprising:

a processor;

a memory for storing processor-executable instructions;

wherein the processor implements the method of claim 8 by executing the executable instructions.

10. A computer readable storage medium, on which a computer program is stored, characterized in that the program, when being executed by a processor, implements the steps of the method according to claim 8.