CN117750238A - Comparator, readout circuit and image sensor - Google Patents

Abstract

The invention provides a comparator, a reading circuit and an image sensor, wherein the comparator comprises a first-stage amplifying circuit and a second-stage amplifying circuit, the first-stage amplifying circuit comprises an input amplifying unit, an active load resetting unit and a variable current providing unit, the input amplifying unit is used for amplifying first comparison data and second comparison data, the active load unit is used for outputting driving voltage under the action of the input amplifying unit, the active load resetting unit is used for resetting the active load unit, the variable current providing unit is used for providing variable current for the input amplifying unit and the active load unit, the second-stage amplifying circuit comprises a common source amplifying tube and an output unit, the grid electrode of the common source amplifying tube is connected with the driving voltage so as to be conducted when the driving voltage is in a low level, the output unit is enabled to output a high level, and the output unit is enabled to output a low level when the driving voltage is in a high level, and the power consumption is greatly reduced.

Description

Comparator, readout circuit and image sensor

Technical Field

The present invention relates to the field of image sensors, and in particular, to a comparator, a readout circuit, and an image sensor.

Background

The CMOS image sensor has increasingly higher resolution and frame rate required in various applications, and power consumption and temperature rise, and the problems of increasing dark current noise of pixels, packaging, heat dissipation and the like, can be directly applied to final imaging quality.

In the prior art, a readout circuit of the CMOS image sensor is a framework mainly comprising parallel analog-digital converters, so that the overall power consumption of the CMOS image sensor is reduced, the power consumption of the analog-digital converters is reduced most importantly, the power consumption of the analog-digital converters mainly comes from a comparator, the normal operation of the traditional comparator can be ensured only under the condition of lasting quiescent current, and the larger power consumption is consumed.

Therefore, there is a need to provide a novel comparator, a readout circuit and an image sensor to solve the above-mentioned problems in the prior art.

Disclosure of Invention

The invention aims to provide a comparator, a reading circuit and an image sensor, which reduce power consumption.

In order to achieve the above object, the comparator of the present invention includes a first-stage amplifying circuit and a second-stage amplifying circuit, the first-stage amplifying circuit includes an input amplifying unit for amplifying first comparison data and second comparison data, an active load unit for outputting a driving voltage under the action of the input amplifying unit, an active load reset unit for resetting the active load unit, and a variable current supply unit for supplying a variable current to the input amplifying unit and the active load unit, the second-stage amplifying circuit includes a common source amplifying tube and an output unit, a gate of the common source amplifying tube is connected to the driving voltage to be turned on when the driving voltage is at a low level, the output unit is made to output a high level, and the output unit is made to be turned off when the driving voltage is at a high level, and the output unit is made to output a low level.

Optionally, the variable current providing unit includes a first NMOS tube, a second NMOS tube, and a first capacitor, a drain electrode of the first NMOS tube is connected to the input amplifying unit, a source electrode of the first NMOS tube is connected to a drain electrode of the second NMOS tube and one end of the first capacitor, a source electrode of the second NMOS tube is grounded, another end of the first capacitor is grounded, a gate electrode of the first NMOS tube is connected to a first control signal, a gate electrode of the second NMOS tube is connected to a second control signal, and the first control signal and the second control signal are opposite signals.

Optionally, the input amplifying unit includes a third NMOS tube, a fourth NMOS tube, a first PMOS tube, a second capacitor and a third capacitor, a source of the third NMOS tube and a source of the fourth NMOS tube are all connected with a drain of the first NMOS tube, a drain of the third NMOS tube is connected with a source of the first PMOS tube, a gate of the third NMOS tube is connected with a drain of the first PMOS tube and one end of the second capacitor, the other end of the second capacitor is connected with first comparison data, a drain of the fourth NMOS tube is connected with a source of the second PMOS tube, a gate of the fourth NMOS tube is connected with a drain of the second PMOS tube and one end of the third capacitor, the other end of the third capacitor is connected with second comparison data, and a gate of the first PMOS tube and a gate of the second PMOS tube are connected with a comparator reset signal.

Optionally, the active load unit includes a third PMOS tube and a fourth PMOS tube, where a source of the third PMOS tube and a source of the fourth PMOS tube are both connected to a power supply voltage, a gate of the third PMOS tube is connected to a drain of the third PMOS tube, a drain of the third NMOS tube is connected to a gate of the fourth PMOS tube, and a drain of the fourth PMOS tube is connected to a drain of the fourth NMOS tube and a gate of the source amplifier tube.

Optionally, the active load reset unit includes a fifth PMOS transistor, a sixth PMOS transistor and a fourth capacitor, where a source of the fifth PMOS transistor and a source of the sixth PMOS transistor are both connected to a power supply voltage, a drain of the fifth PMOS transistor is connected to a drain of the third PMOS transistor, a drain of the sixth PMOS transistor is connected to a drain of the fourth PMOS transistor and one end of the fourth capacitor, another end of the fourth capacitor is grounded, and gates of the fifth PMOS transistor and the sixth PMOS transistor are both connected to a third control signal.

Optionally, the output unit includes a fifth NMOS, a sixth NMOS, and a fifth capacitor, where a drain of the fifth NMOS is connected to a drain of the common source amplifying tube, a source of the fifth NMOS is connected to a drain of the sixth NMOS and one end of the fifth capacitor, as an output end of the comparator, the source of the sixth NMOS and the other end of the fifth capacitor are grounded, a gate of the fifth NMOS is connected to a fourth control signal, and a gate of the sixth NMOS is connected to a fifth control signal.

The invention also provides a reading circuit which comprises a counter and the comparator, wherein the output end of the comparator is connected with the input end of the counter.

The invention also provides an image sensor, which comprises a pixel array, a time sequence control module, a decoding driving module, a slope generator, an output module and at least one reading circuit, wherein the pixel array is used for collecting optical signals and converting the optical signals into electric signals; the time sequence control module is used for controlling the working time sequences of the decoding driving module, the slope generator, the reading circuit and the output module; the decoding driving module is used for driving the pixel array, and the slope generator is used for generating a slope signal; the readout circuit is used for converting the electric signal into a digital signal; the output module is used for converting the digital signal into an image and outputting the image.

The invention has the beneficial effects that: the first-stage amplifying circuit comprises an input amplifying unit, an active load resetting unit and a variable current providing unit, wherein the input amplifying unit is used for amplifying first comparison data and second comparison data, the active load unit is used for outputting driving voltage under the action of the input amplifying unit, the active load resetting unit is used for resetting the active load unit, the variable current providing unit is used for providing variable current for the input amplifying unit and the active load unit, the second-stage amplifying circuit comprises a common source amplifying tube and an output unit, the grid electrode of the common source amplifying tube is connected with the driving voltage so as to be conducted when the driving voltage is in a low level, the output unit is enabled to output a high level, and the output unit is enabled to output a low level when the driving voltage is in a high level, so that the power consumption is greatly reduced.

Drawings

FIG. 1 is a block diagram of an image sensor according to some embodiments of the invention;

FIG. 2 is a schematic circuit diagram of a pixel unit according to some embodiments of the invention;

FIG. 3 is a timing diagram of a pixel unit according to some embodiments of the invention;

FIG. 4 is a circuit diagram of a prior art comparator;

FIG. 5 is a timing diagram of the image sensor shown in FIG. 1 using the comparator shown in FIG. 4;

FIG. 6 is a schematic diagram of a comparator according to some embodiments of the invention;

fig. 7 is a timing diagram of the image sensor shown in fig. 1 using the comparator shown in fig. 6.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. Unless otherwise defined, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and the like means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof without precluding other elements or items.

In view of the problems of the prior art, embodiments of the present invention provide an image sensor. Referring to fig. 1, the image sensor includes a pixel array 101, a timing control module 102, a decoding driving module 103, a ramp generator 104, an output module 105, and at least one readout circuit 106, where the pixel array 101 includes a plurality of pixel units for collecting optical signals and converting the optical signals into electrical signals; the timing control module 102 is configured to control operation timings of the decode driving module 103, the ramp generator 104, the readout circuit 106, and the output module 105; the decoding driving module 103 is used for driving the pixel array, and the ramp generator 104 is used for generating a ramp signal; the readout circuit 106 is configured to convert the electrical signal into a digital signal; the output module 105 is configured to convert the digital signal into an image and output the image. The timing control module 102, the decoding driving module 103, the ramp generator 104 and the output module 105 are all conventional in the art, and are not described in detail herein.

Fig. 2 is a schematic circuit diagram of a pixel unit according to some embodiments of the invention. Referring to fig. 2, the pixel unit includes a photodiode PD, a transfer transistor Mtg, a reset transistor mst, an amplifying transistor Msf, and a gate transistor Msel, wherein an anode of the photodiode PD is grounded, a cathode of the photodiode PD is connected to a source of the transfer transistor Mtg, a gate of the transfer transistor Mtg is connected to a transfer signal TX, a drain of the transfer transistor Mtg is connected to a source of the reset transistor mst and a gate of the amplifying transistor Msf, a drain of the reset transistor mst and a drain of the amplifying transistor Msf are both connected to a power supply voltage VDD, a gate of the reset transistor mst is connected to a pixel unit reset signal RX, a source of the amplifying transistor Msf is connected to a drain of the gate transistor Msel, a source of the gate transistor Msel outputs a pixel signal, and a gate of the gate transistor Msel is connected to a gate signal.

FIG. 3 is a timing diagram of a pixel unit according to some embodiments of the invention. Ginseng radixReferring to fig. 2 and 3, the operation timing of the pixel unit is divided into a reset phase Rst, an integration phase Exp, and a signal Read phase Read. In the reset phase Rst, the transfer signal TX and the pixel unit reset signal RX are at high level, the transfer transistor Mtg and the reset transistor Mrst are both turned on, the floating diffusion FD is reset and its level is pulled up to the power supply voltage VDD. After that, the pixel unit reset signal RX, the transfer signal TX become low level, enter the integration stage Exp, and the floating diffusion PD senses light and accumulates electrons. Then, the signal reading stage Read is entered, the strobe signal SEL is at a high level, the pixel unit reset signal RX is at a high level first, the pixel unit reset signal RX is pulled to a low level again after resetting the level of the floating diffusion FD, the transmission signal TX is kept at a low level, and at this time, the amplifying transistor Msf is controlled by the level of the floating diffusion FD and outputs the reset signal VRST. Thereafter, the transmission signal TX is pulled high and electrons on the photodiode PD are transferred to the floating diffusion FD, and the amplifying transistor Msf is controlled by the level of the floating diffusion FD and outputs an integrated signal V _SIG 。V _RST -V _SIG The difference of (a) is the analog voltage corresponding to the photoelectrons on the photodiode PD. Pixel reset signal V _RST Pixel integral signal V _SIG The level of (2) is converted into a digital quantity by a reading circuit and subtracted to obtain the digital quantity actually corresponding to the photoelectrons on the photodiode PD. If the ADC is 12 bits, the ADC reference voltage range is V _REF Final output D _out ＝(V _RST -V _SIG )×2 ¹² /V _REF 。

Referring to fig. 1, the readout circuit includes a counter 1061 and a comparator 1062, and an output terminal of the comparator 1062 is connected to an input terminal of the counter 1061.

Fig. 4 is a circuit diagram of a prior art comparator. Referring to fig. 4, the comparator includes a third NMOS transistor N3, a fourth NMOS transistor N4, a seventh NMOS transistor N7, an eighth NMOS transistor N8, a first PMOS transistor P1, a second PMOS transistor P2, a third PMOS transistor P3, a fourth PMOS transistor P4, a common source amplifier transistor P7, a second capacitor C2, and a third capacitor C3.

Referring to fig. 4, the source of the third NMOS transistor N3 and the source of the fourth NMOS transistor N4 are connected to the drain of the seventh NMOS transistor N7, the drain of the third NMOS transistor N3 is connected to the source of the first PMOS transistor P1, the drain of the third PMOS transistor P3, the gate of the third PMOS transistor P3 and the gate of the fourth PMOS transistor P4, the gate of the third NMOS transistor N3 is connected to the drain of the first PMOS transistor P1 and one end of the second capacitor C2, the other end of the second capacitor C2 is connected to the first comparison data, the drain of the fourth NMOS transistor N4 is connected to the source of the second PMOS transistor P2, the drain of the fourth PMOS transistor P4 and the gate of the common source amplifying transistor P7, the gate of the fourth NMOS transistor N4 is connected to one end of the second PMOS transistor P2, the other gate of the third NMOS transistor C3 is connected to the drain of the second PMOS transistor P3, the other end of the second NMOS transistor C3 is connected to the drain of the second PMOS transistor P1 and the drain of the eighth NMOS transistor CM 7 is connected to the drain of the common source amplifying transistor P7, and the drain of the eighth NMOS transistor CM 7 is connected to the drain of the eighth NMOS transistor CM 7.

Fig. 5 is a timing diagram of the image sensor shown in fig. 1 using the comparator shown in fig. 4. Referring to fig. 5, in the signal reading stage Read, the strobe signal SEL signal is pulled high, the pixel unit reset signal RX is pulled high, and the pixel unit is reset. The comparator reset signal rstn_cm goes low to put the comparator into a reset state. Then the pixel cell reset signal RX changes from high to low and the comparator reset signal rstn_cm changes from low to flat, and the comparator enters a normal operation state. First, when the level of the RAMP signal RAMP starts to fall, the counter 1061 starts counting until the output signal CMO of the comparator is flipped from low level to high level, and the counter 1061 stops counting and stores the current count value CNT. To perform analog-to-digital conversion of the pixel signal, the readout circuit needs to perform the above operation twice, i.e., the RAMP signal RAMP generates twice RAMPs. The first ramp phase (i.e., the "VR" phase in FIG. 5), the sense circuit will determineAnd stores the pixel reset signal V _RST The counter 1061 will count during time t1 and store the count value CN1 corresponding to the time t 1; the second ramp phase (i.e., the "VS" phase of fig. 5), the readout circuit will determine and store the pixel integration signal V _SIG The counter 1061 will count during time t2 and store the count value CN2 corresponding to that time t 2. Final counter 1061 outputs a count difference Δcn=cn2-CN 1 corresponding to V _SIG -V _RST Is a difference in the amount of the difference.

Referring to fig. 4 and 5, en_bias is a BIAS circuit enable signal of the comparator, and when the BIAS circuit enable signal en_bias is at a high level, the BIAS circuit of the comparator converts a reference signal into a BIAS voltage vbn_cm of the comparator, and at this time, the BIAS voltage vbn_cm of the comparator is at a high level. When the BIAS circuit enable signal en_bias is at a low level, the BIAS circuit of the comparator is not enabled, and at this time, the BIAS voltage vbn_cm of the comparator is at a low level.

Referring to fig. 4 and 5, when the bias voltage vbn_cm of the comparator is at a high level, the current flowing through the seventh NMOS transistor N7 is a first quiescent current I _a1 The current flowing through the eighth NMOS transistor N8 is the second quiescent current I _b1 。

Fig. 6 is a circuit diagram of a comparator according to some embodiments of the invention. Referring to fig. 6, the comparator includes a first stage amplification circuit 10621 and a second stage amplification circuit 10622, where the first stage amplification circuit 10621 includes an input amplification unit for amplifying first comparison data and second comparison data, an active load unit for outputting a driving voltage CMO1 under the action of the input amplification unit, an active load reset unit for resetting the active load unit, and a variable current supply unit for supplying a variable current to the input amplification unit and the active load unit, and the second stage amplification circuit 10622 includes a common source amplifier P7 and an output unit, where a gate of the common source amplifier P7 is connected to the driving voltage CMO1 to be turned on when the driving voltage CMO1 is at a low level, and turned off when the driving voltage CMO1 is at a high level, so that the output unit outputs a low level. Specifically, the first comparator data is a RAMP signal RAMP, and the second comparator data is a pixel signal pix_out.

Referring to fig. 6, the variable current supply unit includes a first NMOS N1, a second NMOS N2, and a first capacitor C1, where a drain of the first NMOS N1 is connected to the input amplifying unit, a source of the first NMOS N1 is connected to a drain of the second NMOS N2 and one end of the first capacitor C1, a source of the second NMOS N2 is grounded, another end of the first capacitor C1 is grounded, a gate of the first NMOS N1 is connected to a first control signal SH1, a gate of the second NMOS N2 is connected to a second control signal SHB1, and the first control signal SH1 and the second control signal SHB1 are inverse signals to each other.

Referring to fig. 6, the input amplifying unit includes a third NMOS transistor N3, a fourth NMOS transistor N4, a first PMOS transistor P1, a second PMOS transistor P2, a second capacitor C2, and a third capacitor C3, where the source of the third NMOS transistor N3 and the source of the fourth NMOS transistor N4 are both connected to the drain of the first NMOS transistor N1, the drain of the third NMOS transistor N3 is connected to the source of the first PMOS transistor P1, the gate of the third NMOS transistor N3 is connected to the drain of the first PMOS transistor P1 and one end of the second capacitor C2, the other end of the second capacitor C2 is connected to first comparison data, the drain of the fourth NMOS transistor N4 is connected to the source of the second PMOS transistor P2, the gate of the fourth NMOS transistor N4 is connected to the drain of the second PMOS transistor P2 and one end of the third capacitor C3, the other end of the third capacitor C3 is connected to second comparison data, and the gate of the first NMOS transistor P1 and the second PMOS transistor P2 are connected to the reset gate of the second capacitor P2.

Referring to fig. 6, the active load unit includes a third PMOS transistor P3 and a fourth PMOS transistor P4, where a source of the third PMOS transistor P3 and a source of the fourth PMOS transistor P4 are both connected to the power supply voltage VDD, a gate of the third PMOS transistor P3 is connected to a drain of the third PMOS transistor P3, a drain of the third NMOS transistor N3 and a gate of the fourth PMOS transistor P4, and a drain of the fourth PMOS transistor P4 is connected to a drain of the fourth NMOS transistor N4 and a gate of the source amplifying transistor.

Referring to fig. 6, the active load reset unit includes a fifth PMOS transistor P5, a sixth PMOS transistor P6, and a fourth capacitor C4, where the source of the fifth PMOS transistor P5 and the source of the sixth PMOS transistor P6 are both connected to the power supply voltage VDD, the drain of the fifth PMOS transistor P5 is connected to the drain of the third PMOS transistor P3, the drain of the sixth PMOS transistor P6 is connected to the drain of the fourth PMOS transistor P4 and one end of the fourth capacitor C4, the other end of the fourth capacitor C4 is grounded, and the gate of the fifth PMOS transistor P5 and the gate of the sixth PMOS transistor P6 are both connected to the third control signal SHB2.

Referring to fig. 6, the common source amplifying tube P7 is a PMOS tube, a source of the common source amplifying tube P7 is connected to a power supply voltage VDD, the output unit includes a fifth NMOS tube N5, a sixth NMOS tube N6, and a fifth capacitor C5, a drain of the fifth NMOS tube N5 is connected to a drain of the common source amplifying tube P7, a source of the fifth NMOS tube N5 is connected to a drain of the sixth NMOS tube N6 and one end of the fifth capacitor C5, and is used as an output end of the comparator, a source of the sixth NMOS tube N6 and the other end of the fifth capacitor C5 are grounded, a gate of the fifth NMOS tube N5 is connected to a fourth control signal SE, and a gate of the sixth NMOS tube N6 is connected to a fifth control signal SH2.

Fig. 7 is a timing diagram of the image sensor shown in fig. 1 using the comparator shown in fig. 6. The pixel unit reset signal RX, the transmission signal TX, the gate signal SEL, the comparator reset signal rstn_cm, the RAMP signal RAMP, the comparator output signal CMO, and the count value CNT in fig. 7 are the same as those in fig. 5. Referring to fig. 6 and 7, when the RAMP signal RAMP is raised, the comparator enters a reset zero state, the fifth control signal SH2 becomes high level, the sixth NMOS transistor N6 is turned on, the fifth capacitor C5 is discharged and zero, the second control signal SHB1 becomes high level, the second NMOS transistor N2 is turned on, the first capacitor C1 is discharged and zero, the third control signal SHB2 becomes low level, the fifth PMOS transistor P5 and the sixth PMOS transistor P6 are turned on, the drain voltage CMO1B and the driving voltage CMO1 of the third PMOS transistor P3 are reset to the power supply voltage VDD, at this time, the common source amplifying transistor P7 is turned off, and the comparator output signal CMO is low level. After that, the fifth control signal SH2 becomes low level, the third control signal SHB2 becomes high level, and the comparator enters a normal operation state.

Referring to fig. 6 and 7, before the RAMP signal RAMP starts to fall, the fourth control signal SE is switched from low level to high level, the fifth NMOS transistor N5 is turned on, when the RAMP signal RAMP starts to fall, the first control signal SH1 synchronously generates a pulse signal with a certain period, when the first control signal SH1 is at high level, the first NMOS transistor N1 is turned on, the first stage branch composed of the third NMOS transistor N3, the fourth NMOS transistor N4, the third PMOS transistor P3 and the fourth PMOS transistor P4 charges the first capacitor C1, and charges the potential of the node SA from low level to potential V in half of the clock period, i.e., half of the pulse period of the first control signal SH1 _C ，V _C ＝V _RAMP -(V _TH3 +V _DSAT3 )，V _RAMP For ramp signal voltage, V _TH3 For the threshold voltage, V, of the third NMOS transistor N3 _DSAT3 Is the overdrive voltage of the third NMOS transistor N3. During the high active period of the first pulse period of the first control signal SH1, it is assumed that the highest point voltage of the RAMP signal RAMP is V _top V is then _RAMP ＝V _top V is then _C ＝V _top -(V _TH3 +V _DSAT3 ). During the active low period of the first pulse period of the first control signal SH1, the second control signal SHB1 is at a high level, and the second NMOS transistor N2 is turned on to discharge the voltage of the node SA to 0. In the second pulse period of the first control signal SH1, the potential to which the node SA is charged will be lower than V due to the voltage of the ramp signal being reduced than before _top -(V _TH3 +V _DSAT3 ) The charge and discharge process of the node SA will be repeated in the VR stage, so that the node SA can be charged to V in the last pulse period of the VR stage _bot1 -(V _TH3 +V _DSAT3 )，V _bot1 Is the lowest voltage of the RAMP signal RAMP in the VR stage. In the view of figure 7 of the drawings,△V＝V _TH3 +V _DSAT3 。

referring to fig. 6 and 7, in the VR stage, when the potential of the RAMP signal RAMP is higher than the pixel signal pix_out, the driving voltage CMO1 maintains a high level, and the comparator output signal CMO is low. When the potential of the RAMP signal RAMP gradually drops below the pixel signal pix_out, the driving voltage CMO1 changes from high level to low level, so that the common source amplifier P7 is turned on, so that the drain voltage of the common source amplifier P7 is pulled up, and the comparator output signal CMO is also pulled up due to the conduction of the fifth NMOS transistor N5. Comparator output signal CMO goes from low to high and counter 1061 stops counting.

Referring to fig. 6 and 7, the voltage of the RAMP signal RAMP stops falling and is pulled up to V _top The pulse signal of the first control signal SH1 is stopped and pulled down to a low level. Then, the fourth control signal SE is changed from high to low, the fifth NMOS transistor N5 is turned off, the fifth control signal SH2 is changed from low to high, the sixth NMOS transistor N6 is turned on, and the comparator output signal CMO is pulled low.

Referring to fig. 6 and 7, after the RAMP signal RAMP enters the VS stage, the comparator operates similarly to the VR stage of the RAMP signal RAMP, except that the node SA is charged to a minimum potential V _bot2 -(V _TH3 +V _DSAT3 )，V _bot2 ＜V _bot1 。

Referring to fig. 6 and 7, in VR and VS phases, the RAMP signal RAMP is higher than the pixel signal pix_out, the driving voltage CMO1 is high, the common source amplifying tube P7 is turned off, the driving voltage CMO1 is low, the common source amplifying tube P7 is turned on, the fifth NMOS tube N5 is turned on, the fifth capacitor C5 is charged to the power supply voltage VDD, and then almost no current flows through the fifth capacitor C5, so that dynamic current is generated in each of VR and VS phases on the fifth capacitor C5, the magnitude of which is I _b2 =vdd/(r1+r2), where R1 represents the on-resistance of the common source amplifier P7, and R2 represents the on-resistance of the fifth NMOS transistor N5. The fifth capacitorCharging time T of C5 _C5 Also current I _b2 Is not required, and the maintenance time of the same is not required.

Referring to fig. 6 and 7, the comparator has a current level I at the first stage amplification circuit 10621 at each pulse period of the first control signal SH1 _a2 ＝C1×(△V _a /△t _a )，△V _a For the difference between the highest voltage charged to the first capacitor C1 and the lowest voltage discharged to the first capacitor C1 in each pulse period of the first control signal SH1 (for example, the highest voltage of the first capacitor C1 charged in the first period of the first control signal SH1 is V _bot1 -(V _TH3 +V _DSAT3 ) The lowest voltage of the first capacitor C1 discharged in the first period of the first control signal SH1 is 0, Δv _a ＝V _top -(V _TH3 +V _DSAT3 ))，△t _a For the time of each pulse period of the first control signal SH 1. The current maintaining time of the first stage amplifier 10621 of the comparator is 1 pulse period T of the first control signal SH1 _p =1/fp, where fp is the pulse signal frequency of the first control signal SH1, the higher fp is, the smaller the potential ripple amplitude at the node S is, and the smaller the ripple of the driving voltage CMO1 is, which greatly reduces power consumption compared to a conventional comparator.

While embodiments of the present invention have been described in detail hereinabove, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. It is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention described herein is capable of other embodiments and of being practiced or of being carried out in various ways.

Claims (8)

1. The comparator is characterized by comprising a first-stage amplifying circuit and a second-stage amplifying circuit, wherein the first-stage amplifying circuit comprises an input amplifying unit, an active load resetting unit and a variable current providing unit, the input amplifying unit is used for amplifying first comparison data and second comparison data, the active load unit is used for outputting driving voltage under the action of the input amplifying unit, the active load resetting unit is used for resetting the active load unit, the variable current providing unit is used for providing variable current for the input amplifying unit and the active load unit, the second-stage amplifying circuit comprises a common source amplifying tube and an output unit, the grid electrode of the common source amplifying tube is connected with the driving voltage so as to be conducted when the driving voltage is in a low level, the output unit outputs a high level, and the output unit is turned off when the driving voltage is in a high level, and the output unit outputs a low level.

2. The comparator according to claim 1, wherein the variable current supply unit comprises a first NMOS transistor, a second NMOS transistor, and a first capacitor, a drain of the first NMOS transistor is connected to the input amplifying unit, a source of the first NMOS transistor is connected to a drain of the second NMOS transistor and one end of the first capacitor, a source of the second NMOS transistor is grounded, another end of the first capacitor is grounded, a gate of the first NMOS transistor is connected to a first control signal, a gate of the second NMOS transistor is connected to a second control signal, and the first control signal and the second control signal are inverse signals to each other.

3. The comparator according to claim 2, wherein the input amplifying unit comprises a third NMOS tube, a fourth NMOS tube, a first PMOS tube, a second capacitor and a third capacitor, wherein the source of the third NMOS tube and the source of the fourth NMOS tube are connected to the drain of the first NMOS tube, the drain of the third NMOS tube is connected to the source of the first PMOS tube, the gate of the third NMOS tube is connected to the drain of the first PMOS tube and one end of the second capacitor, the other end of the second capacitor is connected to first comparison data, the drain of the fourth NMOS tube is connected to the source of the second PMOS tube, the gate of the fourth NMOS tube is connected to the drain of the second PMOS tube and one end of the third capacitor, the other end of the third capacitor is connected to second comparison data, and the gates of the first PMOS tube and the second PMOS tube are connected to comparator reset signals.

4. The comparator according to claim 3, wherein the active load unit comprises a third PMOS tube and a fourth PMOS tube, the source of the third PMOS tube and the source of the fourth PMOS tube are both connected to a power supply voltage, the gate of the third PMOS tube is connected to the drain of the third PMOS tube, the drain of the third NMOS tube and the gate of the fourth PMOS tube, and the drain of the fourth PMOS tube is connected to the drain of the fourth NMOS tube and the gate of the source amplifier tube.

5. The comparator according to claim 4, wherein the active load reset unit comprises a fifth PMOS transistor, a sixth PMOS transistor and a fourth capacitor, wherein the source of the fifth PMOS transistor and the source of the sixth PMOS transistor are both connected to a power supply voltage, the drain of the fifth PMOS transistor is connected to the drain of the third PMOS transistor, the drain of the sixth PMOS transistor is connected to the drain of the fourth PMOS transistor and one end of the fourth capacitor, the other end of the fourth capacitor is grounded, and the gate of the fifth PMOS transistor and the gate of the sixth PMOS transistor are both connected to a third control signal.

6. The comparator of claim 1, wherein the output unit includes a fifth NMOS, a sixth NMOS, and a fifth capacitor, the drain of the fifth NMOS is connected to the drain of the common source amplifier, the source of the fifth NMOS is connected to the drain of the sixth NMOS and one end of the fifth capacitor, as the output terminal of the comparator, the source of the sixth NMOS and the other end of the fifth capacitor are grounded, the gate of the fifth NMOS is connected to the fourth control signal, and the gate of the sixth NMOS is connected to the fifth control signal.

7. A read-out circuit comprising a counter and a comparator as claimed in any one of claims 1 to 6, the output of the comparator being connected to the input of the counter.

8. An image sensor comprising a pixel array, a timing control module, a decoding drive module, a ramp generator, an output module, and at least one readout circuit according to claim 7, wherein the pixel array is configured to collect optical signals and convert the optical signals into electrical signals; the time sequence control module is used for controlling the working time sequences of the decoding driving module, the slope generator, the reading circuit and the output module; the decoding driving module is used for driving the pixel array, and the slope generator is used for generating a slope signal; the readout circuit is used for converting the electric signal into a digital signal; the output module is used for converting the digital signal into an image and outputting the image.