CN114025114B - Readout circuit, image sensor, and control method - Google Patents
Readout circuit, image sensor, and control method Download PDFInfo
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- CN114025114B CN114025114B CN202111295610.5A CN202111295610A CN114025114B CN 114025114 B CN114025114 B CN 114025114B CN 202111295610 A CN202111295610 A CN 202111295610A CN 114025114 B CN114025114 B CN 114025114B
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/71—Charge-coupled device [CCD] sensors; Charge-transfer registers specially adapted for CCD sensors
- H04N25/75—Circuitry for providing, modifying or processing image signals from the pixel array
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K21/00—Details of pulse counters or frequency dividers
- H03K21/02—Input circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
- H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude
- H03K5/2472—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude using field effect transistors
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
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Abstract
The invention provides a reading circuit, which comprises at least two switch units, a comparator and a counter, wherein one ends of different switch units are used for receiving different pixel signals, one end of the comparator is connected with the other ends of all switch units, the other end of the comparator is used for receiving ramp signals, the comparator is used for comparing the pixel signals with the ramp signals to output comparison signals, the counter is connected with the output end of the comparator and is used for starting counting according to the ramp signals and stopping counting according to the comparison signals to obtain count values, and then subtracting operation is carried out on the count values to output digital signals, so that the data processing capacity of the reading circuit is improved, and the number of the reading circuits applied to the same image sensor can be reduced to reduce the power consumption of the image sensor. The invention also provides an image sensor and a control method of the readout circuit.
Description
Technical Field
The present invention relates to the field of image sensors, and in particular, to a readout circuit, an image sensor, and a control method.
Background
In a conventional CMOS image sensor (CMOS image sensor, CIS) structure, a single-integration analog-to-digital conversion circuit (Single Slope Analog-to-Digital Converter, SS-ADC) is a main power consumption source, and the SS-ADC is a readout circuit of the CIS. Typically, the current of a column of SS-ADCs is about 5-10 μa, and the comparator is always on during CIS operation. If the specification of the CIS processing image is 1000 columns and 1000 rows, namely 100 ten thousand pixels, the total quiescent current of the comparator is 5-10 mA. If 800 ten thousand pixels are reached, the SS-ADC of 4000 columns is preferred, and the total quiescent current of the comparator reaches 20-40 mA. For low power applications, a quiescent current of 20mA may result in excessive power consumption.
In some special application scenarios, such as high-temperature environments, if the CIS power consumption is too high, the overall heat productivity will increase, and the temperature of the CIS chip will rapidly increase, which will bring about an increase in image noise, which will seriously affect the quality of the image.
Therefore, there is a need to provide a novel readout circuit, an image sensor and a control method to solve the above-mentioned problems in the prior art.
Disclosure of Invention
The invention aims to provide a reading circuit, an image sensor and a control method, so as to reduce power consumption.
To achieve the above object, the readout circuit of the present invention is applied to a CMOS image sensor, and includes:
at least two switch units, one end of each switch unit is used for receiving different pixel signals;
one end of the comparator is connected with the other ends of all the switch units, the other end of the comparator is used for receiving a ramp signal, and the comparator is used for comparing the pixel signal with the ramp signal so as to output a comparison signal; and
and the counter is connected with the output end of the comparator and is used for starting counting according to the ramp signal, stopping counting according to the comparison signal to obtain a count value, and then performing subtraction operation on the count value to output a digital signal.
The reading circuit has the beneficial effects that: the device comprises at least two switch units, wherein one ends of different switch units are used for receiving different pixel signals, one ends of comparators are connected with the other ends of all switch units, the other ends of comparators are used for receiving ramp signals, the comparators are used for comparing the pixel signals with the ramp signals to output comparison signals, and the data processing capacity of the readout circuit is improved by receiving different pixel signals through one ends of the at least two switch units, so that the number of the readout circuits applied to the same image sensor can be reduced, and the power consumption of the image sensor is reduced.
Optionally, the ramp signals include first stage ramp signals with the same number as the switch units and second stage ramp signals with the same number as the switch units, the pixel signals include pixel signals of a first ramp stage and pixel signals of a second ramp stage, the pixel signals of the first ramp stage are all at a high level, the pixel signals of the second ramp stage are all at a low level, the pixel signals of the first ramp stage are in one-to-one correspondence with the first stage ramp signals, and the pixel signals of the second ramp stage are in one-to-one correspondence with the second stage ramp signals. The beneficial effects are that: the ramp signal can be applied to a read-out circuit for receiving different pixel signals, and the comparator is convenient for processing the different pixel signals.
Optionally, the comparator is configured to compare the pixel signal of the first ramp stage with the corresponding first stage ramp signal to output a first comparison signal, and is further configured to compare the pixel signal of the second ramp stage with the corresponding second stage ramp signal to output a second comparison signal. The beneficial effects are that: facilitating the comparators to process different pixel signals.
Optionally, the counter is configured to start counting according to the first stage ramp signal, then stop counting according to the first comparison signal to obtain a first count value, and is further configured to start counting according to the second stage ramp signal, then stop counting according to the second comparison signal to obtain a second count value, and further configured to subtract the second count value from the corresponding first count value to output a digital signal. The beneficial effects are that: the counter can obtain digital signals of different pixel signals after the comparator is convenient to process the different pixel signals.
The present invention also provides an image sensor including:
the pixel array unit is used for outputting pixel signals after sensitization;
the row selection decoding driving unit is connected with the pixel array unit and used for driving the pixel array unit;
the oblique wave generating unit is used for generating oblique wave signals;
at least one readout circuit connected to the pixel array unit and the ramp wave generating unit;
an output signal processing unit connected to the readout circuit to convert the digital signal into an image and output the image;
and the time sequence control unit is connected with the row selection decoding driving unit, the oblique wave generating unit, the reading circuit and the output signal processing unit and is used for sending clock signals to the row selection decoding driving unit, the oblique wave generating unit, the reading circuit and the output signal processing unit.
The beneficial effects of the image sensor are as follows: the readout circuit is adopted, and one end of the readout circuit through at least two switch units receives different pixel signals, so that the data processing capacity of one comparator is improved, the data processing capacity of the readout circuit is improved, the use of the image sensor to the readout circuit can be reduced, and the power consumption is further reduced.
Optionally, the pixel array unit includes at least one pixel unit, the pixel unit includes a first NMOS, a second NMOS, a third NMOS, a fourth NMOS, and a photodiode, where a drain of the first NMOS is connected to a working voltage, a source of the first NMOS is connected to a gate of the second NMOS and a drain of the third NMOS, a gate of the first NMOS is configured to receive a sixth control signal, a source of the third NMOS is connected to a cathode of the photodiode, a gate of the third NMOS is configured to receive a seventh control signal, an anode of the photodiode is grounded, a drain of the second NMOS is connected to a working voltage, a source of the second NMOS is connected to a drain of the fourth NMOS, a gate of the fourth NMOS is configured to receive the first control signal, and a source of the fourth NMOS is configured to output the pixel signal.
Optionally, the pixel array unit further includes at least one column output line, where the column output line is connected to one end of the switching unit in a one-to-one correspondence, and one column output line is connected to at least one pixel unit to receive the pixel signal from the pixel unit. The beneficial effects are that: and different pixel signals are conveniently transmitted to the switch unit and then transmitted to the read-out circuit.
The invention also provides a control method of the readout circuit, which comprises the following steps:
sequentially starting a switch unit to enable one end of a comparator to receive different pixel signals, the other end of the comparator to receive a ramp signal, and the comparator sequentially compares the pixel signals with the ramp signal to output a comparison signal;
the counter starts counting according to the ramp signal and stops counting according to the comparison signal so as to obtain a count value;
the counter performs a subtraction operation on the count value to output a digital signal.
The control method has the beneficial effects that: the switching unit is sequentially turned on, so that one end of the comparator receives different pixel signals, the other end of the comparator receives oblique wave signals, the comparator sequentially compares the pixel signals with the oblique wave signals to output comparison signals, the counter starts counting according to the oblique wave signals and stops counting according to the comparison signals to obtain a count value, the counter performs subtraction operation on the count value to output digital signals, the comparator can process different pixel data, the data processing capacity of the readout circuit is improved, and the number of the readout circuits applied to the same image sensor can be reduced, so that the power consumption of the image sensor is reduced.
Optionally, the ramp signals include the same number of first stage ramp signals as the number of switch units and the same number of second stage ramp signals as the number of switch units. The beneficial effects are that: the ramp signal can be applied to a read-out circuit for receiving different pixel signals, and the comparator is convenient for processing the different pixel signals.
Optionally, the switching unit is turned on in turn, so that one end of the comparator receives different pixel signals, the other end of the comparator receives a ramp signal, and the comparator compares the pixel signals and the ramp signal in turn to output a comparison signal, including:
the switching unit is sequentially turned on in a first sequence, so that one end of the comparator sequentially receives pixel signals in different first oblique wave stages, the other end of the comparator receives the first oblique wave signals, and the comparison unit sequentially compares the pixel signals in the first oblique wave stages with the corresponding first oblique wave signals to output first comparison signals, wherein the pixel signals in the first oblique wave stages are all in high level. The beneficial effects are that: the comparator is facilitated to complete the operation of the first ramp stage.
Optionally, the switching unit is turned on in turn, so that one end of the comparator receives different pixel signals, the other end of the comparator receives a ramp signal, and the comparator compares the pixel signals and the ramp signal in turn to output a comparison signal, and the method further includes:
the switch units are sequentially turned on in a second sequence, so that one end of the comparator sequentially receives pixel signals with different second ramp phases, the other end of the comparator receives the second-phase ramp signals, and the comparator sequentially compares the pixel signals of the second ramp phases with the corresponding second-phase ramp signals to output second comparison signals, wherein the pixel signals of the second ramp phases are all in low level. The beneficial effects are that: facilitating the comparator to complete the second ramp stage.
Optionally, the counter starts counting according to the ramp signal, stops counting according to the comparison signal to obtain a count value, and includes:
the counter starts counting according to the first stage ramp wave signal and then stops counting according to the first comparison signal so as to obtain a first count value;
and the counter starts counting according to the second stage ramp signal and then stops counting according to the second comparison signal so as to obtain a second count value.
Optionally, the counter performs a subtraction operation on the count value to output a digital signal, including:
the counter subtracts the second count value from the corresponding first count value to output a digital signal.
Optionally, the first order and the second order are completely opposite. The beneficial effects are that: the adjustment of the control switch at one time can be reduced, and the control flow is simplified.
Drawings
FIG. 1 is a schematic circuit diagram of an image sensor according to some embodiments of the invention;
FIG. 2 is a schematic circuit diagram of a pixel unit according to some embodiments of the invention;
FIG. 3 is a timing diagram of a pixel unit according to some embodiments of the invention;
FIG. 4 is a flow chart of a method of controlling a read-out circuit according to some embodiments of the invention;
FIG. 5 is a timing diagram of an image sensor according to the prior art;
fig. 6 is a timing diagram of an image sensor according to some embodiments of the invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present invention more apparent, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention. Unless otherwise defined, technical or scientific terms used herein should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. As used herein, the word "comprising" and the like means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof without precluding other elements or items.
In view of the problems of the prior art, embodiments of the present invention provide an image sensor. Referring to fig. 1, the image sensor 100 includes a pixel array unit 101, a row selection decoding driving unit 103, a ramp wave generating unit 104, at least one readout circuit 102, an output signal processing unit 105, and a timing control unit 106.
Referring to fig. 1, the pixel array unit 101 is configured to output a pixel signal after sensing light; the row selection decoding driving unit 103 is connected with the pixel array unit 101 and is used for driving the pixel array unit 101; the ramp wave generating unit 104 is configured to generate a ramp wave signal; the readout circuits 102 are connected to the pixel array unit 102 and the ramp wave generation unit 104; the output signal processing unit 105 is connected to the readout circuit 102 to convert the digital signal into an image and output; the timing control unit 106 is connected to the row selection decoding driving unit 103, the ramp wave generating unit 104, the readout circuit 102, and the output signal processing unit 105, and is configured to transmit clock signals to the row selection decoding driving unit 103, the ramp wave generating unit 104, the readout circuit 102, and the output signal processing unit 105. The pixel array unit 101 includes at least one pixel unit 1011, the row selection decoding driving unit 103, the ramp wave generating unit 104, the output signal processing unit 105 and the timing control unit 106 are all known in the art, and will not be described in detail herein.
FIG. 2 is a schematic circuit diagram of a pixel cell according to some embodiments of the invention. Referring to fig. 2, the pixel unit 1011 includes a first NMOS tube 10111, a second NMOS tube 10112, a third NMOS tube 10113, a fourth NMOS tube 10114, and a photodiode 10115, wherein a drain electrode of the first NMOS tube 10114 is connected to an operating voltage, a source electrode of the first NMOS tube 10111 is connected to a gate electrode of the second NMOS tube 10112 and a drain electrode of the third NMOS tube 10113, a gate electrode of the first NMOS tube 10111 is used for receiving a first control signal, a source electrode of the third NMOS tube 10113 is connected to a cathode electrode of the photodiode 10115, a gate electrode of the third NMOS tube 10113 is used for receiving a second control signal, an anode electrode of the photodiode 10115 is grounded, a drain electrode of the second NMOS tube 10114 is connected to an operating voltage, a source electrode of the second NMOS tube 10112 is connected to a drain electrode of the fourth NMOS tube 10114, a gate electrode of the fourth NMOS tube 10114 is used for receiving a third control signal, and a source electrode of the fourth NMOS tube 10114 is used for outputting a pixel signal.
In some embodiments, the pixel array unit further includes at least one column output line, the column output line is connected to one end of the switching unit in a one-to-one correspondence, and one column output line is connected to at least one pixel unit to receive the pixel signal from the pixel unit. Specifically, the column output line is connected to the source of the fourth NMOS transistor to receive the pixel signal from the pixel unit.
FIG. 3 is a timing diagram of a pixel unit according to some embodiments of the invention. Referring to fig. 2 and 3, rst denotes a reset stage of the pixel unit 1011, exp denotes an exposure stage of the pixel unit 1011, read denotes a signal Read stage of the pixel unit 1011, SEL denotes a third control signal applied to the gate of the fourth NMOS transistor 10114, RX denotes a first control signal applied to the gate of the first NMOS transistor 10111, and TX denotes a second control signal applied to the gate of the third NMOS transistor 10113.
Referring to fig. 2 and 3, the third control signal SEL maintains a low level, the first control signal RX maintains a high level, and the second control signal TX transitions from a high level to a low level while the pixel unit 1011 is in the reset stage. The first control signal RX and the second control signal TX are both high-point flat, the first NMOS transistor 10111 and the third NMOS transistor 10113 are both turned on, and the potential of the floating node 10115 is pulled up to the working voltage VDD to complete the reset.
Referring to fig. 2 and 3, after both the first control signal RX and the second control signal TX are turned to low level, the pixel unit 1011 enters the exposure stage from the reset stage, the third control signal SEL maintains low level, the first control signal RX maintains low level, and the second control signal TX maintains low level. The first control signal RX and the second control signal TX are both low-point flat, the first NMOS tube 10111 and the third NMOS tube 10113 are both turned off, and the photodiode 10115 senses light and generates photoelectrons in proportion to illumination intensity.
Referring to fig. 2 and 3, after the third control signal SEL is changed from low level to high level, the fourth NMSO tube 10114 is turned on, the pixel unit 1011 enters the signal reading stage from the exposure stage, the first control signal RX is changed from low level to high level to reset the floating node 10118, at this time, the second NMOS tube 10112 is controlled by the potential of the floating node, and the source electrode of the fourth NMOS tube 10114 outputs a first reset potential, and then the first control signal RX is changed from high level to low level; the second control signal TX changes from low level to high level, the photoelectrons in the photodiode 10115 are transferred to the floating node 10118, at this time, the second NMOS transistor 10112 is controlled by the potential of the floating node 10118, and the source of the fourth NMOS transistor 10114 outputs a second reset potential, and then the second control signal TX changes from high level to low level.
In some embodiments, the readout circuit includes at least two switch units, a comparator and a counter, where one end of the switch unit is connected to the column output line in a one-to-one correspondence manner, and is used for receiving different pixel signals; one end of the comparator is connected with the other ends of all the switch units, the other end of the comparator is used for receiving a ramp signal, and the comparator is used for comparing the pixel signal with the ramp signal so as to output a comparison signal; the counter is connected with the output end of the comparator and is used for starting counting according to the ramp signal, stopping counting according to the comparison signal to obtain a count value, and then performing subtraction operation on the count value to output a digital signal.
Referring to fig. 1, the readout circuit 102 includes two switch units, a comparator 1021 and a counter 1022, the two switch units are a first switch unit 1023 and a second switch unit 1024, one end of the first switch unit 1023 is connected to a first column output line and is used for receiving a first pixel signal, the second switch unit 1024 is connected to a second column output line and is used for receiving a second pixel signal, the other end of the first switch unit 1023 and the other end of the second switch unit 1024 are both connected to a positive input end of the comparator 1021, a negative input end of the comparator 1021 is used for receiving a ramp signal, and the counter 1022 is connected to an output end of the comparator 1021.
Referring to fig. 1, the number of comparators 1021 of the readout circuit 102 is reduced by half compared with the prior art, so that the static power consumption of the readout circuit 102 is reduced by half, but the operating frequency of the readout circuit 102 is doubled compared with the operating frequency of the prior art, the operating frequency of the counter 1022 is increased, so that the dynamic power consumption of the counter 1022 is increased, but the dynamic power consumption of the counter 1022 is not increased proportionally, and the counter 1022 is not always in an operating state, so that the average power consumption caused by the dynamic power consumption of the counter 1022 is increased by about 10%, and the overall power consumption of the readout circuit 102 is reduced by about 40% due to the halving of the static power consumption of the readout circuit 102.
In some embodiments, the ramp signals include first stage ramp signals having the same number as the switch units and second stage ramp signals having the same number as the switch units, the pixel signals include pixel signals of a first ramp stage and pixel signals of a second ramp stage, the pixel signals of the first ramp stage are all at a high level, the pixel signals of the second ramp stage are all at a low level, the pixel signals of the first ramp stage are in one-to-one correspondence with the first stage ramp signals, and the pixel signals of the second ramp stage are in one-to-one correspondence with the second stage ramp signals. The first stage oblique wave signals are connected end to end, the second stage oblique wave signals are connected end to end, and the tail of the last first stage oblique wave signal is connected with the head of the first second stage oblique wave signal.
In some embodiments, the comparator is configured to compare the pixel signal of the first ramp stage with the corresponding first stage ramp signal to output a first comparison signal, and is further configured to compare the pixel signal of the second ramp stage with the corresponding second stage ramp signal to output a second comparison signal.
In some embodiments, the counter is configured to start counting according to the first stage ramp signal, then stop counting according to the first comparison signal to obtain a first count value, and further configured to start counting according to the second stage ramp signal, then stop counting according to the second comparison signal to obtain a second count value, and further configured to subtract the second count value from the corresponding first count value to output a digital signal.
Fig. 4 is a flowchart of a control method of a readout circuit according to some embodiments of the invention. Referring to fig. 4, the control method includes the steps of:
s1: sequentially starting a switch unit to enable one end of a comparator to receive different pixel signals, the other end of the comparator to receive a ramp signal, and the comparator sequentially compares the pixel signals with the ramp signal to output a comparison signal;
s2: the counter starts counting according to the ramp signal and stops counting according to the comparison signal so as to obtain a count value;
s3: the counter performs a subtraction operation on the count value to output a digital signal.
In some embodiments, the ramp signals include the same number of first stage ramp signals as the number of switching units and the same number of second stage ramp signals as the number of switching units.
In some embodiments, the switching unit is turned on sequentially, so that one end of the comparator receives different pixel signals, the other end of the comparator receives a ramp signal, and the comparator compares the pixel signals and the ramp signal sequentially to output a comparison signal, including: the switching unit is sequentially turned on in a first sequence, so that one end of the comparator sequentially receives pixel signals in different first oblique wave stages, the other end of the comparator receives the first oblique wave signals, and the comparison unit sequentially compares the pixel signals in the first oblique wave stages with the corresponding first oblique wave signals to output first comparison signals, wherein the pixel signals in the first oblique wave stages are all in high level.
In some embodiments, the switching unit is turned on sequentially, so that one end of the comparator receives different pixel signals, the other end of the comparator receives a ramp signal, and the comparator compares the pixel signals and the ramp signal sequentially to output a comparison signal, and further includes: the switch units are sequentially turned on in a second sequence, so that one end of the comparator sequentially receives pixel signals with different second ramp phases, the other end of the comparator receives the second-phase ramp signals, and the comparator sequentially compares the pixel signals of the second ramp phases with the corresponding second-phase ramp signals to output second comparison signals, wherein the pixel signals of the second ramp phases are all in low level.
In some embodiments, the pixel signals include a pixel signal of a first ramp stage and a pixel signal of a second ramp stage.
In some embodiments, the counter starts counting according to the ramp signal, stops counting according to the comparison signal to obtain a count value, and includes: the counter starts counting according to the first stage ramp wave signal and then stops counting according to the first comparison signal so as to obtain a first count value; and the counter starts counting according to the second stage ramp signal and then stops counting according to the second comparison signal so as to obtain a second count value.
In some embodiments, the counter decrements the count value to output a digital signal, comprising: the counter subtracts the second count value from the corresponding first count value to output a digital signal.
In some embodiments, the first order and the second order are completely opposite, so that one adjustment of the switch unit can be reduced, and the control flow is simplified.
Fig. 5 is a timing diagram of an image sensor in the prior art. Referring to fig. 5, rx denotes a first control signal applied to the gate of the first NMOS transistor 10111, TX denotes a second control signal applied to the gate of the third NMOS transistor 10113, SEL denotes a third control signal applied to the gate of the fourth NMOS transistor 10114, rst_cm denotes a reset control signal of the comparator, RAMP denotes a RAMP signal, pix_out denotes a pixel signal, cm_out denotes a comparison signal output from the comparator, CNT denotes a count value of the counter, VR denotes a first RAMP stage, and VS denotes a second RAMP stage.
Referring to fig. 5, when the RAMP signal RAMP is higher than the pixel data pix_out, the comparison signal cm_out output from the comparator is at a low level; when the RAMP signal RAMP is lower than the pixel data pix_out, the comparison signal cm_out output from the comparator is at a high level.
Referring to fig. 5, in the first RAMP stage VR and the second RAMP stage VS, the RAMP signal RAMP is changed from a high level to a low level, and the level of the RAMP signal RAMP is higher than the pixel signal pix_out and then lower than the pixel signal pix_out.
Fig. 6 is a timing diagram of an image sensor according to some embodiments of the invention. Referring to fig. 1, 2 and 6, rx represents a first control signal applied to the gate of the first NMOS 10111, TX represents a second control signal applied to the gate of the third NMOS 10113, SEL represents a third control signal applied to the gate of the fourth NMOS 10114, S (0) represents a first switch control signal controlling the first switch 1023 to be turned on or off, S (1) represents a second switch control signal controlling the second switch 1024 to be turned on or off, rst_cm represents a reset control signal of the comparator, RAMP represents the RAMP signal, RAMP1 represents a first stage RAMP signal, RAMP2 represents a second stage RAMP signal, RAMP3 represents a first stage RAMP signal, RAMP4 represents a second stage RAMP signal, pix_out (0) represents a first pixel signal transmitted by the first column output line 1022, pix_out (1) represents a second column VR signal VR1 represents a second output of the comparator, and a counter 1022, and each of the two stages VR1 represents a counter 1022, and each of which represents a first stage of the counter 1022, a second stage VR1 represents a counter 1022, a first stage and a counter 1022, and a second stage 2 represents a counter 1022, and a counter 2 of the two stages, respectively, and a counter 2 represents the two stages of the counter 1022.
Referring to fig. 1 and 6, when RX is changed from high to low, SEL is changed from low to high, rst_cm is changed from low to high, and rst_cm is changed from high, S (0) is changed from low to high, that is, the first switching unit 1023 is turned on, then S (0) is changed from high to low, that is, the first switching unit 1023 is turned off, S (1) is changed from low to high, that is, the second switching unit 1024 is turned on, and then S (1) is changed from high to low, that is, the second switching unit 1024 is turned off, to achieve the reset of the first pixel signal and the second pixel signal.
Referring to fig. 1 and 6, in the first ramp stage, S (0) is changed from low level to high level, that is, the first switch unit 1023 is turned on, S (1) is maintained at low level, the readout circuit converts the reset signal of the first pixel signal, after entering the VR1 stage, when the first ramp signal starts to change from high level to low level, the counter 1022 starts counting until pix_out (0) is greater than the first ramp signal, that is, when the comparison signal output by the comparator is high level, the counter 1022 stops counting to obtain the first count value of the VR1 stage. Wherein the reset signal of the first pixel signal is a high level portion of the first pixel signal.
Referring to fig. 1 and 6, in the second first ramp stage, S (0) is changed from high to low, that is, the first switching unit 1023 is turned off, S (0) is maintained at low, S (1) is changed from low to high, that is, the second switching unit 1024 is turned on, S (1) is maintained at high, the readout circuit converts the reset signal of the second pixel signal, and after entering the VR2 stage, the counter 1022 starts counting when the second first ramp signal starts to change from high to low until pix_out (1) is greater than the second first ramp signal, that is, the comparison signal output by the comparator is high, and the counter 1022 stops counting to obtain the first count value of the VR2 stage. Wherein the reset signal of the second pixel signal is a high level portion of the second pixel signal.
Referring to fig. 1 and 6, in the first second ramp stage, after TX changes from high to low, S (0) maintains low, S (1) maintains high, the readout circuit converts the integral signal of the second pixel signal, after entering the VS2 stage, when the first second ramp signal starts to change from high to low, the counter 1022 starts to count until pix_out (1) is greater than the first second ramp signal, that is, when the comparison signal output by the comparator is high, the counter 1022 stops counting to obtain the second count value of the VS2 stage. Wherein the integrated signal of the second pixel signal is a low level portion of the second pixel signal.
Referring to fig. 1 and 6, in the second ramp stage, S (0) is changed from low level to high level, that is, the first switch is turned on, S (0) is maintained at high level, S (1) is changed from high level to low level, that is, the second switch unit 1024 is turned off, S (1) is maintained at low level, the readout circuit converts the integrated signal of the first pixel signal, and after entering the VS1 stage, the counter 1022 starts counting when the second ramp signal starts to change from high level to low level until pix_out (0) is greater than the second ramp signal, that is, when the comparison signal output by the comparator is high level, the counter 1022 stops counting to obtain the second count value of the VS1 stage. Wherein the integrated signal of the first pixel signal is a low level portion of the first pixel signal.
In some embodiments, the counter subtracts the first count value of VR1 stage from the second count value of VS1 stage to obtain a digital signal of pix_out (0); the counter subtracts the first count value of the VR2 stage from the second count value of the VS2 stage to obtain a digital signal of pix_out (1).
While embodiments of the present invention have been described in detail hereinabove, it will be apparent to those skilled in the art that various modifications and variations can be made to these embodiments. It is to be understood that such modifications and variations are within the scope and spirit of the present invention as set forth in the following claims. Moreover, the invention described herein is capable of other embodiments and of being practiced or of being carried out in various ways.
Claims (14)
1. A readout circuit for use in a CMOS image sensor, comprising:
at least two switch units, one end of each switch unit is used for receiving different pixel signals;
one end of the comparator is connected with the other ends of all the switch units, the other end of the comparator is used for receiving a ramp signal, and the comparator is used for comparing the pixel signal with the ramp signal so as to output a comparison signal; and
and the counter is connected with the output end of the comparator and is used for starting counting according to the ramp signal, stopping counting according to the comparison signal to obtain a count value, and then performing subtraction operation on the count value to output a digital signal.
2. The readout circuit according to claim 1, wherein the ramp signals include first-stage ramp signals of the same number as the switching units and second-stage ramp signals of the same number as the switching units, the pixel signals include pixel signals of a first ramp stage and pixel signals of a second ramp stage, the pixel signals of the first ramp stage are all at a high level, the pixel signals of the second ramp stage are all at a low level, the pixel signals of the first ramp stage are in one-to-one correspondence with the first-stage ramp signals, and the pixel signals of the second ramp stage are in one-to-one correspondence with the second-stage ramp signals.
3. The readout circuit of claim 2, wherein the comparator is configured to compare the pixel signal of the first ramp stage with the corresponding first stage ramp signal to output a first comparison signal, and wherein the comparator is further configured to compare the pixel signal of the second ramp stage with the corresponding second stage ramp signal to output a second comparison signal.
4. A readout circuit according to claim 3, wherein the counter is configured to start counting according to the first stage ramp signal and then stop counting according to the first comparison signal to obtain a first count value, the counter is further configured to start counting according to the second stage ramp signal and then stop counting according to the second comparison signal to obtain a second count value, and the counter is further configured to subtract the second count value and the corresponding first count value to output a digital signal.
5. An image sensor, comprising:
the pixel array unit is used for outputting pixel signals after sensitization;
the row selection decoding driving unit is connected with the pixel array unit and used for driving the pixel array unit;
the oblique wave generating unit is used for generating oblique wave signals;
at least one readout circuit according to any one of claims 1 to 4, each connected to the pixel array unit and the ramp wave generating unit;
an output signal processing unit connected to the readout circuit to convert the digital signal into an image and output the image;
and the time sequence control unit is connected with the row selection decoding driving unit, the oblique wave generating unit, the reading circuit and the output signal processing unit and is used for sending clock signals to the row selection decoding driving unit, the oblique wave generating unit, the reading circuit and the output signal processing unit.
6. The image sensor of claim 5, wherein the pixel array unit comprises at least one pixel unit, the pixel unit comprises a first NMOS tube, a second NMOS tube, a third NMOS tube, a fourth NMOS tube, and a photodiode, a drain electrode of the first NMOS tube is connected to an operating voltage, a source electrode of the first NMOS tube is connected to a gate electrode of the second NMOS tube and a drain electrode of the third NMOS tube, a gate electrode of the first NMOS tube is used for receiving a sixth control signal, a source electrode of the third NMOS tube is connected to a cathode of the photodiode, a gate electrode of the third NMOS tube is used for receiving a seventh control signal, an anode of the photodiode is grounded, a drain electrode of the second NMOS tube is connected to an operating voltage, a source electrode of the second NMOS tube is connected to a drain electrode of the fourth NMOS tube, a gate electrode of the fourth NMOS tube is used for receiving the first control signal, and a source electrode of the fourth NMOS tube is used for outputting the pixel signal.
7. The image sensor of claim 6, wherein the pixel array unit further comprises at least one column output line, the column output line being connected to one end of the switching unit in one-to-one correspondence, one of the column output lines being connected to at least one of the pixel units to receive the pixel signal from the pixel unit.
8. A control method of the readout circuit according to claim 1, comprising:
sequentially starting a switch unit to enable one end of a comparator to receive different pixel signals, the other end of the comparator to receive a ramp signal, and the comparator sequentially compares the pixel signals with the ramp signal to output a comparison signal;
the counter starts counting according to the ramp signal and stops counting according to the comparison signal so as to obtain a count value;
the counter performs a subtraction operation on the count value to output a digital signal.
9. The control method according to claim 8, wherein the ramp signals include first-stage ramp signals of the same number as the switching units and second-stage ramp signals of the same number as the switching units.
10. The control method according to claim 9, wherein the sequentially turning on the switching units so that one end of the comparator receives different pixel signals and the other end of the comparator receives a ramp signal, the comparator sequentially comparing the pixel signals and the ramp signal to output a comparison signal, comprising:
the switching unit is sequentially turned on in a first sequence, so that one end of the comparator sequentially receives pixel signals in different first oblique wave stages, the other end of the comparator receives the first oblique wave signals, and the comparator sequentially compares the pixel signals in the first oblique wave stages with the corresponding first oblique wave signals to output first comparison signals, wherein the pixel signals in the first oblique wave stages are all in high level.
11. The control method according to claim 10, wherein the switching units are turned on in order to cause one end of a comparator to receive different pixel signals, the other end of the comparator to receive a ramp signal, the comparator comparing the pixel signals and the ramp signal in order to output a comparison signal, further comprising:
the switch units are sequentially turned on in a second sequence, so that one end of the comparator sequentially receives pixel signals with different second ramp phases, the other end of the comparator receives the second-phase ramp signals, and the comparator sequentially compares the pixel signals of the second ramp phases with the corresponding second-phase ramp signals to output second comparison signals, wherein the pixel signals of the second ramp phases are all in low level.
12. The control method according to claim 11, wherein the counter starts counting according to the ramp signal, stops counting according to the comparison signal to obtain a count value, comprising:
the counter starts counting according to the first stage ramp wave signal and then stops counting according to the first comparison signal so as to obtain a first count value;
and the counter starts counting according to the second stage ramp signal and then stops counting according to the second comparison signal so as to obtain a second count value.
13. The control method according to claim 12, wherein the counter performs a subtraction operation on the count value to output a digital signal, comprising:
the counter subtracts the second count value from the corresponding first count value to output a digital signal.
14. The control method of claim 11, wherein the first order and the second order are diametrically opposed.
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