CN115379144A - Data transmission circuit and image sensor - Google Patents

Abstract

The invention provides a data transmission circuit and an image sensor, wherein the data transmission circuit comprises: the device comprises a first data transmission module and a second data transmission module, wherein the first data transmission module comprises at least one data transmission unit; the data transmission unit comprises a data transmission line and a driving unit, and the driving unit is connected with the output ends of the counters in the image sensor at the same counting bit through the data transmission line; the driving unit acquires the output of the counting bits through the data transmission line, converts the output of the counting bits into a current difference inside the driving unit, and converts the current difference into a voltage difference. The driving unit in the data transmission circuit provided by the invention can quickly convert the output of the counting bits into the current difference in the driving unit and immediately amplify and output the current difference, and the requirements of high resolution and high frame rate data transmission of an image sensor can be met.

Description

Data transmission circuit and image sensor

Technical Field

The invention relates to the technical field of image sensor design and application, in particular to a data transmission circuit and an image sensor.

Background

CMOS Image Sensors (CIS) have been widely used in The imaging fields of video, surveillance, industrial manufacturing, automobiles, home appliances, and The like. The main-stream readout circuit structure of the CIS is a readout circuit mainly based on a column-level single-slope analog-to-digital converter (ADC), so as to ensure that the CIS has sufficient conversion accuracy and speed under reasonable power consumption. With the increasing resolution and frame rate of CIS applications, after the column ADCs read out data simultaneously, the data need to be transmitted out of the column ADCs through a data transmission circuit in a short time for further data processing. The data transmission circuit needs to complete all the ADC data in all the rows in a shorter row period, which is very high in requirements on the driving capability and frequency of the data transmission circuit. In the CIS with higher resolution, the number of parallel ADC columns is large, and when ADC data is input to the bus for serial output, the parasitic capacitance and resistance time constant of the bus are relatively large, power consumption consumed by bus driving is large, and the maximum transmission frequency is limited.

The present technical solution, for example, a chinese patent with an authorization publication number of CN108184081B, discloses a middle and high speed data transmission readout circuit and readout channel used in a CMOS image sensor, which is formed by connecting a high speed data transmission circuit behind each column of pixels, and including a sample hold circuit, a column ADC circuit, and a column LVDS output circuit. The circuit carries out analog-to-digital conversion on a reset signal and a photo-generated signal output by each row of pixels through the pipeline sampling and holding circuit and the column ADC circuit, and then outputs the signals to the column LVDS circuit through the pipeline latching and holding circuit, so that high-speed data transmission is realized. In the method, in the digital signal output stage, the enable of each column of tri-state gates is controlled by the multi-path selection circuit to output the column signals to the corresponding LVDS channels, so that the risk of column signal output delay exists, and the column signal reading time sequence is increased.

Therefore, the present application provides a data transmission circuit and an image sensor, which can achieve a high frequency transmission rate on the premise of having high driving capability.

Disclosure of Invention

The invention provides a data transmission circuit and an image sensor, and aims to solve the technical problem that the highest frequency of data transmission of the image sensor with higher resolution requirement cannot meet the actual requirement.

In a first aspect, the present invention provides a data transmission circuit applied to an image sensor, wherein the image sensor includes at least one counter, and the data transmission circuit includes: the device comprises a first data transmission module and a second data transmission module, wherein the first data transmission module comprises at least one data transmission unit; the data transmission unit comprises a data transmission line and a driving unit, and the driving unit is connected with the output ends of the counters in the image sensor, which have the same counting bit, through the data transmission line; the driving unit acquires the output of the counting bit through the data transmission line, converts the output of the counting bit into a current difference inside the driving unit, and converts the current difference into a voltage difference; the driving unit is further connected to the second data transmission module, the second data transmission module is configured to convert the voltage difference into a logic level signal, and the logic level signal is used to generate image information.

The beneficial effects are that: the driving unit in the data transmission circuit provided by the invention can quickly convert the output of the counting bit into the current difference in the driving unit and immediately amplify and output the current difference, and the requirements of high resolution and high frame rate data transmission of an image sensor can be met.

Optionally, the data transmission line includes a first line and a second line, one input end of the driving unit is electrically connected to the first output end of the counting bit through the first line, another input end of the driving unit is electrically connected to the second output end of the same counting bit through the second line, and the first output end and the second output end output signals in opposite directions. The beneficial effects are that: one input end of the driving unit is electrically connected with a first output end of the counting bit through the first line, the other input end of the driving unit is electrically connected with a second output end of the same counting bit through the second line, and the directions of signals output by the first output end and the second output end are opposite, so that when the counting bit is output, two signals acquired by the driving unit are different inevitably, and the driving unit can rapidly respond to the difference.

Optionally, the driving unit includes a first amplifying unit and a second amplifying unit, the first amplifying unit is connected to the first output end of the counting bit through the first line, the second amplifying unit is electrically connected to the second output end of the counting bit through the second line, the first output end is one of the normal phase output end or the reverse phase output end of the counting bit, and the second output end is the other of the normal phase output end or the reverse phase output end of the counting bit. The beneficial effects are that: the first amplifying unit and the second amplifying unit respectively amplify the received signals so as to strengthen the difference and obtain an accurate output result of the driving unit.

Optionally, when the first output terminal is a positive phase output terminal of the count bit and the second output terminal is an inverted phase output terminal of the count bit, the first amplification unit includes a first amplifier and a second amplifier, and the second amplification unit includes a third amplifier, a fourth amplifier and a mirror unit; the first amplifier includes: a first P-type transistor, a second P-type transistor, a first N-type transistor, and a second N-type transistor, the second amplifier comprising: a third P-type transistor, a fourth P-type transistor, and a third N-type transistor; the third amplifier includes: a fifth P-type transistor, a sixth P-type transistor, a fourth N-type transistor, and a fifth N-type transistor, the fourth amplifier comprising: the mirror unit comprises a seventh P-type transistor, an eighth P-type transistor and a sixth N-type transistor; the source electrode of the first P-type transistor is respectively connected with a first power supply, the source electrode of the second P-type transistor and the source electrode of the third P-type transistor, the grid electrode of the first P-type transistor is respectively connected with the grid electrode of the second P-type transistor and the drain electrode of the first P-type transistor, and the drain electrode of the first P-type transistor is connected with the drain electrode of the first N-type transistor; the drain electrode of the second P-type transistor is connected with the drain electrode of the second N-type transistor; the grid electrode of the third P-type transistor is connected with the grid electrode of the fourth P-type transistor, and the drain electrode of the third P-type transistor is respectively connected with one end of a first circuit, the drain electrode of the third N-type transistor, the grid electrode of the third N-type transistor and the grid electrode of the first N-type transistor; the drain electrode of the fourth P-type transistor is respectively connected with the drain electrode of the eighth N-type transistor; the source electrode of the first N-type transistor is grounded; the grid electrode of the second N-type transistor is used for receiving a first bias voltage, the first bias voltage is used for providing stable bias current for the driving unit, and the source electrode of the second N-type transistor is grounded; the source electrode of the third N-type transistor is grounded; a source electrode of the fifth P-type transistor is connected with a second power supply, a source electrode of a sixth P-type transistor and a source electrode of the seventh P-type transistor respectively, a grid electrode of the fifth P-type transistor is connected with a grid electrode of the sixth P-type transistor and a drain electrode of the fifth P-type transistor respectively, and a drain electrode of the fifth P-type transistor is connected with a drain electrode of the fifth N-type transistor; the drain electrode of the sixth P-type transistor is connected with the drain electrode of the fifth N-type transistor; a gate of the seventh P-type transistor is connected to a gate of the eighth P-type transistor, and a drain of the seventh P-type transistor is connected to one end of the second line, a drain of the sixth N-type transistor, a gate of the sixth N-type transistor, and a gate of the fourth N-type transistor, respectively; the drain electrode of the eighth P-type transistor is respectively connected with the drain electrode of the seventh N-type transistor, the grid electrode of the seventh N-type transistor and the grid electrode of the eighth N-type transistor; the source electrode of the fourth N-type transistor is grounded; the grid electrode of the fifth N-type transistor is used for receiving a second bias voltage, and the source electrode of the fifth N-type transistor is grounded; the source electrode of the sixth N-type transistor is grounded; the source electrode of the seventh N-type transistor is grounded; and the source electrode of the eighth N-type transistor is grounded.

Optionally, the first line includes at least one branch, and a ninth N-type transistor and a tenth N-type transistor are disposed on each of the branches of the first line; the second circuit comprises at least one branch, and an eleventh N-type transistor and a twelfth N-type transistor are respectively arranged on each branch of the second circuit; the source electrode of the ninth N-type transistor is grounded, the grid electrode of the ninth N-type transistor is used for receiving the positive phase output of the corresponding counting bit, and the drain electrode of the ninth N-type transistor is connected with the source electrode of the tenth N-type transistor; the grid electrode of the tenth N-type transistor and the grid electrode of the twelfth N-type transistor are used for receiving column selection signals, and the column selection signals are used for sequentially controlling the ninth N-type transistor and the eleventh N-type transistor on the corresponding branches to be switched on or switched off; drains of the tenth N-type transistors on all the branches of the first line are connected, and further connected to a drain of the third P-type transistor and a drain of the third N-type transistor; the source electrode of the eleventh N-type transistor is grounded, the grid electrode of the eleventh N-type transistor is used for receiving the inverted output of the corresponding counting bit, and the drain electrode of the eleventh N-type transistor is connected with the source electrode of the twelfth N-type transistor; drains of the twelfth N-type transistors on all the branches of the second line are connected to each other, and a drain of the seventh P-type transistor and a drain of the sixth N-type transistor are also connected to each other.

Optionally, the second data transmission module includes at least one signal shaping module, and each signal shaping module is connected to one driving unit, respectively, and is configured to perform two-time phase inversion processing on the voltage difference.

Optionally, the signal shaping module includes a first inverter and a second inverter, an input end of the first inverter is connected to a drain of the fourth P-type transistor and a drain of the eighth N-type transistor, respectively, an input end of the first inverter is used to obtain the voltage difference, an input end of the second inverter is connected to an output end of the first inverter, and an output of the second inverter is used to generate the image information.

Optionally, the number of the data transmission units is set according to the number of the counting bits of the counter, and the number of the branches on the first line and the number of the branches on the second line are set according to the number of the counter.

Optionally, the number of the data transmission units is equal to the number of the counting bits of the counter, and both the number of the branches on the first line and the number of the branches on the second line are equal to the number of the counter.

In a second aspect, the present invention provides an image sensor comprising: a pixel array, an analog-to-digital converter, a data transmission circuit according to any one of the first aspect, a ramp generator, a decoding driving module, and a timing control module; the pixel array is used for collecting optical signals and converting the optical signals into electric signals; the decoding driving module is connected with the pixel array and used for controlling the output of the pixel units of each row in the pixel array; the analog-to-digital converter is respectively connected with the pixel units in one column in the pixel array and the slope generator and is used for outputting according to the output of the pixel units and the output of the slope generator; the data transmission circuit is used for converting the output of the analog-to-digital converter into a logic level signal; the time sequence control module is respectively connected with the decoding driving module, the ramp generator and the analog-to-digital converter and is used for controlling the working time sequences of the decoding driving module, the ramp generator and the analog-to-digital converter.

The beneficial effects are that: the image sensor provided by the invention can meet the requirement on high frame rate data transmission of the image sensor through the quick response of the data transmission circuit to counting bit output.

Drawings

FIG. 1 is a circuit diagram of a four-transistor pixel unit;

FIG. 2 is a schematic diagram of a working timing sequence of a four-transistor pixel unit;

FIG. 3 is a schematic diagram of a readout circuit of an image sensor;

FIG. 4 is a timing diagram illustrating the operation of a readout circuit of an image sensor;

FIG. 5 is a schematic diagram of an embodiment of a data transmission circuit provided in the present invention;

FIG. 6 is a schematic diagram of another embodiment of a data transmission circuit provided in the present invention;

fig. 7 is a schematic diagram illustrating an operation timing sequence of a column selection signal of the driving unit according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present application are described below with reference to the drawings in the embodiments of the present application. In the description of the embodiments of the present application, the terminology used in the following embodiments is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in the specification of this application and the appended claims, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, such as "one or more", unless the context clearly indicates otherwise. It should also be understood that in the following embodiments of the present application, "at least one", "one or more" means one or more than two (including two). The term "and/or" is used to describe an association relationship that associates objects, meaning that three relationships may exist; for example, a and/or B, may represent: a exists singly, A and B exist simultaneously, and B exists singly, wherein A and B can be singular or plural. The character "/" generally indicates that the former and latter associated objects are in an "or" relationship.

Reference throughout this specification to "one embodiment" or "some embodiments," or the like, means that a particular feature, structure, or characteristic described in connection with the embodiment is included in one or more embodiments of the present application. Thus, appearances of the phrases "in one embodiment," "in some embodiments," "in other embodiments," or the like, in various places throughout this specification are not necessarily all referring to the same embodiment, but rather "one or more but not all embodiments" unless specifically stated otherwise. The terms "comprising," "including," "having," and variations thereof mean "including, but not limited to," unless expressly specified otherwise. The term "coupled" includes direct coupling and indirect coupling, unless otherwise noted. "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

In the embodiments of the present application, the words "exemplary" or "such as" are used herein to mean serving as an example, instance, or illustration. Any embodiment or design described herein as "exemplary" or "such as" is not necessarily to be construed as preferred or advantageous over other embodiments or designs. Rather, use of the word "exemplary" or "such as" is intended to present concepts related in a concrete fashion.

Fig. 1 shows a circuit structure of a CIS standard four-tube pixel unit, which is commonly applied to a CIS in a row exposure mode and comprises a photodiode PD, a transfer transistor Mtg, a reset transistor Mrst, an amplifying transistor Msf and a row selection transistor Msel. The photodiode PD senses light and generates photoelectrons proportional to the intensity of light. The transfer transistor Mtg functions to transfer photoelectrons within the photodiode PD. When the TX signal is high, the transfer transistor Mtg is turned on, and transfers the photoelectrons in the photodiode PD to the floating node FD. The reset transistor Mrst is operative to reset the potential of the floating node FD when the RX signal is high. When SEL is at a high potential, the row selection transistor Msel is turned on, the amplification transistor Msf, the row selection transistor Msel and a current source to the ground form a path, and the amplification transistor Msf follows the change of the potential of the floating node FD and is finally output from the output bus PIX _ OUT.

Fig. 2 is a timing sequence of the four-tube pixel unit shown in fig. 1, which is divided into reset (Rst), exposure (Exp), and signal Read (Read). In the Rst stage, the TX signal and the RX signal are at "high" potentials, the transfer transistor Mtg and the reset transistor Mrst are both turned on, the floating point FD is reset and its potential is pulled up to the power supply voltage VDD. Then, the RX signal and the TX signal become "low" potential, and the Exp stage is entered, and the floating-point PD senses light and accumulates electrons. Then, entering a Read stage, SEL is at a high potential, the RX signal is at a high potential, after the potential of the floating point FD is reset, the RX signal is pulled to a low potential, the TX signal is kept at a low potential, and the source follower transistor Msf is controlled by the floating point FDThe floating point FD potential and the reset potential VRST are output through the output bus PIX _ OUT. Thereafter, the TX signal is pulled to "high" potential and transfers electrons on the photodiode PD to the floating point FD, at which time the source follower transistor Msf is controlled by the potential of the floating point FD and outputs the integration potential VSIG through the output bus PIX _ OUT. The difference of VRST-VSIG is the amount of analog voltage corresponding to the photoelectrons on the photodiode PD. The VRST and VSIG potentials are converted to digital values by an analog-to-digital converter (ADC) circuit and subtracted to obtain digital values corresponding to the photoelectrons on the photodiode PD. If the ADC is 12 bits and the reference voltage range of the ADC is VREF, the final output is DOUT = (VRST-VSIG) × 2 ¹² /VREF。

Fig. 3 is a schematic structural diagram of a CIS readout circuit, which includes a pixel array, an ADC, a ramp generator, a timing control module, a decoding driving module, and an output signal processing module. The pixel array is composed of a plurality of pixel units P as shown in fig. 1. The ADC includes a comparator and a counter. The pixel array is read out in a ROW-by-ROW mode, and the specific sequence is ROW (0), ROW (1), 8230, ROW (k-1) and ROW (k). And k is a positive integer. Each column in the pixel array is connected with an output bus respectively, and the output buses are PIX _ OUT (0), PIX _ OUT (1) and/or 8230, PIX _ OUT (n-1) and PIX _ OUT (n). The output ends of the output buses are connected with the ADC module. The ADC module is composed of a comparator and a counter, the comparator compares an output pixel signal with a RAMP signal RAMP, and the comparison result determines the count value of the counter. The ADC module also respectively judges the VRST and the VSIG potentials and converts the VRST-VSIG difference value into a digital quantity to be output.

Fig. 4 is a corresponding operation timing sequence of the CIS readout circuit shown in fig. 3, i.e., a Read phase of the timing sequence shown in fig. 2. In the timing shown in fig. 4, the Read phase is entered, SEL is pulled to the "high" potential, RX is the "high" potential, and the pixel cell is reset. RST _ CM is a comparator reset control signal, and RST _ CM is also pulled to a high potential to reset the comparators in all ADC blocks. Then RX, RST _ CM change from "high" to "low" potential, ADC module enters normal working state. The working process of the ADC module comprises two processes of comparison and counting, firstly, when the RAMP potential starts to fall, the counter CNT starts to count until the comparator signal is turned from low potential to high potential, the counter CNT stops counting and stores the current count value. To complete the analog-to-digital conversion of the pixel signal, the ADC module needs to perform the above operations twice, that is, two ramp waves are generated as a reference of the ADC module. In the first ramp stage (i.e. the "VR" stage in fig. 4), the ADC module will determine and store the reset potential VRST, and the counter CNT will count within the time t1 and store a count value CN1 corresponding to the time t 1; during the second ramp phase (i.e. the "VS" phase of fig. 4), the ADC module will determine and store the reset potential VSIG, and the counter CNT will count and store a count value CN2 corresponding to the t2 time period within the time t 2. The final counter CNT will output a count difference Δ CN = CN2-CN1, corresponding to the difference amount of VSIG-VRST.

To describe the data transmission circuit provided in the present application in more detail, it is explained herein with reference to fig. 5. The counter used in the embodiments of the present application is a column counter, and the data transmission circuit is applied to an image sensor including N +1 column counters, where N is an integer and is responsible for converting data output by a column ADC into serial data. The column counter includes 12 count bits, and the number of data transfer units is equal to the number of count bits of the column counter. The data transmission circuit shown in fig. 5 includes: 12 data transmission lines, 12 driving units, which are respectively a first data transmission line, a second data transmission line, a twelfth data transmission line, and 9 data transmission lines, which are omitted from illustration, including a first driving unit SA _ D0, a second driving unit SA _ D1, and a twelfth driving unit SA _ D11. The count bits of each column counter are a first count bit D0, a second count bit D1, a twelfth count bit D11, and 9 count bits not shown are omitted, respectively. The counting bits occupying the same counting position in the corresponding column counter are the same counting bit, the output end of the same counting bit is connected with the same data transmission line, and the data transmission line is connected with the output ends of different counting bits. For example, the first counting bit D0 in each column counter is connected to the first data transmission line, and is connected to the first driving unit SA _ D0 through the first data transmission line; the second counting bit D1 in each column counter is connected with the second data transmission line and is connected with a second driving unit SA _ D1 through the second data transmission line; the twelfth counting bit D11 in each column counter is connected to the twelfth data transmission line and connected to the twelfth driving unit SA _ D11 through the twelfth data transmission line. The comparator of the column ADC compares the output of the pixel unit corresponding to N +1 output buses such as the output bus PIX _ OUT (0), the output bus PIX _ OUT (1), the output bus PIX _ OUT (N-1), the output bus PIX _ OUT (N), and the omitted portion not shown in fig. 5 with the RAMP signal RAMP, and the column counter acquires the output of the comparator. The data of the counting bits transmitted by each data transmission line are sequentially transmitted through the control of the corresponding driving unit so as to carry out subsequent data processing, and image information is generated.

The driving units mentioned in the above embodiments are differential inputs, so each data transmission line includes two lines, namely a first line and a second line, and the directions of signals transmitted by the first line and the second line are opposite. Specifically, as shown in fig. 6, the data transmission line includes a first line 601 and a second line 602, the second data transmission module 604 includes a first inverter INV1 and a second inverter INV2, the driving unit 603 includes a first amplifying unit and a second amplifying unit, and the second data transmission module 604 includes a first inverter INV1 and a second inverter INV2. The first inverter INV1 and the second inverter INV2 are used for performing inversion processing on the voltage difference twice, so as to realize the function of converting an analog signal into a digital signal.

With continued reference to fig. 6, the first amplification unit includes a first amplifier and a second amplifier, and the second amplification unit includes a third amplifier, a fourth amplifier, and a mirroring unit. The first amplifier includes: a first P-type transistor P1, a second P-type transistor P2, a first N-type transistor N1, and a second N-type transistor N2, the second amplifier including: a third P-type transistor P3, a fourth P-type transistor P4, and a third N-type transistor N3. The third amplifier includes: a fifth P-type transistor P5, a sixth P-type transistor P6, a fourth N-type transistor N4, and a fifth N-type transistor N5, the fourth amplifier including: a seventh P-type transistor P7, an eighth P-type transistor P8, and a sixth N-type transistor N6, and the mirror unit includes a seventh N-type transistor N7 and an eighth N-type transistor N8.

The source electrode of the first P-type transistor P1 is respectively connected with a first power supply VDD1, the source electrode of the second P-type transistor P2 and the source electrode of the third P-type transistor P3, the grid electrode of the first P-type transistor P1 is respectively connected with the grid electrode of the second P-type transistor P2 and the drain electrode of the first P-type transistor P1, and the drain electrode of the first P-type transistor P1 is connected with the drain electrode of the first N-type transistor N1; the drain electrode of the second P-type transistor P2 is connected with the drain electrode of the second N-type transistor N2; the gate of the third P-type transistor P3 is connected to the gate of the fourth P-type transistor P4, and the drain of the third P-type transistor P3 is respectively connected to one end of the first line 601, the drain of the third N-type transistor N3, the gate of the third N-type transistor N3, and the gate of the first N-type transistor N1; the drain electrode of the fourth P-type transistor P4 is respectively connected with the drain electrode of the eighth N-type transistor N8 and the input end of the first inverter INV 1; the source electrode of the first N-type transistor N1 is grounded; the grid electrode of the second N-type transistor N2 is used for receiving a first bias voltage VB1, and the source electrode of the second N-type transistor N2 is grounded; the source of the third N-type transistor N3 is grounded.

A source of the fifth P-type transistor P5 is connected to the second power supply VDD2, a source of the sixth P-type transistor P6, and a source of the seventh P-type transistor P7, respectively, a gate of the fifth P-type transistor P5 is connected to a gate of the sixth P-type transistor P6 and a drain of the fifth P-type transistor P5, respectively, and a drain of the fifth P-type transistor P5 is connected to a drain of the fifth N-type transistor N5; the drain electrode of the sixth P-type transistor P6 is connected with the drain electrode of the fifth N-type transistor N5; a gate of the seventh P-type transistor P7 is connected to a gate of the eighth P-type transistor P8, and a drain of the seventh P-type transistor P7 is respectively connected to one end of the second line 602, a drain of the sixth N-type transistor N6, a gate of the sixth N-type transistor N6, and a gate of the fourth N-type transistor N4; the drain electrode of the eighth P-type transistor P8 is connected to the drain electrode of the seventh N-type transistor N7, the gate electrode of the seventh N-type transistor N7 and the gate electrode of the eighth N-type transistor N8 respectively; the source electrode of the fourth N-type transistor N4 is grounded; the grid electrode of the fifth N-type transistor N5 is used for receiving a second bias voltage VB2, and the source electrode of the fifth N-type transistor N5 is grounded; the source electrode of the sixth N-type transistor N6 is grounded; the source electrode of the seventh N-type transistor is grounded; and the source electrode of the eighth N-type transistor is grounded. In some embodiments, the first bias voltage VB1 and the second bias voltage VB2 are the same.

The number of branches on the first line and the number of branches on the second line are set according to the number of counters. Optionally, the number of the data transmission units is equal to the number of the counting bits of the counter, and both the number of the branches on the first line and the number of the branches on the second line are equal to the number of the counter. When the image sensor has N +1 column counters, the first line 601 includes N +1 branches, each of which is provided with 2N-type transistors, i.e., a ninth N-type transistor MS1 and a tenth N-type transistor MS2, respectively, and the second line 602 includes N +1 branches, each of which is provided with 2N-type transistors, i.e., an eleventh N-type transistor MS3 and a twelfth N-type transistor MS4, respectively. The source of the ninth N-type transistor MS1 is grounded, the gate of the ninth N-type transistor MS1 is configured to receive the non-inverted output D0 (0) of the corresponding counter first count bit D0, and the drain of the ninth N-type transistor MS1 is connected to the source of the tenth N-type transistor MS 2; the gates of the tenth N-type transistor MS2 and the twelfth N-type transistor MS4 are both configured to receive column selection signals (e.g., a column selection signal COL _ SEL (0), a column selection signal COL _ SEL (1), and a column selection signal COL _ SEL (N) shown in fig. 6), and by controlling the state of each column selection signal, the ninth N-type transistor MS1 and the eleventh N-type transistor MS3 on the corresponding branches are sequentially controlled to be turned on or off. As shown in fig. 7, when one of the column select signals is a high pulse, the remaining column select signals are all at a low level. With reference to fig. 6, when the column selection signal is high pulse in sequence, the ninth N-type transistor MS1 and the eleventh N-type transistor MS3 on the corresponding branches are controlled to be turned on in sequence, and when the column selection signal is low level, the ninth N-type transistor MS1 and the eleventh N-type transistor MS3 on the corresponding branches are turned off. The drains of the tenth N-type transistors MS2 on the N +1 branches of the first line 601 are connected to each other, and are further connected to the drain of the third P-type transistor and the drain of the third N-type transistor N3. The source of the eleventh N-type transistor MS3 is grounded, the gate of the eleventh N-type transistor MS3 is configured to receive the inverted output D0_ b (0) of the corresponding counter first counting bit D0, and the drain of the eleventh N-type transistor MS3 is connected to the source of the twelfth N-type transistor MS 4; the drains of the twelfth N-type transistors MS4 on the N +1 branches of the second line 602 are connected to each other, and are further connected to the drain of the seventh P-type transistor P7 and the drain of the sixth N-type transistor N6.

The seventh N-type transistor N7 and the eighth N-type transistor N8 function to mirror the current 1 of the eighth P-type transistor P8 to the branch where the fourth P-type transistor P4 and the eighth P-type transistor N8 are located. The second N-type transistor N2 is a current source transistor and is controlled by the fixed first bias voltage VB to provide a fixed bias current for the entire driving unit. When data does not start to be transmitted, all column selection signals are low, the ninth N-type transistor MS1 and the eleventh N-type transistor MS3 on the corresponding branch are both switched off, no current exists on the first line and the second line, the current IU on the third P-type transistor P3 is equal to the current IB on the sixth N-type transistor N6, and the magnitude of the quiescent current of each branch in the driving unit is determined by the current flowing through the second N-type transistor N2 and the width-to-length ratio of each transistor.

Referring to fig. 6, when the column selection signal COL _ SEL (0) IS high, the positive phase output D0 (0) of the first counting bit D0 of the corresponding counter IS high, and the negative phase output D0_ b (0) of the first counting bit D0 of the corresponding counter IS low, the branch where the ninth N-type transistor MS1 and the tenth N-type transistor MS2 are located IS turned on, the branch where the eleventh N-type transistor MS3 and the twelfth N-type transistor MS4 are located IS turned off, a current IS0_ P IS added to one end IP of the first line, and the current flows from the IP end to the ground GND through the ninth N-type transistor MS1 and the tenth N-type transistor MS 2. At this time, the potential at the IP terminal IS slightly pulled low, then the potential at the node F between the first N-type transistor and the third N-type transistor becomes low, the current IU at the third P-type transistor P3 IS slightly larger than the current IB at the third N-type transistor N3, and there IS a difference between the current IU and the current IB, the first bias voltage VB input by the first amplifier IS unchanged, and the potential at the node F becomes low, so that the potential at the node a between the drain of the second P-type transistor and the drain of the second N-type transistor IS pulled low, so that the gate-source voltage of the third P-type transistor P3 increases, the current IU at the third P-type transistor P3 further increases, and the current IS0_ P continues to increase, at this time, the third P-type transistor P3 pulls the potential at the terminal IP of the first circuit high again, and finally reaches a stable state. Because the mirror ratio of the third P-type transistor P3 and the fourth P-type transistor P4 is 1:1, the current on the third P-type transistor P3 and the current on the fourth P-type transistor P4 are equal, and the current IU on the fourth P-type transistor P4 will also reach a stable value. At this time, since the one end IN of the second line has no current, the current ID of the eighth N-type transistor N8 is smaller than the current IU flowing through the fourth P-type transistor P4, so the signal SAOUT of the output of the driving unit is pulled high, and finally the output logic level signal DOUT is driven to be high by the first inverter INV1 and the second inverter INV2.

Similarly, if the column selection signal COL _ SEL (0) is high, the positive phase output D0 (0) of the first counting bit D0 of the corresponding counter is at a low level, and the negative phase output D0_ b (0) of the first counting bit D0 of the corresponding counter is at a high level, the branch where the ninth N-type transistor MS1 and the tenth N-type transistor MS2 are located is turned off, the branch where the eleventh N-type transistor MS3 and the twelfth N-type transistor MS4 are located is turned on, so that the current ID of the eighth N-type transistor N8 is finally greater than the current IU flowing through the fourth P-type transistor P4, the signal SAOUT of the output of the driving unit is low, and the corresponding logic level signal DOUT is also low. The above process is the data transmission of the 0 th column of the first count bit D0. And so on, so does the transmission process of other bits. Because the proposed driving unit only needs to judge the difference of the input node currents, the response speed is high, if the driving of the first line and the second line is replaced by a voltage comparator, the time constant is large due to the fact that parasitic resistance and parasitic capacitance on one end IP of the first line and one end IN node of the second line are large, voltage swing of one end IP of the first line and one end IN node of the second line are very small, and therefore the response speed of the voltage comparator is very low. The driving unit provided by the application has the advantages that even though the parasitic resistance and the parasitic capacitance of the input ends are large, the two input ends can be detected and immediately amplified and output as long as a certain current difference exists.

Therefore, the data transmission circuit provided by the application can meet the requirements of CIS high-resolution and high-frame rate data transmission.

Based on the data transmission circuit provided in the above embodiment, the present invention provides an image sensor, including: the pixel array, the analog-to-digital converter, the data transmission circuit according to any one of the embodiments, the ramp generator, the decoding driving module and the timing control module; the pixel array is used for collecting optical signals and converting the optical signals into electric signals; the decoding driving module is connected with the pixel array and used for controlling the output of the pixel units of each row in the pixel array; the analog-to-digital converter is respectively connected with the pixel units in one column in the pixel array and the slope generator and is used for outputting according to the output of the pixel units and the output of the slope generator; the data transmission circuit is used for converting the output of the analog-to-digital converter into a logic level signal; the time sequence control module is respectively connected with the decoding driving module, the ramp generator and the analog-to-digital converter and is used for controlling the working time sequences of the decoding driving module, the ramp generator and the analog-to-digital converter. The image sensor provided by the invention can meet the requirement of high frame rate data transmission of the image sensor through the rapid response of the data transmission circuit to the output of the counting bit.

The above description is only a specific implementation of the embodiments of the present application, but the scope of the embodiments of the present application is not limited thereto, and any changes or substitutions within the technical scope disclosed in the embodiments of the present application should be covered within the scope of the embodiments of the present application. Therefore, the protection scope of the embodiments of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A data transmission circuit, applied to an image sensor including at least one counter, comprising: the device comprises a first data transmission module and a second data transmission module, wherein the first data transmission module comprises at least one data transmission unit;

the data transmission unit comprises a data transmission line and a driving unit, and the driving unit is connected with the output ends of the counters in the image sensor, which have the same counting bit, through the data transmission line;

the driving unit acquires the output of the counting bit through the data transmission line, converts the output of the counting bit into a current difference inside the driving unit, and converts the current difference into a voltage difference;

the driving unit is further connected to the second data transmission module, the second data transmission module is configured to convert the voltage difference into a logic level signal, and the logic level signal is used to generate image information.

2. The data transmission circuit according to claim 1, wherein the data transmission line includes a first line and a second line, one input terminal of the driving unit is electrically connected to a first output terminal of the count bit through the first line, and the other input terminal of the driving unit is electrically connected to a second output terminal of the same count bit through the second line, and the first output terminal and the second output terminal output signals in opposite directions.

3. The data transmission circuit according to claim 2, wherein the driving unit includes a first amplification unit and a second amplification unit, the first amplification unit is connected to the first output terminal of the count bit through the first line, the second amplification unit is electrically connected to the second output terminal of the count bit through the second line, the first output terminal is one of a positive phase output terminal or an inverted phase output terminal of the count bit, and the second output terminal is the other of the positive phase output terminal or the inverted phase output terminal of the count bit.

4. The data transmission circuit according to claim 3, wherein when the first output terminal is a non-inverting output terminal of the count bit and the second output terminal is an inverting output terminal of the count bit, the first amplification unit includes a first amplifier and a second amplifier, and the second amplification unit includes a third amplifier, a fourth amplifier, and a mirror unit;

the first amplifier includes: a first P-type transistor, a second P-type transistor, a first N-type transistor, and a second N-type transistor, the second amplifier comprising: a third P-type transistor, a fourth P-type transistor, and a third N-type transistor; the third amplifier includes: a fifth P-type transistor, a sixth P-type transistor, a fourth N-type transistor, and a fifth N-type transistor, the fourth amplifier comprising: the mirror unit comprises a seventh P-type transistor, an eighth P-type transistor and a sixth N-type transistor;

the source electrode of the first P-type transistor is respectively connected with a first power supply, the source electrode of the second P-type transistor and the source electrode of the third P-type transistor, the grid electrode of the first P-type transistor is respectively connected with the grid electrode of the second P-type transistor and the drain electrode of the first P-type transistor, and the drain electrode of the first P-type transistor is connected with the drain electrode of the first N-type transistor; the drain electrode of the second P-type transistor is connected with the drain electrode of the second N-type transistor; the grid electrode of the third P-type transistor is connected with the grid electrode of the fourth P-type transistor, and the drain electrode of the third P-type transistor is respectively connected with one end of a first circuit, the drain electrode of the third N-type transistor, the grid electrode of the third N-type transistor and the grid electrode of the first N-type transistor; the drain electrode of the fourth P-type transistor is respectively connected with the drain electrode of the eighth N-type transistor; the source electrode of the first N-type transistor is grounded; the grid electrode of the second N-type transistor is used for receiving a first bias voltage, the first bias voltage is used for providing stable bias current for the driving unit, and the source electrode of the second N-type transistor is grounded; the source electrode of the third N-type transistor is grounded;

a source electrode of the fifth P-type transistor is connected with a second power supply, a source electrode of a sixth P-type transistor and a source electrode of the seventh P-type transistor respectively, a grid electrode of the fifth P-type transistor is connected with a grid electrode of the sixth P-type transistor and a drain electrode of the fifth P-type transistor respectively, and a drain electrode of the fifth P-type transistor is connected with a drain electrode of the fifth N-type transistor; the drain electrode of the sixth P-type transistor is connected with the drain electrode of the fifth N-type transistor; a gate of the seventh P-type transistor is connected to a gate of the eighth P-type transistor, and a drain of the seventh P-type transistor is connected to one end of a second line, a drain of the sixth N-type transistor, a gate of the sixth N-type transistor, and a gate of the fourth N-type transistor, respectively; the drain electrode of the eighth P-type transistor is respectively connected with the drain electrode of the seventh N-type transistor, the grid electrode of the seventh N-type transistor and the grid electrode of the eighth N-type transistor; the source electrode of the fourth N-type transistor is grounded; the grid electrode of the fifth N-type transistor is used for receiving a second bias voltage, and the source electrode of the fifth N-type transistor is grounded; the source electrode of the sixth N-type transistor is grounded; the source electrode of the seventh N-type transistor is grounded; and the source electrode of the eighth N-type transistor is grounded.

5. The data transmission circuit according to claim 4, wherein the first line comprises at least one branch, and a ninth N-type transistor and a tenth N-type transistor are arranged on each branch of the first line; the second line comprises at least one branch, and an eleventh N-type transistor and a twelfth N-type transistor are respectively arranged on each branch of the second line;

the source electrode of the ninth N-type transistor is grounded, the grid electrode of the ninth N-type transistor is used for receiving the positive phase output of the corresponding counting bit, and the drain electrode of the ninth N-type transistor is connected with the source electrode of the tenth N-type transistor; the grid electrode of the tenth N-type transistor and the grid electrode of the twelfth N-type transistor are used for receiving column selection signals, and the column selection signals are used for sequentially controlling the ninth N-type transistor and the eleventh N-type transistor on the corresponding branches to be switched on or switched off;

the drains of the tenth N-type transistors on all the branches of the first line are connected, and are also connected with the drain of the third P-type transistor and the drain of the third N-type transistor; the source electrode of the eleventh N-type transistor is grounded, the grid electrode of the eleventh N-type transistor is used for receiving the inverted output of the corresponding counting bit, and the drain electrode of the eleventh N-type transistor is connected with the source electrode of the twelfth N-type transistor; drains of the twelfth N-type transistors on all the branches of the second line are connected to each other, and a drain of the seventh P-type transistor and a drain of the sixth N-type transistor are also connected to each other.

6. The data transmission circuit according to claim 7, wherein the second data transmission module comprises at least one signal shaping module, and each signal shaping module is connected to one of the driving units respectively and is configured to perform two inversion processes on the voltage difference.

7. The data transmission circuit of claim 6, wherein the signal shaping module comprises a first inverter and a second inverter, an input terminal of the first inverter is connected to a drain of the fourth P-type transistor and a drain of the eighth N-type transistor, respectively, an input terminal of the first inverter is used for obtaining the voltage difference, an input terminal of the second inverter is connected to an output terminal of the first inverter, and an output terminal of the second inverter is used for generating the image information.

8. The data transmission circuit according to claim 7, wherein the number of the data transmission units is set according to the number of the count bits of the counter, and the number of the branches on the first line and the number of the branches on the second line are set according to the number of the counter.

9. The data transmission circuit according to claim 8, wherein the number of the data transmission units is equal to the number of the counting bits of the counter, and the number of the branches on the first line and the number of the branches on the second line are equal to the number of the counters.

10. An image sensor, comprising: a pixel array, an analog-to-digital converter, a data transmission circuit according to any one of claims 1 to 9, a ramp generator, a decode drive module, a timing control module;

the pixel array is used for collecting optical signals and converting the optical signals into electric signals;

the decoding driving module is connected with the pixel array and used for controlling the output of the pixel units of each row in the pixel array;

the analog-to-digital converter is respectively connected with the pixel units in one column in the pixel array and the slope generator and is used for outputting according to the output of the pixel units and the output of the slope generator;

the data transmission circuit is used for converting the output of the analog-to-digital converter into a logic level signal;

the time sequence control module is respectively connected with the decoding driving module, the ramp generator and the analog-to-digital converter and is used for controlling the working time sequences of the decoding driving module, the ramp generator and the analog-to-digital converter.

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