CN117747542A - Method for dry etching polyimide layer, rewiring layer and preparation method thereof - Google Patents
Method for dry etching polyimide layer, rewiring layer and preparation method thereof Download PDFInfo
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Abstract
The application discloses a method for dry etching of a polyimide layer, a preparation method of a rewiring layer and the rewiring layer, and relates to the technical field of semiconductors. A method of dry etching a polyimide layer comprising: coating a photosensitive material and forming a first predetermined pattern layer; performing first etching to transfer the first preset pattern layer to the polyimide layer and remove the photosensitive material; coating photoresist and forming a second preset pattern layer; performing second etching to transfer the second preset pattern layer to the polyimide layer; and removing the photoresist. The method and the device can at least solve the problem that byproducts which are difficult to clean up are generated in the RDL wiring preparation process.
Description
Technical Field
The application belongs to the technical field of semiconductors, and particularly relates to a method for dry etching a polyimide layer, a preparation method of a rewiring layer and the rewiring layer.
Background
Since the 21 st century, emerging technologies such as 5G, VR, AR, artificial intelligence, internet of things, high performance computing, autopilot, and big data have found that various thin, lightweight, portable mobile electronic devices are coming into the field of view of people and create tremendous application demands. To meet the current development demands, semiconductor chips are mainly developed toward the continuation and expansion of moore's law. However, as transistor dimensions approach physical atomic limits more and more, the development of moore's law will eventually slow down or even go to the endpoint. And therefore have evolved as advanced packaging techniques beyond moore's law. In recent years, advanced packaging technologies that are rapidly developed mainly include: wafer-level Packaging (WLP), panel-level Chip-scale Packaging (die-on-package), package-on-package (Packaging-on-package), 2.5D Packaging, 3D Packaging, system-in-package (System in a package), and the like. Advanced packaging technology mainly develops towards high frequency, high efficiency, multifunctional system integration, miniaturization, light weight, high performance and high reliability.
It is particularly emphasized that the manner of using an interposer in a 2.5D advanced package, and the manner of connecting the functional chiplet to the external circuitry, enables heterogeneous integration of a variety of different chips, enhancing chip performance. In actual industrial production, the preparation of silicon intermediaries (sinterpost) as 2.5D intermediaries by means of through silicon via technology (Through Silicon Via, TSV) is a very well established technology. However, the high-density interconnection is generally expensive, and with the development of the WLP, the process method of preferentially manufacturing the high-density rewiring layer (Re-distribution layer, RDL) can realize the high-density interconnection with relatively low cost, so as to achieve the effect of TSV package interconnection. As the interconnect density increases, the wiring density of RDLs also increases.
PI (polyimide) is a stable conjugated structure polymer chemical containing imide ring and benzene ring structures, and is widely used in microelectronics industry due to low stress, low absorptivity, high young's modulus and better ductility. In addition, since the dielectric properties are good, the dielectric coefficient is about 3.4, and the material is a very good organic insulating material, so that the material is widely used as an RDL wiring passivation layer. The preparation of the wiring pattern layer based on PI is therefore critical for the preparation of the organic RDL interposer.
However, by-products that are difficult to clean up are currently generated during the preparation of RDL routing, thereby reducing the duty cycle of the etching chamber.
Disclosure of Invention
The embodiment of the application aims to provide a method for dry etching a polyimide layer, a method for preparing a rewiring layer and the rewiring layer, which at least can solve the problem that byproducts which are difficult to clean in the RDL wiring preparation process are generated.
In order to solve the technical problems, the application is realized as follows:
the embodiment of the application provides a method for dry etching a polyimide layer, which comprises the following steps:
coating a photosensitive material containing a silicon oxygen component on a polyimide layer on a substrate, exposing and developing the photosensitive material, and forming a first preset pattern layer on the photosensitive material;
performing first etching on the polyimide layer by using an etching gas by adopting a plasma dry etching technology, so that the first preset pattern layer is transferred to the polyimide layer, wherein the etching gas comprises oxygen and fluorine-based gas;
removing the photosensitive material;
coating photoresist on the polyimide, exposing and developing the photoresist, and forming a second preset layer on the photoresist, wherein the position of the second preset layer corresponds to the position of the first preset layer;
performing second etching on the polyimide layer by using the etching gas by adopting a plasma dry etching technology, so that the second preset pattern layer is transferred to the polyimide layer, and the etching depth of the second etching is smaller than that of the first etching;
and removing the photoresist.
The application also provides a preparation method of the rewiring layer, which comprises the method for etching the polyimide layer by the dry method;
wherein, after removing the photoresist, the preparation method further comprises:
respectively depositing a metal seed layer on the polyimide surface, the first preset pattern layer and the second preset pattern layer;
copper is electroplated on the surface of the polyimide layer, the first preset pattern layer and the second preset pattern layer respectively corresponding to the metal seed layer, so that filling preparation of a single-layer wiring layer is formed;
and removing copper and the metal seed layer on the surface of the polyimide layer, and removing copper which corresponds to the second preset pattern layer and protrudes out of the surface of the polyimide layer.
The embodiment of the application also provides a rewiring layer, which is prepared by adopting the preparation method, and comprises the following steps: a substrate and a polyimide layer;
the polyimide layer is arranged on the substrate;
the polyimide layer is provided with a groove, and the bottom of the groove is provided with a through hole;
copper is filled in the groove and the through hole, and the copper is flush with the surface of the notch of the groove and the surface of the orifice of the through hole respectively.
The method for dry etching the polyimide layer can relieve byproducts which are difficult to clean in the process, is relatively simple and low in cost, depends on a dry etching PI process, and can meet PI hole or line shape requirements of high wiring density, high depth-to-width ratio, high perpendicularity and smooth side walls.
Drawings
FIG. 1 is a schematic flow chart of preparing an RDL interposer according to the related art;
FIG. 2 is a schematic diagram of an etching profile in the related art;
FIG. 3 is a flow chart of a method for dry etching a polyimide layer disclosed in an embodiment of the present application;
FIG. 4 is a schematic illustration of a process for preparing a single RDL interposer according to embodiments of the present application;
FIG. 5 is a schematic diagram of a dual-layer RDL interposer disclosed in embodiments of the present application;
FIG. 6 is a schematic diagram of an etching process disclosed in an embodiment of the present application;
FIG. 7 is a schematic diagram of a single step etching PI sidewall anomaly morphology as disclosed in embodiments of the present application;
fig. 8 is an SEM characterization diagram of the etching results disclosed in the examples of the present application.
Detailed Description
The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art based on the embodiments herein without making any inventive effort, are intended to be within the scope of the present application.
The terms first, second and the like in the description and in the claims, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged, as appropriate, such that embodiments of the present application may be implemented in sequences other than those illustrated or described herein, and that the objects identified by "first," "second," etc. are generally of a type and not limited to the number of objects, e.g., the first object may be one or more. Furthermore, in the description and claims, "and/or" means at least one of the connected objects, and the character "/", generally means that the associated object is an "or" relationship.
The embodiments of the present application will be described in detail below with reference to the accompanying drawings by means of specific embodiments and application scenarios thereof.
In the related art, in fan-out type package, RDL fabrication is to form micro vias (via) by photolithography and development using photosensitive PI as a passivation layer of Cu wiring, and then sputter Cu seed layer and plate Cu to form a connection circuit.
However, for PI with high aspect ratio, the photolithography verticality is problematic, residues exist at the bottom of the deep hole after photolithography, an additional plasma treatment process is still required to remove the residual photoresist, and the photosensitive PI has poor reliability.
Referring to fig. 1 and 2, with a bilayer mask,PVD sputtering Al on the PI surface, spin coating photoresist on Al, exposing and developing to prepare the required pattern. Wherein, it is needed to etch Al as the hard mask after PI etching, and then the hard mask needs to be removed. In etching PI, O is used 2 +SF 6 /CF 4 /CHF 3 As an etching gas, the etching profile is shown in fig. 2.
However, the above-mentioned dual mask process is complicated, which makes the process cost high, and SF is used in the process of etching PI 6 F-based gas is etched to part of Al to generate a small amount of AlF 3 The by-product is difficult to clean, the working period of the etching chamber is reduced, and the PI etched by the technology is a groove, and the depth-to-width ratio is smaller and is generally smaller than 0.5.
Based on the above situation, the embodiment of the application discloses a method for dry etching a polyimide layer, which is used for alleviating the above problems. As shown in fig. 3 to 8, the disclosed method of dry etching a polyimide layer includes:
s100, coating a photosensitive material containing a silicon oxygen component on a polyimide layer on a substrate, exposing and developing the photosensitive material, and forming a first preset pattern layer on the photosensitive material.
Alternatively, the substrate may be a wafer. For example, a 12 inch wafer may be used, and of course, other sizes of wafers are also possible. The substrate may also be glass for cost reduction. The glass may be of the type schottky, BF33, for example, but of course, may be of other types.
In the embodiment of the application, polyimide is spin-coated on a substrate serving as a base body, and annealed and cured to form a polyimide layer (i.e., a polyimide film).
In addition, a photosensitive material containing a silicon oxygen component may be spin-coated on the polyimide layer, and exposed and developed to prepare a first predetermined pattern layer, wherein the first predetermined pattern layer may be a predetermined micro via (via) pattern. Illustratively, the feature sizes (critical dimension, CD) of the via may all be less than 5 μm.
Alternatively, the photosensitive material may comprise SiO x Ingredients, e.g. including SiO, siO 2 And the like, and the proportion among the components can be set according to the actual working condition, and the specific proportion is not limited.
The photosensitive material may be exemplified by a photosensitive silane coupling agent, but may be other materials, and is not particularly limited herein.
And S200, performing first etching on the polyimide layer by using an etching gas by adopting a plasma dry etching technology, so that the first preset pattern layer is transferred to the polyimide layer, wherein the etching gas comprises oxygen and fluorine-based gas.
In some embodiments, an inductively coupled plasma (Indrctively coupled plasma, ICP) etching technique may be used to etch Polyimide (PI) holes to obtain a first PI via topography.
In addition, the flow ratio of oxygen to fluorine-based gas may range from 5:1 to 15:1, including: 5:1, 8:1, 10:1, 12:1, 15:1, etc., of course, other flow ratios are also possible, as long as the process requirements can be met. Illustratively, the etching gas may include O 2 And CH (CH) 2 F 2 。
S300, removing the photosensitive material.
Alternatively, a wet process may be used to remove the photosensitive material. In particular, hydrofluoric acid (HF) and ammonium fluoride (NH) 4 F) Removing photosensitive material at normal temperature to ensure the surface of the polyimide layer to be clean.
And S400, coating photoresist on polyimide, exposing and developing the photoresist, and forming a second preset layer on the photoresist, wherein the position of the second preset layer corresponds to the position of the first preset layer.
And repeating S100, preparing a second preset pattern layer through exposure and development, wherein the second preset pattern layer can be a mask pattern required by a preset line pattern layer so as to prepare for the next etching.
S500, performing second etching on the polyimide layer by using an etching gas by adopting a plasma dry etching technology, so that the second preset pattern layer is transferred to the polyimide layer, and the etching depth of the second etching is smaller than that of the first etching.
And repeating S200, specifically, an ICP type plasma etching technology can be adopted, and the etching time is reduced according to different etching depths, so as to prepare a line pattern layer, such as a groove, on top of the original PI.
It should be noted that the etching gas used in the second etching may be the same as that used in the first etching, and of course, some other etching parameters may be the same, and the difference is mainly that the etching depth of the second etching is smaller than that of the first etching, so as to form different layers. Specifically, the first etching may form a via hole, and the second etching may form a trench corresponding to the via hole.
S600, removing the photoresist.
And after the second etching is finished, removing the photoresist. Alternatively, a wet process may be used to remove the photoresist. In particular, hydrofluoric acid (HF) and ammonium fluoride (NH) 4 F) And removing the photoresist at normal temperature to ensure the surface of the polyimide layer to be clean.
In this embodiment, before coating the photoresist on the polyimide layer, the method for dry etching the polyimide layer further includes:
by O 2 +CF 4 The surface of the polyimide layer is treated by microwave source plasma so as to remove residual glue, ensure the surface of the polyimide layer to be clean and increase the binding force between the subsequent surfaces.
Specifically, during the microwave source layer ion body treatment, the pressure range of the process chamber can be 0.2-0.8T, preferably 0.4T; the power of the upper microwave source can be 800-2500W, preferably 1000W; the lower radio frequency power can be 50-500W, preferably 80W; the flow rate of the oxygen may be 300 to 3000sccm, preferably 500sccm; the flow rate of the carbon tetrafluoride may be 10 to 1000sccm, preferably 50sccm; the treatment time may be 60s.
In this embodiment of the present application, after removing the photoresist, the method for dry etching the polyimide layer further includes:
by O 2 +CF 4 Surface of polyimide layer is treated by microwave source plasma, firstThe area corresponding to the preset layer and the area corresponding to the second preset layer ensure that the surfaces of all layers are clean so as to increase the binding force between the subsequent surfaces.
Specifically, during microwave source plasma treatment, the pressure of the process chamber may range from 0.2T to 0.8T, preferably 0.4T; the power of the upper microwave source can be 800-2500W, preferably 1000W; the lower radio frequency power can be 50-500W, preferably 80W; the flow rate of the oxygen may be 300 to 3000sccm, preferably 500sccm; the flow rate of the carbon tetrafluoride may be 10 to 1000sccm, preferably 50sccm; the treatment time may be 60s.
In this embodiment, before the first etching, the method for dry etching the polyimide layer further includes:
by O 2 +Cl 2 The polyimide layer is subjected to surface pretreatment.
The method of dry etching the polyimide layer prior to the second etching further comprises:
by O 2 +Cl 2 The polyimide layer is subjected to surface pretreatment.
By pre-treating the surface to form a deposit, the PI can be protected to a certain extent.
The description of the specific embodiments is made with the first etching step and the second etching step, the PI topography is etched based on inductively coupled plasma (inductively coupled plasma, ICP), and the PI etching process is specifically preferably formulated as shown in table 1 (wherein the temperature of the electrostatic chuck is preferably 20 ℃).
Table 1 plasma etching process recipe
Wherein the temperature range is-15-40 ℃, the cavity pressure range of the process chamber is 2-200 mTorr, the upper electrode power range is 100-5000W, the lower electrode power range is 10-1000W, the ratio of the upper electrode power to the lower electrode power is more than 2:1, the process gas flow range is 5-500 sccm, and the process time is determined by the etching rate and the designed etching depth.
In the plasma etching process of the embodiment of the application, surface pretreatment is first required, and O is adopted 2 +Cl 2 Performing a short-time process, and then performing etching by using etching gas, wherein the specific etching process is considered as follows:
PI material is an organic polymer material, its main component is C, O, N, H, etc., which is used as a functional medium material, and other elements are added to enhance its physical properties, wherein a small amount of Si element can be added to increase its toughness. Illustratively, the PI may be of the type BL301, which contains a small amount of Si element. In the embodiment of the application, the photosensitive material containing the silicon-oxygen component is used as the mask adhesive of PI, instead of the traditional photoresist (the main component of the photoresist is C, H, O and the like), so that the component difference between the mask and the PI is increased, and the mask can be selected higher when the PI is etched.
In some embodiments, O is used 2 +Ar+N 2 +CH 2 F 2 Either the first etching or the second etching is performed. In the first etching or the second etching process, O is used as 2 As the main etching gas of PI, the main etching gas dissociates O ions and O-containing free radicals react with C-H, C-N in PI under a high-frequency electromagnetic field to generate gaseous CO and CO 2 、NO、N 2 O and H 2 O, etc.; n (N) 2 Can promote O 2 Thereby promoting the generation of oxidation reaction and increasing the etching rate; ar dissociates Ar ion and Ar free radical, increases physical bombardment effect in vertical direction, does not participate in chemical reaction, thus ensuring anisotropic etching effect and increasing perpendicularity of PI holes; introducing small amounts of CH in etching gases 2 F 2 CF, CF may be provided 2 And F free radicals which can react with a small amount of Si in the PI component to form SiF 4 And (3) gas, so that Si element in PI is removed.
Here, the CH is as follows 2 F 2 Cannot be introduced too much and other gases with a high F group content, e.g. SF 6 、NF 3 、CF 4 And so on, otherwise the organic SiOx mask would be etched too much,resulting in a lower or even insufficient selection.
In addition, if the shape of the photoresist edge opening is better, the one-step method O can be adopted 2 +Ar+N 2 +CH 2 F 2 Etching. For the situation that the pattern edge is overshadowed in the photoetching development process of the organic medium photoresist, the bottom of the edge and the PI surface are provided with pores, at the moment, the loss (loss) of the top characteristic dimension (critical dimension, CD) of the PI is increased by only one-step etching, the top lateral etching is serious, and the shape deviation and the roughness of the side wall are increased, as shown in figure 7.
Therefore, for the abnormal condition of the mask, the embodiment of the application introduces a surface pretreatment process, and firstly performs sidewall deposit protection. By O 2 +Cl 2 Operating, under the action of a radio frequency electromagnetic field, generating O free radicals and Cl free radicals to react with a top SiO component to generate SiOCl sediment, and depositing the sediment on the top side wall and the top surface gap to protect the PI inside; in the second step O 2 +Ar+N 2 +CH 2 F 2 In the etching PI, since the top sidewall is protected, the top feature size will keep the original size, and PI holes or lines with feature size close to the theoretical design value and high verticality are generated, as shown in fig. 6, where a is a substrate, B is a bottom stop layer, C is a PI layer, D is an organic medium mask, and E is sidewall deposit SiOCl.
The SEM characterization of the etching results obtained using the above process recipe is shown in fig. 8, where the sidewall verticality is high, approximately 89 ° is close to 90 °, and the feature size loss of the top sidewall is small.
Therefore, the embodiment of the application can adopt a two-step treatment process aiming at the phenomena of poor photoetching morphology and void at the edge of the bottom of the mask, and firstly adopts O 2 +Cl 2 Protecting the appearance of the top of PI, and adopting O 2 +Ar+N 2 +CH 2 F 2 And performing morphology etching, such as micro-via/line morphology etching, on the PI according to the first preset pattern layer and the second preset pattern layer to obtain a better etching result.
In summary, compared with the related art, the method for dry etching the polyimide layer in the embodiment of the application can relieve byproducts which are difficult to clean in the process, is relatively simple and low in cost, depends on the dry etching PI process, and can meet PI hole or line appearance requirements of higher wiring density, higher depth-to-width ratio, higher verticality and smooth side wall.
Based on the method for dry etching the polyimide layer, the embodiment of the application also discloses a preparation method of the rewiring layer, and the preparation method of the rewiring layer comprises the method for dry etching the polyimide layer;
wherein, after removing the photoresist, the preparation method further comprises:
and S700, respectively depositing metal seed layers on the polyimide surface, the first preset pattern layer and the second preset pattern layer.
Alternatively, PVD may be used to plate a metallic titanium seed layer, wherein the thickness of titanium may range from 10 to 100nm, preferably 50nm. Of course, PVD may also be used to plate a metallic copper seed layer, wherein the copper thickness may range from 100 to 500nm, preferably 200nm.
S800, electroplating copper on the surface of the polyimide layer, the metal seed layers corresponding to the first preset pattern layer and the second preset pattern layer respectively to form filling preparation of a single-layer wiring layer.
And filling the through holes and the grooves on the PI corresponding to the first preset pattern and the second preset pattern by adopting an electrolytic copper plating process.
S900, removing copper and the metal seed layer on the surface of the polyimide layer, and removing copper which corresponds to the second preset pattern layer and protrudes out of the surface of the polyimide layer.
Alternatively, chemical mechanical polishing (chemical mechanical polishing, CMP) may be used to remove the copper (or titanium) layer on top of the PI, which may be overground in order to remove the metallic copper on the PI surface, leaving only the metallic copper in the wiring trenches for subsequent connection to the chip and package substrate without shorting.
Of course, when the RDL wiring density or the interconnection complexity further increases, a multi-layer RDL wiring may be further performed, so that a second layer RDL wiring may be performed on top of the original RDL layer, and steps S100 to S900 are repeated, thereby performing multi-layer RDL interposer preparation.
As shown in fig. 3 and fig. 4, taking a wafer as an example of a substrate, the specific flow of the preparation method of the rewiring layer in the embodiment of the application is as follows:
s110, uniformly spin-coating polyimide on a wafer carrier, and annealing and curing to form a polyimide layer;
s120, spin-coating a photosensitive silane coupling agent on the polyimide layer, exposing and developing the photosensitive silane coupling agent to form a first preset pattern layer (such as a via pattern) on the photosensitive silane coupling agent;
s210, performing first etching on the polyimide layer by adopting a plasma dry etching technology, and transferring a first preset pattern layer into the polyimide layer;
s310, using HF and NH 4 Wet-removing the photosensitive silane coupling agent from the mixed solution;
s320, adopt O 2 +CF 4 Treating the surface of the polyimide layer by microwave source plasma;
s410, coating photoresist on the polyimide layer, exposing and developing the photoresist, and forming a second preset pattern layer (e.g. Line pattern) on the photoresist, wherein the second preset pattern layer corresponds to the first preset pattern layer in position;
s510, performing second etching on the polyimide layer by adopting a plasma dry etching technology, and transferring a second preset pattern layer into the polyimide layer;
s610 using HF and NH 4 Wet-removing photoresist from the mixed solution of (a);
s620, adopt O 2 +CF 4 The surface of the polyimide layer, the area corresponding to the first preset layer and the area corresponding to the second preset layer are treated by microwave source plasma;
s710, depositing a metal seed layer (such as a Ti layer or a Cu layer) on the polyimide surface, the first preset pattern layer and the second preset pattern layer respectively by PVD;
s810, respectively electroplating copper on the surface of the polyimide layer, the metal seed layers corresponding to the first preset pattern layer and the second preset pattern layer to form filling preparation of a single-layer wiring layer;
s910, removing copper and a metal seed layer on the surface of the polyimide layer by adopting CMP, and removing copper which corresponds to the second preset pattern layer and protrudes out of the surface of the polyimide layer;
s1010, judging whether the current RDL layer number meets the requirement, returning to S210 when the current RDL layer number does not meet the requirement, and repeatedly executing S210-S910 to prepare multi-layer RDL wiring until the RDL layer number meets the requirement; when the RDL layer number meets the requirement, the preparation is finished.
Based on the preparation method of the rewiring layer, the embodiment of the application also discloses a rewiring layer, which is prepared by adopting the preparation method, and the disclosed rewiring layer comprises the following steps: the substrate and the polyimide layer, wherein, the polyimide layer is located on the substrate, and the polyimide layer is equipped with the slot, and the tank bottom of slot is equipped with the through-hole, all fills with copper in slot and the through-hole, and copper and the notch of slot place face, and the drill way place face of through-hole are flush respectively.
The polyimide layer is a wiring passivation layer, and can be directly connected with wiring metal copper without preparing an additional insulating barrier layer because the polyimide layer is an insulator; copper serves as a conductor and may serve as an electrical interconnect, with the polyimide layer and copper together forming an interposer, which is disposed on a substrate to form a rewiring layer.
In some embodiments, the rewiring layer may comprise a plurality of polyimide layers, the plurality of polyimide layers being stacked on the substrate, with copper being provided on each of the adjacent polyimide layers to connect. Illustratively, the rewiring layer may include polyimide layers of 2 layers, 3 layers, 5 layers, and the like, the number of layers of which is not limited. The rewiring layer in the form can be very conveniently used for high-density wiring with small line width and line distance (such as less than or equal to 5 mu m, etc.), so that the rewiring layer can be compatible with stacking of various chips, and the manufacturing process is simpler.
Taking a dual-layer RDL interposer as an example, as shown in fig. 5, the substrate 100 is a substrate for manufacturing the interposer, the first interposer 200 is disposed on the substrate 100, and the second interposer 300 is disposed on a side of the first interposer 200 facing away from the substrate 100.
The first interposer 200 and the second interposer 300 each include a polyimide layer 210 and a copper layer 220, the copper layer 220 is disposed in the polyimide layer 210, and two ends of the copper layer 220 are respectively flush with two opposite sides of the polyimide layer 210, so that when the first interposer 200 is bonded to the second interposer 399, the copper layer 220 in the first interposer 200 is connected to the copper layer 220 in the second interposer 300, so as to achieve electrical conduction.
The embodiments of the present application have been described above with reference to the accompanying drawings, but the present application is not limited to the above-described embodiments, which are merely illustrative and not restrictive, and many forms may be made by those of ordinary skill in the art without departing from the spirit of the present application and the scope of the claims, which are also within the protection of the present application.
Claims (11)
1. A method of dry etching a polyimide layer, the method comprising:
coating a photosensitive material containing a silicon oxygen component on a polyimide layer on a substrate, exposing and developing the photosensitive material, and forming a first preset pattern layer on the photosensitive material;
performing first etching on the polyimide layer by using an etching gas by adopting a plasma dry etching technology, so that the first preset pattern layer is transferred to the polyimide layer, wherein the etching gas comprises oxygen and fluorine-based gas;
removing the photosensitive material;
coating photoresist on the polyimide, exposing and developing the photoresist, and forming a second preset layer on the photoresist, wherein the position of the second preset layer corresponds to the position of the first preset layer;
performing second etching on the polyimide layer by using the etching gas by adopting a plasma dry etching technology, so that the second preset pattern layer is transferred to the polyimide layer, and the etching depth of the second etching is smaller than that of the first etching;
and removing the photoresist.
2. The method of claim 1, wherein prior to performing the first etch, the method further comprises: by O 2 +Cl 2 Carrying out surface pretreatment on the polyimide layer; and/or the number of the groups of groups,
before performing the second etching, the method further includes: by O 2 +Cl 2 And carrying out surface pretreatment on the polyimide layer.
3. The method of claim 1, wherein prior to coating the photoresist on the polyimide layer, the method further comprises:
by O 2 +CF 4 The microwave source plasma treats the surface of the polyimide layer.
4. The method of claim 1, wherein after removing the photoresist, the method further comprises:
by O 2 +CF 4 And the microwave source plasma processes the polyimide layer surface, the region corresponding to the first preset layer and the region corresponding to the second preset layer.
5. The method of claim 1, wherein the flow ratio of the oxygen to the fluorine-based gas ranges from 5:1 to 15:1.
6. The method of claim 1, wherein the photosensitive material is a photosensitive silane coupling agent.
7. The method according to claim 1, wherein HF and NH are used 4 Wet-process removal of F mixed solutionThe photosensitive material or the photoresist.
8. The method of claim 1, wherein the substrate is glass or a wafer.
9. A method for producing a rewiring layer, characterized by comprising the method for dry etching a polyimide layer according to any one of claims 1 to 8;
wherein, after removing the photoresist, the preparation method further comprises:
respectively depositing a metal seed layer on the polyimide surface, the first preset pattern layer and the second preset pattern layer;
copper is electroplated on the surface of the polyimide layer, the first preset pattern layer and the second preset pattern layer respectively corresponding to the metal seed layer, so that filling preparation of a single-layer wiring layer is formed;
and removing copper and the metal seed layer on the surface of the polyimide layer, and removing copper which corresponds to the second preset pattern layer and protrudes out of the surface of the polyimide layer.
10. A rewiring layer prepared by the method of claim 9, the rewiring layer comprising: a substrate and a polyimide layer;
the polyimide layer is arranged on the substrate;
the polyimide layer is provided with a groove, and the bottom of the groove is provided with a through hole;
copper is filled in the groove and the through hole, and the copper is flush with the surface of the notch of the groove and the surface of the orifice of the through hole respectively.
11. The rewiring layer of claim 10, wherein the rewiring layer comprises a plurality of the polyimide layers, the plurality of polyimide layers being laminated to the substrate;
and copper arranged on each of the two adjacent polyimide layers is connected.
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| CN202311775026.9A CN117747542A (en) | 2023-12-21 | 2023-12-21 | Method for dry etching polyimide layer, rewiring layer and preparation method thereof |
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