CN117743016A - Detection method and device for execution time sequence abnormality of multi-core processor system - Google Patents
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Abstract
The invention provides a method and a device for detecting abnormal execution time sequence of a multi-core processor system, wherein the method comprises the following steps: acquiring target instruction addresses corresponding to each processor core in the multi-core processor system when the processor cores run the target program at the same moment; mapping each target instruction address into a Cartesian coordinate system, detecting whether the execution sequence of a processor core in the multi-core processor system is abnormal or not according to the coordinate information corresponding to each target instruction address, wherein the horizontal axis of the Cartesian coordinate system represents the instruction execution sequence, and the vertical axis represents the instruction address. The method can improve the detection efficiency and the accuracy of the detection result, reduce the detection cost and improve the reliability and the stability of the whole system.
Description
Technical Field
The invention belongs to the technical field of detection of fault devices of electronic equipment, and particularly relates to a method and a device for detecting abnormal execution time sequence of a multi-core processor system.
Background
In space environments, the irradiation of high-energy particles can cause a single event effect to occur in the multi-core processor unit, and the effect can generally cause single event soft errors, namely, the effect can not cause damage to a hardware circuit, but can influence stored data or circuit states. These errors may be restored to normal conditions by means of a system reset, a re-power-up, a re-write, etc. Single event upset is a common situation that can lead to confusion of logic inside the processor, errors in the computation results, anomalies in functionality, and even a system crash. In a highly reliable system, such as a space device or a space facility, the processor functions are required to be highly reliable, so that a mode that multiple processors run the same program in parallel and synchronously is often adopted to serve as a redundant backup. The purpose of this is to detect and correct an exception handler by comparing the results of execution on different cores when a single event effect occurs resulting in an error. However, to achieve error detection in multi-core operation, a significant reliability challenge is faced.
The existing synchronization detection of the multi-core processor generally has the following three schemes. 1) And judging the task, namely executing the same task on a plurality of cores simultaneously, and comparing the execution results of the tasks on different cores after the task is completed. If the results of one core are inconsistent with other cores, then there may be a synchronization exception. 2) The timing judgment is to design a timing interrupt program in each core, interrupt the execution of the core regularly and save the state and the register content during interrupt. By comparing interrupt sites for different cores, errors can be detected. 3) The form verification is to carry out mathematical verification on the programming of the multi-core processor when the programming is carried out, so that the program can be automatically detected when the synchronism abnormality occurs.
However, the method in the prior art has the problems of low detection efficiency and poor accuracy, and can not locate the processor core with the abnormality, so that the user experience is poor.
Disclosure of Invention
In order to solve the problems in the prior art, the invention provides a method and a device for detecting abnormal execution time sequence of a multi-core processor system. The invention is realized by the following technical scheme:
in a first aspect, the present invention provides a method for detecting an execution timing anomaly of a multi-core processor system, including:
acquiring target instruction addresses corresponding to each processor core in the multi-core processor system when the processor cores run the target program at the same moment;
mapping each target instruction address into a Cartesian coordinate system, detecting whether the execution sequence of a processor core in the multi-core processor system is abnormal or not according to the coordinate information corresponding to each target instruction address, wherein the horizontal axis of the Cartesian coordinate system represents the instruction execution sequence, and the vertical axis represents the instruction address.
In a second aspect, the present invention provides a detection apparatus for abnormal execution timing of a multi-core processor system, including:
the acquisition module is used for acquiring target instruction addresses corresponding to each processor core in the multi-core processor system when the processor cores run the target program at the same moment;
the processing module is used for mapping each target instruction address into a Cartesian coordinate system so as to detect whether the execution sequence of the processor core in the multi-core processor system is abnormal according to the coordinate information corresponding to each target instruction address, wherein the horizontal axis of the Cartesian coordinate system represents the instruction execution sequence, and the vertical axis represents the instruction address.
In a third aspect, the present invention provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, where the processor, the communication interface, and the memory complete communication with each other through the communication bus;
a memory for storing a computer program;
a processor for implementing any of the method steps provided in the first aspect when executing a program stored on a memory.
In a fourth aspect, the present invention provides a computer-readable storage medium having stored thereon a computer program which, when executed by a processor, implements any of the method steps provided in the first aspect.
The invention has the beneficial effects that:
according to the detection method and the detection device for the abnormal execution time sequence of the multi-core processor system, the multi-core processor is effectively detected by utilizing the heartbeat mechanism by acquiring the target instruction address corresponding to each processor core in the multi-core processor system when the target program is operated at the same moment, so that the monitoring of the multi-core processor system is realized; further, each target instruction address is mapped into a Cartesian coordinate system, whether the execution sequence of a processor core in the multi-core processor system is abnormal or not is detected according to coordinate information corresponding to each target instruction address, the horizontal axis of the Cartesian coordinate system represents the instruction execution sequence, the vertical axis of the Cartesian coordinate system represents the instruction addresses, and the detection can be completed without additional hardware equipment in a software implementation mode in combination with geometric mathematic thinking, so that the detection process is simplified, the detection cost is reduced, the detection efficiency is improved, the detection quality is improved, and the reliability and stability of the whole system are effectively improved.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a flow chart of a method for detecting abnormal execution time sequence of a multi-core processor system;
FIG. 2 is a schematic diagram showing a correspondence relationship between instruction execution sequences and instruction addresses according to the present invention;
FIG. 3 is a schematic diagram of a mapping result provided by the present invention;
fig. 4 is a schematic structural diagram of a detection device for abnormal execution timing sequence of a multi-core processor system according to the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
The synchronicity detection of the existing multi-core processor generally adopts task judgment or timing judgment or form verification. The task judgment is to execute the same task on a plurality of cores at the same time, and compare the task execution results on different cores after the task is completed. If the results of one core are inconsistent with other cores, then there may be a synchronization exception. The method judges whether each core is wrong or not by obtaining results on different cores, the time is too long to detect errors in time, and the method is a specific instruction which can not find errors for indirect error detection. The timing judgment is to design a timing interrupt program in each core, interrupt the execution of the core regularly, and save the state and the register content during interrupt. By comparing interrupt sites for different cores, errors can be detected. Although the state and the register content stored in different cores are compared through the time interrupt program, the core processor is prevented from being in error to a certain extent, the running environment change, the clock precision difference or the external interference can possibly cause different interrupt protection sites, so that erroneous judgment is caused, the processing efficiency of the processor is influenced, and the accuracy of a detection result is lower. The form verification is to carry out mathematical verification on the programming of the multi-core processor when the programming is carried out, so that the program can be automatically detected when the synchronism abnormality occurs. However, the form verification technology has high computational complexity and high resource consumption, is difficult to cope with the state explosion problem of a complex system, has high requirement on form specifications, and is difficult to cover all possible system behaviors, so that the detection efficiency and the accuracy of detection results are low.
Under the high reliability requirement, the multi-core processor needs to run the same functional code on each core, but the synchronicity is lost due to deviation in the execution process of a certain processor or a certain processors caused by irradiation and other factors, and the synchronicity detection of the existing multi-core processor can not meet the requirement.
Fig. 1 is a flow chart of a method for detecting abnormal execution timing of a multi-core processor system, which is applied to an electronic device, and includes:
s101, acquiring target instruction addresses corresponding to each processor core in the multi-core processor system when the processor cores run the target program at the same moment.
The multi-core processor system comprises a plurality of processor cores, and each processor core synchronously executes the same instruction so as to improve the reliability of the system.
Optionally, obtaining the target instruction address corresponding to each processor core in the multi-core processor system when running the target program at the same time includes: and acquiring instructions executed by the processor cores and corresponding instruction addresses when the timing interrupts in the processor cores are triggered in the process of running the target program by the processor cores from the corresponding registers of the processor cores respectively, wherein the timing duration of the timing interrupts in the processor cores is the same.
The timing interrupts are deployed in each processor core in the multi-core processor system, and the timing duration corresponding to each timing interrupt is the same, so that the timing interrupts are ensured to be triggered synchronously.
When the timer is triggered, if the running time sequence of each processor core of the multi-core processor system is normal, the instructions corresponding to each processor core at the current moment are the same, and the instruction addresses are the same; if the running time sequence of the processor cores is abnormal in the multi-core processor system, the instructions corresponding to the processor cores at the current moment are different, and the instruction addresses are also different.
FIG. 2 is a schematic diagram showing a correspondence between instruction execution sequences and instruction addresses, wherein each instruction is executed by a program counter corresponding to a different instruction address as shown in FIG. 2. When the instructions are executed sequentially, the instruction addresses are increased in sequence, the difference between the adjacent instruction addresses is smaller, and when the instruction jumps such as function call occur, the difference between the adjacent instruction addresses is larger.
The value of the program counter of each processor core comprises executed instructions and corresponding instruction addresses, the data directly represents the overall running trend of the program in each processor core, when the corresponding interrupt is triggered, the value of the program counter is stored in the corresponding register, and based on the value, the instructions executed by each processor core and the corresponding instruction addresses can be acquired from the corresponding register of each processor core respectively in the process of running the target program of each processor core when the timed interrupt in each processor core is triggered.
The interrupt can be triggered to acquire the data in the corresponding register so as to improve the detection accuracy; the method can also be used for periodically acquiring the data in the register at fixed time intervals or at selected moments, so that the detection accuracy is ensured, the program is simplified, the detection frequency is reduced, the operation is reduced, and the cost is reduced.
S102, mapping each target instruction address into a Cartesian coordinate system, and detecting whether the execution time sequence of a processor core in the multi-core processor system is abnormal or not according to the coordinate information corresponding to each target instruction address.
Wherein the horizontal axis of the Cartesian coordinate system represents the instruction execution order and the vertical axis represents the instruction address.
Optionally, mapping each target instruction address into a cartesian coordinate system includes: and determining the difference value between any two target instruction addresses, comparing the difference value with a preset threshold value, and mapping each target instruction address into a Cartesian coordinate system if at least one difference value is larger than the preset threshold value.
It will be appreciated that, in theory, when the processor cores in the multi-core processor system synchronously execute the same target program, the instruction addresses corresponding to the processor cores are the same at any time, however, in a real running environment, the execution states of the processor cores deviate, but in general, the deviation within an acceptable range is considered to be normal. When the difference between the target instruction addresses is large, it is considered that there may be a case where the execution timing of the processor core is abnormal, but when there is a program jump in the target program, a case where the difference between the target instruction addresses is large may also occur.
Based on the method, whether the execution time sequence of the multi-core processor system is abnormal or not can be roughly detected, detection is further carried out on the basis of rough detection, accuracy of detection results can be improved, detection efficiency is improved, computer resource waste can be reduced, and cost is saved.
Optionally, mapping each target instruction address to a cartesian coordinate system, so as to detect whether an abnormality exists in the execution sequence of the multi-core processor system according to coordinate information corresponding to each target instruction address, including: mapping a plurality of instruction addresses corresponding to the target program into Cartesian coordinates according to a corresponding instruction execution sequence to obtain a plurality of first coordinates, wherein the abscissa of the first coordinates is the instruction execution sequence, and the ordinate is the instruction address; determining a first coordinate with the same ordinate as any target instruction address in the first coordinates as a second coordinate; and detecting whether the execution time sequence of the multi-core processor system is abnormal or not according to the first coordinates and the second coordinates.
The mapping the multiple instruction addresses corresponding to the target program into the cartesian coordinates according to the corresponding instruction execution sequence may be that any processor core in the multi-core processor system is controlled to successfully execute the target program under an ideal environment, and the values of the corresponding program counters are recorded and mapped into the cartesian coordinates.
FIG. 3 is a schematic diagram of a mapping result provided by the present invention, wherein data in a data link table on the left side in FIG. 3 is instruction addresses, and arrows indicate address jump sequences, i.e. instruction execution sequences; the right is a schematic view of the left data link projected into the coordinate system, with black dots representing the first coordinates. The positional relationship of the coordinates in fig. 3 can intuitively reflect the degree of deviation between the corresponding instruction addresses.
With continued reference to FIG. 3, blue "+" in FIG. 3 indicates the second coordinate of the mapping of the target instruction address into the Cartesian coordinate system, C1, C2, C3, C4, respectively. It should be noted that, fig. 3 is only an example, and the second coordinate mapped by the target instruction address may not overlap with the first coordinate, and when such a situation occurs, it may be directly determined that the execution timing of the corresponding processor core is abnormal, and the program is deviated.
Optionally, detecting whether an abnormality exists in the execution timing of the multi-core processor system according to the plurality of first coordinates and the plurality of second coordinates includes: selecting at least three second coordinates as target second coordinates to construct a binary first-order program set; detecting whether the execution time sequence of the multi-core processor system is abnormal according to the first coordinates and the binary first-order program group.
The method can convert complex detection problems into simple mathematical geometry problems, reduce detection difficulty and improve detection accuracy.
Optionally, selecting at least three second coordinates as target second coordinates to construct a binary first-order set of equations, including: and selecting at least three second coordinates with corresponding abscissas closer to each other from the plurality of second coordinates as target second coordinates.
By the method, a binary once equation set can be reasonably constructed, and the detection efficiency is improved.
With continued reference to FIG. 3, C2 is adjacent to the abscissa of C1, C3, and the ordinate of C2 is more different from the ordinate of C3, and the ordinate of C2 is less different from the ordinate of C1. C4 and C2 have smaller differences in ordinate and C1 and C3 have larger differences in ordinate, and C4 and C1, C2 and C3 have smaller differences in abscissa. As can be seen from the first mapping result indicated by the black dots, the instruction execution sequences corresponding to C1, C2 and C3 are closer.
Illustratively, selecting C1, C2, C3 constructs a binary system of once equations, expressed as:
wherein, (x) 1 ,y 1 ) Is the coordinates of C1, (x) 2 ,y 2 ) Is the coordinates of C2, (x) 3 ,y 3 ) Is the coordinate of C3, L 1 Straight lines defined for C1 and C2, L 2 Straight lines defined for C2 and C3, L 3 Straight lines defined for C1 and C3.
The method is obtained by calculating the equation set:
optionally, detecting whether an abnormality exists in the execution timing of the multi-core processor system according to the plurality of first coordinates and the binary first-order program group includes: for any target second coordinate, if the slopes corresponding to the binary first-order equation sets related to the target second coordinate are determined to be unequal, determining the target second coordinate as a jumping point; determining a first coordinate, of the plurality of first coordinates, in a preset range corresponding to the abscissa of the jumping point as a target first coordinate; and determining whether the first coordinates of the target include second coordinates except the second coordinates of the target, and if not, determining that the execution time sequence of the processor core corresponding to the second coordinates of the target is abnormal.
In combination with the above example, k 1 ≠k 2 ≠k 3 Then C2 can be determined to be a jumping point.
Further, according to the first mapping result, determining a plurality of target first coordinates included in the 5 steps before and after the jumping point, wherein the target first coordinates are respectively T1, T2, T3, T4, T5 (C1), T6 (C3), T7, T8, T9 and T10 (C4), all the second coordinates C1, C3 and C4 except C2 are included, and judging that C2 is a normal jumping point, and the execution time sequence of a processor core corresponding to C2 is normal.
According to the detection method for the abnormal execution time sequence of the multi-core processor system, provided by the invention, the multi-core processor is effectively detected by utilizing the heartbeat mechanism by acquiring the target instruction address corresponding to each processor core in the multi-core processor system when the target program is operated at the same moment, so that the monitoring of the multi-core processor system is realized; further, each target instruction address is mapped into a Cartesian coordinate system, whether the execution sequence of a processor core in the multi-core processor system is abnormal or not is detected according to coordinate information corresponding to each target instruction address, the horizontal axis of the Cartesian coordinate system represents the instruction execution sequence, the vertical axis of the Cartesian coordinate system represents the instruction addresses, and the detection can be completed without additional hardware equipment in a software implementation mode in combination with geometric mathematic thinking, so that the detection process is simplified, the detection cost is reduced, the detection efficiency is improved, the detection quality is improved, and the reliability and stability of the whole system are effectively improved.
Fig. 4 is a schematic structural diagram of a detection device for abnormal execution timing of a multi-core processor system according to the present invention, where, as shown in fig. 4, the device includes:
the obtaining module 41 is configured to obtain a target instruction address corresponding to each processor core in the multi-core processor system when the processor cores run the target program at the same time.
The processing module 42 is configured to map each target instruction address to a cartesian coordinate system, so as to detect whether an abnormality exists in an execution sequence of a processor core in the multi-core processor system according to coordinate information corresponding to each target instruction address, where a horizontal axis of the cartesian coordinate system represents an instruction execution sequence and a vertical axis represents an instruction address.
Optionally, the acquiring module 41 is specifically configured to acquire, from the registers corresponding to the processor cores, when the timing interrupt in each processor core triggers during the running of the target program by each processor core, an instruction executed by each processor core and a corresponding instruction address, where the timing duration of the timing interrupt in each processor core is the same.
Optionally, the processing module 42 is specifically configured to determine a difference between any two target instruction addresses, compare the difference with a preset threshold, and map each target instruction address to a cartesian coordinate system if at least one difference is greater than the preset threshold.
Optionally, the processing module 42 specifically maps a plurality of instruction addresses corresponding to the target program into cartesian coordinates according to a corresponding instruction execution sequence, so as to obtain a plurality of first coordinates, where an abscissa of the first coordinates is the instruction execution sequence and an ordinate is the instruction address; determining a first coordinate with the same ordinate as any target instruction address in the first coordinates as a second coordinate; and detecting whether the execution time sequence of the multi-core processor system is abnormal or not according to the first coordinates and the second coordinates.
Optionally, the processing module 42 is specifically configured to select at least three second coordinates as the target second coordinates, and construct a binary first-order program set; detecting whether the execution time sequence of the multi-core processor system is abnormal according to the first coordinates and the binary first-order program group.
Optionally, the processing module 42 is specifically configured to determine, for any target second coordinate, the target second coordinate as the jumping point if it is determined that the slopes corresponding to the binary first-order equation sets related to the target second coordinate are all not equal; determining a first coordinate, of the plurality of first coordinates, in a preset range corresponding to the abscissa of the jumping point as a target first coordinate; and determining whether the first coordinates of the target include second coordinates except the second coordinates of the target, and if not, determining that the execution time sequence of the processor core corresponding to the second coordinates of the target is abnormal.
Optionally, the processing module 42 is specifically configured to select, from the plurality of second coordinates, at least three second coordinates with corresponding abscissas closer to each other as the target second coordinate.
The invention also provides a structural schematic diagram of the electronic equipment, which comprises a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory are communicated with each other through the communication bus,
a memory for storing a computer program;
and the processor is used for realizing the steps provided in the method embodiment when executing the program stored in the memory.
The present invention also provides a computer readable storage medium having a computer program stored therein, which when executed by a processor implements the steps provided in the above-described method embodiments.
For the apparatus/electronic device/storage medium embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and details, advantages, and the like may be found in part in the description of the method embodiments.
The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present invention, the meaning of "a plurality" is two or more, unless explicitly defined otherwise.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Further, one skilled in the art can engage and combine the different embodiments or examples described in this specification.
Although the present application has been described herein in connection with various embodiments, other variations to the disclosed embodiments can be understood and effected by those skilled in the art in practicing the claimed application, from a review of the figures, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other elements or steps, and the "a" or "an" does not exclude a plurality. A single processor or other unit may fulfill the functions of several items recited in the claims. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (10)
1. A method for detecting an execution timing anomaly of a multi-core processor system, comprising:
acquiring target instruction addresses corresponding to each processor core in the multi-core processor system when the processor cores run the target program at the same moment;
mapping each target instruction address into a Cartesian coordinate system so as to detect whether the execution sequence of a processor core in the multi-core processor system is abnormal according to the coordinate information corresponding to each target instruction address, wherein the horizontal axis of the Cartesian coordinate system represents the instruction execution sequence, and the vertical axis represents the instruction address.
2. The method of claim 1, wherein the obtaining the target instruction address corresponding to each processor core in the multi-core processor system when the processor cores run the target program at the same time comprises:
and acquiring instructions executed by the processor cores and corresponding instruction addresses from the corresponding registers of the processor cores respectively, wherein the timing duration of the timing interrupts in the processor cores is the same when the timing interrupts in the processor cores are triggered in the process of running the target program by the processor cores.
3. The method of claim 1, wherein said mapping each of said target instruction addresses into a cartesian coordinate system comprises:
and determining a difference value between any two target instruction addresses, comparing the difference value with a preset threshold value, and mapping each target instruction address into the Cartesian coordinate system if at least one difference value is larger than the preset threshold value.
4. A method according to any one of claims 1-3, wherein mapping each target instruction address into a cartesian coordinate system to detect whether an abnormality exists in execution timing of the multi-core processor system according to coordinate information corresponding to each target instruction address, includes:
mapping a plurality of instruction addresses corresponding to the target program into the Cartesian coordinates according to the corresponding instruction execution sequence to obtain a plurality of first coordinates, wherein the abscissa of the first coordinates is the instruction execution sequence, and the ordinate is the instruction address;
determining a first coordinate with the same ordinate as any target instruction address in the first coordinates as a second coordinate;
and detecting whether the execution time sequence of the multi-core processor system is abnormal or not according to the first coordinates and the second coordinates.
5. The method of claim 4, wherein detecting whether an exception exists in the multi-core processor system execution timing based on the plurality of first coordinates and the second coordinates comprises:
selecting at least three second coordinates as target second coordinates, and constructing a binary first-order program group;
and detecting whether the execution time sequence of the multi-core processor system is abnormal or not according to the first coordinates and the binary one-time equation group.
6. The method of claim 5, wherein detecting whether an exception exists in the execution timing of the multi-core processor system based on the plurality of first coordinates and the set of binary once equations comprises:
for a second coordinate of either object,
if the slopes corresponding to the binary first-order equation sets related to the target second coordinates are not equal, determining the target second coordinates as jumping points;
determining a first coordinate, of the plurality of first coordinates, in a preset range corresponding to the abscissa of the jumping point as a target first coordinate;
and determining whether the first coordinates of the target comprise second coordinates except the second coordinates of the target, and if not, determining that the execution time sequence of the processor core corresponding to the second coordinates of the target is abnormal.
7. The method according to claim 5 or 6, wherein selecting at least three second coordinates as target second coordinates, constructing a binary first-order set of equations, comprises:
and selecting at least three second coordinates with corresponding abscissas closer to each other from the plurality of second coordinates as the target second coordinates.
8. A device for detecting an execution timing anomaly of a multi-core processor system, comprising:
the acquisition module is used for acquiring target instruction addresses corresponding to each processor core in the multi-core processor system when the processor cores run the target program at the same moment;
the processing module is used for mapping each target instruction address into a Cartesian coordinate system so as to detect whether the execution sequence of the processor core in the multi-core processor system is abnormal according to the coordinate information corresponding to each target instruction address, wherein the horizontal axis of the Cartesian coordinate system represents the instruction execution sequence, and the vertical axis represents the instruction address.
9. The electronic equipment is characterized by comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory are communicated with each other through the communication bus;
a memory for storing a computer program;
a processor for carrying out the method steps of any one of claims 1-7 when executing a program stored on a memory.
10. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored therein a computer program which, when executed by a processor, implements the method steps of any of claims 1-7.
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