CN111324355B - Method and system for debugging many-core code - Google Patents
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Abstract
The application discloses a method and a system for debugging many-core codes, wherein the method comprises the following steps: acquiring an original code and a many-core code; analyzing the original code and the many-core code, and establishing a mapping relation between a master core and a slave core; according to the mapping relation, performing correctness verification on the many-core code to obtain a verification result; if the verification result contains the error code, analyzing the error code to obtain the analysis result of the error code; and correcting error of the error code and reporting information according to the analysis result. The system comprises: the device comprises a code acquisition module, a mapping relation establishment module, a code verification module, an error code analysis module and an error correction and report module. By the method and the device, the processes from development to verification and to final application of the many-core code can be accelerated, the debugging efficiency of the many-core code is greatly improved, and the application program transplanting efficiency is further improved.
Description
Technical Field
The present application relates to the field of heterogeneous computing technologies, and in particular, to a method and a system for debugging many-core codes.
Background
In the field of parallel heterogeneous computing, various super-computations are usually completed by adopting heterogeneous accelerators. The accelerator is a many-core, and the normal operation of the heterogeneous accelerator requires libraries supported by the many-core and correct many-core code. The many-core supported library is generated along with the generation of many-core, a language, an instruction and the like different from the traditional C language and the like are adopted, and the implementation of many-core codes relates to the division of data, the division of calculation tasks, even the conversion of codes and the like, so that errors are easy to occur in the writing of many-core codes, and how to debug the many-core codes is an important technical problem in order to ensure the normal operation of a heterogeneous accelerator.
The present method for debugging many-core code is usually performed in large-scale applications, that is: in the execution process of large-scale application, the correctness of the many-core code can be verified by the cooperation between the master core and the slave core, and sometimes even by completely running the application once. After the problem of many-core codes is discovered, the problems need to be checked and debugged one by one in large-scale application.
However, in the current method for debugging many-core codes, because debugging needs to be performed in a large-scale application, and when problems occur in operation, the debugging needs to be checked one by one, so the current many-core code debugging process is relatively complex and time-consuming, and the debugging efficiency is too low.
Disclosure of Invention
The application provides a method and a system for debugging many-core codes, which aim to solve the problems that the debugging process of many-core codes is too complex and the debugging efficiency is low in the prior art.
In order to solve the technical problem, the embodiment of the application discloses the following technical scheme:
a method of debugging many-core code, the method comprising:
acquiring an original code and a many-core code;
analyzing the original code and the many-core code, and establishing a mapping relation between a master core and a slave core;
according to the mapping relation, carrying out correctness verification on the many-core code to obtain a verification result;
if the verification result contains an error code, analyzing the error code to obtain an analysis result of the error code;
and correcting error of the error code and reporting information according to the analysis result.
Optionally, the analyzing the original code and the many-core code to establish a mapping relationship between the master core and the slave core includes:
analyzing the character string of the original code to obtain a calculation parameter, a calculation mode and a cycle parameter which participate in calculation in the original code, wherein the calculation parameter comprises: the names, the dimensions and the start-stop coordinates of all the dimensions of the arrays participating in the calculation, wherein the cycle parameters comprise: the number of circulating layers and the start-stop index of each layer of circulation;
performing character string analysis on the many-core code to obtain the total number of the slave cores and the ID of the slave cores which participate in calculation;
analyzing the character strings of the many-core codes to obtain calculation parameters and calculation modes participating in calculation in the many-core codes;
analyzing the character string of the many-core code to acquire data loading and unloading information in the many-core code, wherein the data loading and unloading information comprises: loading the loaded array name and index position information corresponding to the data block in the original integral array;
and establishing a mapping relation between the master core and the slave core according to the calculation parameters participating in calculation in the original code, the calculation parameters participating in calculation in the many-core code, the matching relation between the calculation mode in the original code and the calculation mode in the many-core code, the cycle parameters and the data load-out information.
Optionally, after performing character string analysis on the many-core code and acquiring a calculation parameter and a calculation mode participating in calculation in the many-core code, the method further includes:
judging whether a loop exists in the slave core code;
and if so, acquiring the number of layers of loops in the core code and the start-stop index of each layer of loop.
Optionally, after the mapping relationship between the master core and the slave core is established according to the computation parameters participating in computation in the original code, the computation parameters participating in computation in the many-core code, the matching relationship between the computation patterns in the original code and the computation patterns in the many-core code, the loop parameters, and the data load/unload information, the method further includes:
determining a division mechanism of the data among different slave cores according to the mapping relation and the information loaded and unloaded by the data load, wherein the division mechanism comprises: non-redundant uniform partitioning, and global loading.
Optionally, the method for performing correctness verification on the many-core code according to the mapping relationship to obtain a verification result includes:
according to the mapping relation, converting the core code into the main core code to generate a test code for testing the many-core code;
running the test code and the many-core code;
judging whether the running result of the test code is consistent with the running result of the many-core code;
if yes, judging that the many-core code is correct;
if not, the many-core code is judged to be wrong.
Optionally, the method for analyzing the error code to obtain an analysis result of the error code includes:
comparing the running result of the test code with the running result of the many-core code, and determining the proportion of error codes and the position distribution of the error codes;
judging whether the error codes exist in the whole data range or not according to the position distribution of the error codes;
if the error code exists in the whole data range, determining as a global error code;
performing static analysis on the global error codes;
if the error code does not exist in the whole data range, judging as a local error code;
the localized error codes are analyzed.
Optionally, the method for statically analyzing a global error code includes:
verifying whether the slave kernel code completely covers the original data or not according to the mapping relation;
verifying data and calculating the full coverage of division according to the task division of the cycle hierarchy;
verifying index subscript information of the loaded and unloaded data;
the processing information of the boundary data is verified.
Optionally, the method for error correction and information reporting of the error code according to the analysis result includes:
correcting the error codes according to the static analysis result to obtain an error correction result;
verifying the error correction result;
if the verification is passed, reporting error code information;
if the verification fails, detailed error information is reported.
A system to debug many-core code, the system comprising:
the code acquisition module is used for acquiring an original code and a many-core code;
the mapping relation establishing module is used for analyzing the original code and the many-core code and establishing the mapping relation between the master core and the slave core;
the code verification module is used for verifying the correctness of the many-core code according to the mapping relation to obtain a verification result;
the error code analysis module is used for analyzing the error code to obtain the analysis result of the error code if the error code exists in the verification result;
and the error correction and report module is used for correcting errors of the error codes and reporting information according to the analysis result.
Optionally, the mapping relationship establishing module includes:
a first parsing unit, configured to perform string parsing on the original code, and obtain a calculation parameter, a calculation mode, and a loop parameter that participate in calculation in the original code, where the calculation parameter includes: the name, the dimension and the start-stop coordinate of each dimension of the array participating in the calculation, and the loop parameters comprise: the number of circulating layers and the starting and stopping indexes of each layer of circulation;
the second analysis unit is used for carrying out character string analysis on the many-core code and acquiring the total number of the slave cores and the ID of the slave cores which participate in the calculation;
the third analysis unit is used for carrying out character string analysis on the many-core code to obtain calculation parameters and calculation modes participating in calculation in the many-core code;
a fourth analyzing unit, configured to perform character string analysis on the many-core code, and acquire data load-and-unload information in the many-core code, where the data load-and-unload information includes: loading the loaded array name and index position information corresponding to the data block in the original integral array;
and the mapping relation establishing unit is used for establishing the mapping relation between the master core and the slave core according to the calculation parameters participating in calculation in the original code, the calculation parameters participating in calculation in the many-core code, the matching relation between the calculation mode in the original code and the calculation mode in the many-core code, the cycle parameters and the data loading and unloading information.
The technical scheme provided by the embodiment of the application can have the following beneficial effects:
the application provides a method for debugging many-core codes, which comprises the steps of firstly obtaining original codes and many-core codes; secondly, analyzing the original code and the many-core code, and establishing a mapping relation between a master core and a slave core; then, according to the established mapping relation, performing correctness verification on the many-core code to obtain a verification result; if the verification result contains the error code, analyzing the error code to obtain an analysis result of the error code; and finally, error correction and information reporting are carried out on the error codes according to the analysis result. According to the method, the mapping relation between the master core and the slave core is established, the many-core code is subjected to correctness verification according to the mapping relation, and the error code is analyzed and corrected, so that the correctness of the code can be effectively verified, the error position of the code with the error is positioned according to the code with the error, and finally, a code correction suggestion is given according to the analysis of the code, so that the processes from development to verification and to final application of the many-core code are accelerated, the debugging efficiency of the many-core code is greatly improved, and the application program transplanting efficiency is further improved.
The present application further provides a system for debugging many-core code, which mainly includes: the device comprises a code acquisition module, a mapping relation establishment module, a code verification module, an error code analysis module and an error correction and report module. According to the embodiment, through the setting of the mapping relationship establishing module, the mapping relationship between the master core and the slave core can be established, the code verifying module is used for verifying the correctness of the many-core code according to the mapping relationship, the error code analyzing module is used for analyzing the error code, and finally the error correcting and reporting module is used for correcting the error code and reporting information. The structural design can effectively verify the correctness of the codes, locate the error positions of the codes with errors and finally give a code correction suggestion according to the analysis of the codes, so that the processes of development, verification and final application of the many-core codes are accelerated, the debugging efficiency of the many-core codes is greatly improved, and the application program transplanting efficiency is further improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the application.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and, together with the description, serve to explain the principles of the application.
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a flowchart illustrating a method for debugging many-core code according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of a system for debugging many-core code according to an embodiment of the present disclosure.
Detailed Description
In order to make those skilled in the art better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
For a better understanding of the present application, embodiments of the present application are explained in detail below with reference to the accompanying drawings.
Example one
Referring to fig. 1, fig. 1 is a flowchart illustrating a method for debugging many-core code according to an embodiment of the present application. As shown in fig. 1, the method for debugging many-core code in this embodiment mainly includes the following steps:
s1: and acquiring original codes and many-core codes.
In this embodiment, the many cores are accelerators, and the scheme is mainly applied to heterogeneous accelerators such as GPUs, SW26010, and the like. To debug the many-core code, the original code and the many-core code, which are typically provided by the user, are preferably determined based on the retrieved commands.
S2: and analyzing the original code and the many-core code, and establishing a mapping relation between the master core and the slave core.
Specifically, step S2 includes the following processes:
s21: and analyzing the character strings of the original codes to obtain the calculation parameters, the calculation modes and the circulation parameters which participate in the calculation in the original codes.
Wherein, calculating the parameters comprises: the name and the dimension of the array participating in the calculation and the start-stop coordinates of each dimension; the cycle parameters include: the number of circulating layers and the starting and stopping indexes of each layer of circulation; the calculation mode is a calculation mode in which the array participates.
S22: and performing character string analysis on the many-core codes to obtain the total number of the slave cores and the ID of the slave cores which participate in the calculation.
Namely: and performing character string analysis on the many-core codes, determining how many secondary cores share the calculation task, and acquiring secondary core IDs participating in calculation, namely distinguishing codes of the secondary cores, wherein the secondary core IDs are unique IDs corresponding to the current secondary cores. In this embodiment, the total number of slave cores and the slave core ID involved in the calculation are obtained by calling a fixed library function.
S23: and analyzing the character strings of the many-core codes to obtain the calculation parameters and the calculation modes participating in calculation in the many-core codes.
In this embodiment, the many-core code and the slave core code, where the calculation parameters of the many-core code participating in the calculation include: the name, the dimension and the start-stop coordinates of each dimension of the array participating in the calculation in the many-core code.
Further, in this embodiment, after step S23, the method further includes:
s24: it is determined whether there is a loop in the slave core code.
If there are still loops from the kernel code, step S25 is performed: and acquiring the number of layers circulating from the core code and the start-stop index of each layer of circulation. That is, when there is a loop in the slave core code, loop parameters participating in the calculation in the slave core code are obtained, and the loop parameters include: the number of circulating layers and the start and stop indexes of each layer of circulation.
S26: and analyzing the character strings of the many-core codes to acquire data loading and unloading information in the many-core codes. Wherein, the data loading and unloading information comprises: and loading the loaded array name and index position information corresponding to the data block in the original whole array.
S27: and establishing a mapping relation between the master core and the slave core according to the calculation parameters participating in calculation in the original code, the calculation parameters participating in calculation in the many-core code, the matching relation between the calculation mode in the original code and the calculation mode in the many-core code, the cycle parameters and the data load and unload information.
Specifically, the data information of the local master-slave core participating in the calculation is combined with the matching information of the participating calculation mode and the information loaded and unloaded by the array loading to complete the data mapping between the master-slave core and the slave core, that is, the corresponding relationship between the data in the master core and the data in the slave core.
Further, the present embodiment further includes step S28: and determining a division mechanism of the data among different slave cores according to the mapping relation and the information loaded and unloaded by the data load. Wherein, the dividing mechanism comprises: non-redundant uniform partitioning, and global loading.
With continued reference to fig. 1, after the mapping relationship between the master core and the slave core is established, step S3 is executed: and according to the mapping relation, carrying out correctness verification on the many-core code to obtain a verification result.
In this embodiment, the verifying the correctness of the many-core code mainly includes: generating test codes and carrying out correctness verification through the running of the test codes. Specifically, step S3 includes the following processes:
s31: and according to the mapping relation, converting the core code into the main core code to generate a test code for testing the many-core code.
In this embodiment, the test code framework is entirely executed in the CPU of the main core. The method for converting the core code into the main core code mainly comprises the following steps: defining and converting the slave core data result under the main core framework; loading and unloading data by adopting a memory copying method; the calculation part keeps the original slave core calculation mode unchanged.
After the test code is generated, step S32 is executed: and running the test code and the many-core code.
The embodiment directly carries out compiling and debugging at the main core end. The debugging mainly comprises the following steps: different parameters are defined, such as: the dimensions of the array, the size of the array, etc. And after the debugging is passed, starting to run, and obtaining the running results of the test codes and the many-core codes.
S33: and judging whether the running result of the test code is consistent with the running result of the many-core code.
If the operation result of the test code is consistent with the operation result of the many-core code, step S34 is executed: and judging that the many-core code is correct.
If the running result of the test code is not consistent with the running result of the many-core code, executing step S35: and judging that the many-core code is wrong.
When it is determined that the many-core code is erroneous, step S4 is executed: and if the verification result has the error code, analyzing the error code to obtain an analysis result of the error code.
Specifically, step S4 includes the following processes:
s41: and comparing the running result of the test code with the running result of the many-core code, and determining the proportion of the error codes and the position distribution of the error codes.
S42: and judging whether the error codes exist in the whole data range or not according to the position distribution of the error codes.
If the error code exists in the entire data range, step S43 is executed: the error code is determined to be a global error code.
S44: and carrying out static analysis on the global error codes.
Specifically, the method of static analysis comprises:
s441: and verifying whether the slave core code completely covers the original data according to the mapping relation.
Specifically, for all data, it is seen whether the original data is completely covered according to the aggregation of indexed partitions in the slave kernel code. And for the data with redundant coverage, the position and the redundancy of the redundant data are further statistically analyzed. A typical redundant location is a location of a data slice. Redundancy 1 is: without redundancy, redundancy 2 is: data redundancy between adjacent slave cores. If the redundancy positions are cluttered or the redundancy is random, the probability of code error is higher.
S442: verifying the data and calculating the full coverage of the partitioning according to the cyclic hierarchy of task partitioning.
In this embodiment, the full coverage of the calculation partition is also a special form of the full coverage of the data, and mainly aims at the full coverage analysis of the array located at the left side of the equation in the calculation process, that is, the full coverage analysis of the array whose value is changed. These arrays must be fully-covered and non-redundant.
S443: and verifying index subscript information of the load and load data.
The data loaded and unloaded by the load is the data participating in the calculation, so that the final calculation result can be correct only by ensuring that the data loaded and unloaded are completely correct. Specifically, verifying the content includes: whether the outer index is divided according to the number of the secondary cores, whether the memory index is consistent with the original code or not, and whether the starting position of the data is the starting position of the data in the original array or not is verified if the conversion from Fortran to the C-like code is involved.
S444: the processing information of the boundary data is verified.
Specifically, the processing information verification of the boundary data mainly includes: whether the initial position and the end position of the array corresponding to each calculation have corresponding calculation or not and whether the remainder part of the data division is reasonably processed or not.
If the error code does not exist in the entire data range, step S45 is executed: the error code is determined to be a local error code.
S46: the localized error codes are analyzed.
The analysis of the local error code in this embodiment mainly includes: and analyzing whether the corresponding local position has errors, whether the index information of each dimensionality of the array is correct, and whether the head and tail of the data are uniformly divided.
S5: and correcting error of the error code and reporting information according to the analysis result.
Specifically, step S5 includes the following processes:
s51: and correcting the error codes according to the static analysis result to obtain an error correction result.
The method for correcting the code error in the embodiment mainly comprises the following steps: and (4) determining the digital information by converting the index subscript of the array index, dividing the data into full coverage and the like.
In the embodiment, after the many-core code is subjected to error code analysis, error correction is performed on the error code, and partial error codes can be automatically corrected by correcting the error code, so that the code development process is accelerated, and the code development efficiency is improved.
S52: and verifying the error correction result.
If the verification is passed, step S53 is executed: error code information is reported.
By reporting the error code information, debugging information can be provided for a user for the user to refer to for debugging, so that the debugging efficiency is improved.
If the verification is not passed, step S54 is executed: detailed error information is reported.
If the verification fails, the problem is relatively large, the user needs to debug the card by himself, and the user can debug the card by himself as comprehensively as possible by reporting detailed error information, so that the debugging efficiency and the accuracy of the debugging result are improved.
Example two
Referring to fig. 2 based on the embodiment shown in fig. 1, fig. 2 is a schematic structural diagram of a system for debugging many-core code according to an embodiment of the present application. As shown in fig. 2, the system for debugging many-core code in this embodiment mainly includes: the device comprises a code acquisition module, a mapping relation establishment module, a code verification module, an error code analysis module and an error correction and report module.
The code acquisition module is used for acquiring an original code and a many-core code. And the mapping relation establishing module is used for analyzing the original code and the many-core code and establishing the mapping relation between the master core and the slave core. And the code verification module is used for verifying the correctness of the many-core code according to the mapping relation and acquiring a verification result. And the error code analysis module is used for analyzing the error code to obtain the analysis result of the error code if the error code exists in the verification result. And the error correction and report module is used for correcting errors of the error codes and reporting information according to the analysis result.
The mapping relation establishing module comprises: the device comprises a first analysis unit, a second analysis unit, a third analysis unit, a fourth analysis unit and a mapping relation establishment unit. The first analysis unit is used for performing character string analysis on the original code to acquire calculation parameters, calculation modes and circulation parameters participating in calculation in the original code, and the calculation parameters comprise: the name and the dimension of the array participating in the calculation and the start-stop coordinates of each dimension, and the cycle parameters comprise: the number of circulating layers and the starting and stopping indexes of each layer of circulation; the second analysis unit is used for carrying out character string analysis on the many-core codes and acquiring the total number of the slave cores and the ID of the slave cores which participate in the calculation; the third analysis unit is used for carrying out character string analysis on the many-core code to obtain calculation parameters and calculation modes participating in calculation in the many-core code; the fourth analysis unit is used for performing character string analysis on the many-core code to acquire data loading and unloading information in the many-core code, wherein the data loading and unloading information comprises: loading the loaded array name and index position information corresponding to the data block in the original integral array; and the mapping relation establishing unit is used for establishing the mapping relation between the master core and the slave core according to the calculation parameters participating in calculation in the original code, the calculation parameters participating in calculation in the many-core code, the matching relation between the calculation mode in the original code and the calculation mode in the many-core code, the cycle parameters and the data loading and unloading information.
Further, the mapping relationship establishing module further includes: the device comprises a first judging unit and a circulation parameter acquiring unit. The first judging unit is used for judging whether a loop exists in the slave core code. And the loop parameter acquisition unit is used for acquiring the number of layers looped in the slave core code and the start-stop index of each layer loop when the slave core code has loops.
Further, the mapping relationship establishing module further includes: a partitioning mechanism determining unit, configured to determine a partitioning mechanism of data among different slave cores according to the mapping relationship and information loaded and unloaded by the data load, where the partitioning mechanism includes: non-redundant uniform partitioning, and global loading.
The code verification module further comprises: the device comprises a conversion unit, an operation unit and a second judgment unit. The conversion unit is used for converting the core code into the main core code according to the mapping relation and generating a test code for testing the many-core code; the operation unit is used for operating the test code and the many-core code; and the second judging unit is used for judging whether the running result of the test code is consistent with the running result of the many-core code, judging that the many-core code is correct if the running result of the test code is consistent with the running result of the many-core code, and judging that the many-core code is wrong if the running result of the test code is not consistent with the running result of the many-core code.
The error code analysis module comprises: the device comprises a comparison unit, a third judgment unit, a global error code analysis unit and a local error code analysis unit. The comparison unit is used for comparing the operation result of the test code with the operation result of the many-core code and determining the proportion of the error codes and the position distribution of the error codes. And a third judging unit, configured to judge whether the error code exists in the entire data range according to the position distribution of the error code, determine that the error code is a global error code if the error code exists in the entire data range, and determine that the error code is a local error code if the error code does not exist in the entire data range. The global error code analysis unit is used for carrying out static analysis on the global error codes; and the local error code analysis unit is used for analyzing the local error codes.
Further, the global error code analysis unit further includes: the first, second, third and fourth verification subunits. The first verification subunit is used for verifying whether the slave core code completely covers the original data according to the mapping relation; the second verification subunit is used for verifying data and calculating the full coverage of the division according to the task division of the cycle hierarchy; the third verification subunit is used for verifying the index subscript information of the loaded data; and the fourth verification subunit is used for verifying the processing information of the boundary data.
The error correction and reporting module includes: the device comprises an error correction unit, a verification unit, a first reporting unit and a second reporting unit. And the error correction unit is used for correcting the error codes according to the static analysis result to obtain an error correction result. The verification unit is used for verifying the error correction result, if the verification is passed, the first reporting unit is started, otherwise, the second reporting unit is started; the first reporting unit is used for reporting error code information, and the second reporting unit is used for reporting detailed error information.
The working principle and working method of the system for debugging many-core code in this embodiment have already been described in detail in the embodiment shown in fig. 1, and are not described herein again.
The above description is merely exemplary of the present application and is presented to enable those skilled in the art to understand and practice the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (8)
1. A method of debugging many-core code, the method comprising:
acquiring an original code and a many-core code;
analyzing the original code and the many-core code, and establishing a mapping relation between a master core and a slave core;
according to the mapping relation, carrying out correctness verification on the many-core code to obtain a verification result;
if the verification result contains an error code, analyzing the error code to obtain an analysis result of the error code;
error correction and information reporting are carried out on the error codes according to the analysis result;
analyzing the original code and the many-core code, and establishing a mapping relation between the master core and the slave core, wherein the mapping relation comprises:
analyzing the character string of the original code to obtain a calculation parameter, a calculation mode and a cycle parameter which participate in calculation in the original code, wherein the calculation parameter comprises: the name, the dimension and the start-stop coordinate of each dimension of the array participating in the calculation, and the loop parameters comprise: the number of layers of circulation and the start-stop index of each layer of circulation;
performing character string analysis on the many-core code to obtain the total number of the slave cores and the ID of the slave cores which participate in calculation;
analyzing the character strings of the many-core codes to obtain calculation parameters and calculation modes participating in calculation in the many-core codes;
analyzing the character string of the many-core code to acquire data loading and unloading information in the many-core code, wherein the data loading and unloading information comprises: loading the loaded array name and index position information corresponding to the data block in the original integral array;
and establishing a mapping relation between the master core and the slave core according to the calculation parameters participating in calculation in the original code, the calculation parameters participating in calculation in the many-core code, the matching relation between the calculation mode in the original code and the calculation mode in the many-core code, the cycle parameters and the data load-out information.
2. The method of claim 1, wherein after performing string parsing on the many-core code to obtain computation parameters and computation patterns of the many-core code that participate in computation, the method further comprises:
judging whether a loop exists in the slave core code;
if so, the number of layers to loop through the core code and the start-stop index of each layer of loop are obtained.
3. The method of claim 1, wherein after the mapping relationship between the master core and the slave core is established according to the computation parameters of the original code, the computation parameters of the many-core code, the matching relationship between the computation patterns of the original code and the computation patterns of the many-core code, the loop parameters, and the data load/unload information, the method further comprises:
determining a division mechanism of the data among different slave cores according to the mapping relation and the information loaded and unloaded by the data load, wherein the division mechanism comprises: non-redundant uniform partitioning, and global loading.
4. The method of claim 1, wherein the method for performing correctness verification on the many-core code according to the mapping relationship to obtain a verification result comprises:
according to the mapping relation, converting the core code into the main core code to generate a test code for testing the many-core code;
running the test code and the many-core code;
judging whether the running result of the test code is consistent with the running result of the many-core code;
if yes, judging that the many-core code is correct;
if not, the many-core code is judged to be wrong.
5. The method of claim 4, wherein analyzing the error code to obtain the analysis result of the error code comprises:
comparing the running result of the test code with the running result of the many-core code, and determining the proportion of error codes and the position distribution of the error codes;
judging whether the error codes exist in the whole data range or not according to the position distribution of the error codes;
if the error code exists in the whole data range, determining as a global error code;
performing static analysis on the global error codes;
if the error code does not exist in the whole data range, judging as a local error code;
and analyzing the local error codes.
6. The method of debugging many-core code according to claim 5, wherein the method of statically analyzing global error code comprises:
verifying whether the slave kernel code completely covers the original data or not according to the mapping relation;
verifying data and calculating the full coverage of division according to the task division of the cycle hierarchy;
verifying index subscript information of the loaded data;
the processing information of the boundary data is verified.
7. The method of debugging many-core code according to claim 6, wherein the method of error correction and information reporting for error codes according to the analysis result comprises:
correcting the error codes according to the static analysis result to obtain an error correction result;
verifying the error correction result;
if the verification is passed, reporting error code information;
if the verification fails, detailed error information is reported.
8. A system for debugging many-core code, the system comprising:
the code acquisition module is used for acquiring an original code and a many-core code;
the mapping relation establishing module is used for analyzing the original code and the many-core code and establishing the mapping relation between the master core and the slave core;
the code verification module is used for verifying the correctness of the many-core code according to the mapping relation to obtain a verification result;
the error code analysis module is used for analyzing the error code to obtain the analysis result of the error code if the error code exists in the verification result;
the error correction and report module is used for carrying out error correction and information report on the error codes according to the analysis result;
wherein, the mapping relationship establishing module comprises:
a first parsing unit, configured to perform string parsing on the original code, and obtain a calculation parameter, a calculation mode, and a loop parameter that participate in calculation in the original code, where the calculation parameter includes: the name, the dimension and the start-stop coordinate of each dimension of the array participating in the calculation, and the loop parameters comprise: the number of circulating layers and the starting and stopping indexes of each layer of circulation;
the second analysis unit is used for carrying out character string analysis on the many-core code and acquiring the total number of the slave cores and the ID of the slave cores which participate in the calculation;
the third analysis unit is used for carrying out character string analysis on the many-core code to obtain calculation parameters and calculation modes participating in calculation in the many-core code;
a fourth parsing unit, configured to perform character string parsing on the many-core code, and acquire data load-and-unload information in the many-core code, where the data load-and-unload information includes: loading the loaded array name and index position information corresponding to the data block in the original integral array;
and the mapping relation establishing unit is used for establishing the mapping relation between the master core and the slave core according to the calculation parameters participating in calculation in the original code, the calculation parameters participating in calculation in the many-core code, the matching relation between the calculation mode in the original code and the calculation mode in the many-core code, the cycle parameters and the data loading and unloading information.
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