CN117741413A - Detection system for detecting test needle plate of boundary scanning interconnection equipment - Google Patents

Abstract

The invention discloses a detection system for detecting a test needle board of boundary scan interconnection (Boundary Scan Interconnect; BSI) equipment, which is matched with a qualified circuit board to detect whether the test needle board of the BSI equipment is normal or not. The detection system includes a BSI control module and a joint test workgroup (Joint Test Action Group; JTAG) resistance detection module. The BSI control module is electrically connected with the JTAG resistance detection module and the test signal probe of the test needle board. Before the BSI device is powered on, the test signal probes are in contact with a plurality of test joints corresponding to the qualified circuit board in advance, so that the JTAG resistance detection module is utilized to detect the actual grounding resistance value of the test signal probes in advance. When the detection system compares any actual grounding resistance value to be out of the allowable range of the corresponding grounding resistance value, abnormal information is transmitted to prompt the probe number corresponding to the abnormal probe.

Description

Detection system for detecting test needle plate of boundary scanning interconnection equipment

Technical Field

The invention relates to a detection system, in particular to a detection system for detecting a test needle plate of boundary scanning interconnection equipment.

Background

The development of the electronic products is seen, and the intelligent electronic products not only enrich the daily life of human beings, but also gradually become indispensable living tools for the human beings. Along with the convenience of intelligent electronic products, there is an increasing amount of data to be transferred and operated in a shorter time, so that the integration of chips is also becoming more and more remarkable, especially for server chips that need to perform large data operations in a short time.

Moreover, the chips with extremely high integration level are densely distributed on the circuit board in a limited space, and once the connection of some chips is problematic, the chips are light and can cause partial functional abnormality of the circuit board, and the chips are heavy and can cause complete paralysis of the whole equipment where the circuit board is located and can not continue to operate. In the manufacture of circuit boards, circuits are typically printed on the circuit board, and chips with multiple pins are soldered to soldered locations on the printed circuit board using Surface Mount Technology (SMT) or other soldering techniques, which may include a plurality of pads or contacts. In such many bonding locations, it is inevitable that some pins or joints are not actually soldered to form empty solder (non-soldered contact), insufficient solder joint (insufficient solder contact area) or missolder (soldered to devices or pins not in contact), resulting in abnormal disconnection or abnormal short circuit.

Since the early chip size is larger than the current chip size and the early chip integration is lower than the current chip integration, enough space is available for the pins of all chips on the printed circuit board to extend outwards to expose the edges of the chips or pass through the printed circuit board to be exposed at the other side of the printed circuit board, the pins of each device can be sequentially contacted through the probes, and whether the interconnection condition between the pins of each device and the connecting circuit is normal or not is judged according to the response signals.

However, in the current chip, most of the pins (or bonding pads) are located at the bottom of the chip, and in other cases, there are many stacked chips, and the probes cannot reach the bottom of the chip or the narrow gaps between the chips at all to contact the pins of the chip. Due to the above, only Boundary Scan (Boundary Scan) technology can be used to detect the interconnection between the chip pins or device pins and the connection circuit.

In the boundary scanning technology, in a plurality of boundary joints which are accessible by a circuit board edge probe, a signal probe is used for sequentially inputting test signals in a scanning way, one or more corresponding signal output joints in the boundary joints detect actual response signals, and the actual response signals are compared with the due normal response signals, so that whether the interconnection condition of the whole circuit is normal or not is judged. Since the signal input contact and the signal output contact in the boundary contact generally pass through a plurality of pins and connecting circuits of a plurality of chips, once all actual response signals are consistent with corresponding normal response signals, the normal functions of each chip, device and connecting circuit in the circuit board can be basically confirmed.

Since the existing boundary scan technology is mainly used for detecting the interconnection condition of chips and devices on a circuit board, the boundary scan interconnection (Boundary Scan Interconnect; BSI) technology is also commonly called as a BSI device. When the existing BSI device actually detects a circuit board to be tested, it usually works with a joint test working group (Joint Test Action Group; JTAG) device to complete the detection, and the JTAG device can provide different JTAG signals as the test signals input to the boundary pads according to a specific timing sequence in accordance with the boundary scan requirement.

Because of the large number of probes, in order to ensure that each probe can actually contact the corresponding boundary contact of the circuit board, the probes are usually arranged on at least one test needle board, and JTAG lines are arranged in the test needle board to connect each probe, so that JTAG signals are transmitted to the corresponding probe according to time sequence. In order to confirm that the connection condition of the JTAG lines is normal, it is necessary to confirm in advance whether the JTAG lines are normal or not, that is, to perform self-test on the test needle board before performing boundary scan.

However, in the prior art, it is pre-determined whether the JTAG line is normal or not by powering up (power on) the BSI device and performing the initialization, and then pressing at least one test pin board onto a specific qualified circuit board to directly perform the test. Since one or more actual response signals may be detected at one or more signal output contacts when the test signals are sequentially inputted by using the signal probes in a scanning manner, the one or more corresponding actual response signals and the normal response signals must be checked and compared one by one when the test signals are inputted for each probe.

As can be seen from the above description, in the prior art, when the test needle board is tested by itself, the BSI device must be powered on (power on) and the initialization setting is completed, so that a lot of early waiting time is consumed. In addition, since the plurality of probes, the plurality of actual response signals and the normal response signals are checked and compared one by one in the later period, and the plurality of probes, the actual response signals and the normal response signals are arranged and combined in a plurality of ways, more later checking time is consumed to confirm whether the JTAG line is normal or not. Under the above circumstances, the present inventors consider that it is very necessary to develop a new self-detection technique, which can effectively shorten the above-mentioned early waiting time and the later investigation time, so as to improve the detection efficiency of self-detection.

Disclosure of Invention

In view of the prior art, it is generally necessary to perform self-test on the test board of the BSI apparatus with a long early waiting time and a long post-inspection time. The main objective of the present invention is to provide a testing system for testing a test pin board of a boundary scan interconnection device, so as to effectively shorten the foregoing early waiting time and the later inspection time. Accordingly, the present invention provides a test system for testing a test pin board of a boundary scan interconnection device.

The detection system is electrically connected to at least one test needle board of the boundary scan interconnection (Boundary Scan Interconnect; BSI) device and is matched with a qualified circuit board to detect whether the test needle board (particularly JTAG line) is normal or not. The detection system comprises a database, a BSI control module, a JTAG resistance detection module and a judgment module.

The database stores a plurality of probe numbers and a plurality of allowed ranges of grounding resistance values corresponding to a plurality of test signal probes of the test needle plate. The BSI control module is electrically connected with the test signal probes of the test needle board, and before the BSI equipment is powered on, the test signal probes are in contact with a plurality of test joints corresponding to the qualified circuit board in advance. The JTAG resistance detection module is electrically connected with the BSI control module, so as to detect a plurality of actual grounding resistance values of a plurality of probe numbers corresponding to the test signal probes in advance before the BSI equipment is powered on.

The judging module is electrically connected with the database and the JTAG resistance detecting module, so as to capture the actual grounding resistance values corresponding to the probe numbers and compare the actual grounding resistance values with the allowable ranges of the grounding resistance values. When any one of the actual grounding resistance values is compared and falls outside the allowable range of the corresponding grounding resistance value, the test signal probe corresponding to the corresponding probe number is judged to be at least one abnormal probe, and abnormal information is transmitted to prompt the probe number corresponding to the abnormal probe.

Based on the above-mentioned necessary technical means, in the derived preferred auxiliary technical means, the at least one test needle board includes an upper test needle board and a lower test needle board, and the upper test needle board and the lower test needle board are respectively disposed on the upper side and the lower side of the qualified circuit board. Preferably, the detection system further comprises a computer device, and the database and the judging module are arranged in the computer device. The computer device may further comprise a storage module communicatively connected to the determination module for storing the anomaly information. The detection system may further comprise a display, and the display is communicatively connected to the determination module for displaying the anomaly information.

Preferably, the BSI control module is disposed on the BSI device, and the JTAG resistance detection module is externally connected from the BSI device, wherein the JTAG resistance detection module is electrically connected to the BSI control module by a plurality of JTAG cables, and each JTAG cable includes a plurality of JTAG signal lines.

In summary, in the detection system for detecting the test probe card of the boundary scan interconnection device provided by the present invention, a plurality of actual ground resistance values of a plurality of test signal probes of the test probe card are detected in advance before the BSI device is powered on; it is clear that the above-mentioned early waiting time can be drastically reduced. Moreover, the actual grounding resistance value is compared with the allowable range of the grounding resistance value, and the actual response signal and the normal response signal are not used for checking and comparing one by one as described in the prior art; as is well known, the time required for the numerical comparison is necessarily much shorter than the time required for the signal comparison, so that the later examination time can be further greatly reduced, and the self-detection efficiency of the test needle board is further greatly improved.

Drawings

FIG. 1 is a schematic perspective view showing a testing system for testing a test pin board of a boundary-scan interconnect device and related components in the surroundings according to a preferred embodiment of the present invention; and

FIG. 2 is a functional block diagram of a test system for testing a test card of a boundary-scan interconnect device according to a preferred embodiment of the present invention.

Reference numerals illustrate:

1. detection system

11 BSI control module

12 JTAG resistance detection module

13. Computer device

131. Database for storing data

132. Judgment module

1321. Abnormality information presenting unit

133. Storage module

14. Operating device

15. Display device

2 BSI device

21. Upper test needle plate

211. Test signal probe

22. Lower test needle plate

221. Test signal probe

23. Detection platform

3. Qualified circuit board

31. Test contact

C JTAG cable

Detailed Description

The detection system for detecting the test needle board of the boundary scan interconnection device can be widely applied to various test needle boards for detecting various BSI devices, and therefore, the detection system is not described in detail herein, and only a preferred embodiment is exemplified for specific description. Moreover, the drawings in the various embodiments are in a very simplified form, and are not presented in an absolute precise scale, so as to facilitate a clear and concise description of the objects and features of the embodiments of the present inventions.

Referring to fig. 1 and 2, fig. 1 is a schematic perspective view showing a detection system for detecting a test needle board of a boundary scan interconnection device and related surrounding components according to a preferred embodiment of the invention; FIG. 2 is a functional block diagram of a test system for testing a test card of a boundary-scan interconnect device according to a preferred embodiment of the present invention. As shown in fig. 1 and 2, a test system (hereinafter referred to as a "test system") 1 for testing a test board of a boundary scan interconnection device is electrically connected to at least one test board (including an upper test board 21 and a lower test board 22 in the present embodiment) of a boundary scan interconnection (Boundary Scan Interconnect; BSI) device (hereinafter referred to as a "BSI device") 2, and is matched with a qualified circuit board 3 to test whether the upper test board 21 and the lower test board 22 are normal, preferably, the qualified circuit board 3 is a gold sample circuit board whose contact positions, circuit configuration and performance and functions are confirmed by multi-party cross test, which meets specific standard requirements (generally, the standard requirements are more strict than the requirements of mass production quarantine standards of circuit boards).

The detection system 1 comprises a BSI control module 11, a joint test workgroup (Joint Test Action Group; JTAG) resistance detection module 12, a computer device 13, an operating device 14 and a display 15. The computer device 13 is provided with a database 131, a judging module 132 and a storage module 133. The judging module 132 is electrically connected to the database 131 in the computer device 13 and electrically connected to the JTAG resistance detecting module 12 outside the computer device 13. The storage module 133 is communicatively connected to the determination module 132.

The upper test needle plate 21 has a plurality of test signal probes 211 (typically, there are tens or even hundreds of test signal probes, only two of which are drawn in fig. 1 and only one of which is indicated), and the lower test needle plate 22 has a plurality of test signal probes 221 (typically, there are tens or even hundreds of test signal probes, only four of which are drawn in fig. 1 and only one of which is indicated). Each of the test signal probes 211 and 221 has a respective one of the probe numbers.

The database 131 records the allowable range of the ground resistance value corresponding to each probe number, and the corresponding relationship is shown in table one.

Table one: probe number and grounding resistance value allowable range corresponding relation table

Probe numbering	Test needle plate	Ground resistance value allowable range
			0001	Upper test needle plate	0.11～0.12Ω
0002	Upper test needle plate	0.05～0.06Ω
			0003	Lower test needle plate	0.09～0.10Ω
0004	Lower test needle plate	0.05～0.06Ω
			0005	Lower test needle plate	0.18～0.20Ω
0006	Lower test needle plate	0.30～0.32Ω

The BSI control module 11 may be built in the BSI apparatus 2 and electrically connected to the test signal probes 211 of the upper test needle board 21 and the test signal probes 221 of the lower test needle board 22. Before the BSI apparatus 2 is powered on (power on), on the test platform 23 of the BSI apparatus 2, the upper test needle board 21 and the lower test needle board 22 are respectively disposed on the upper side and the lower side of the qualified circuit board 3, and then the upper test needle board 21 and the lower test needle board 22 are respectively pressed towards the qualified circuit board 3, so that the test signal probes 211 and 221 are in contact with a plurality of test contacts 31 corresponding to the qualified circuit board 3 in advance, and these test contacts 31 are usually located at the edge of the qualified circuit board 3 or the boundary of a specific functional module interface or interface of the qualified circuit board 3, but the boundary of the specific functional module interface or interface is not necessarily located at the edge of the qualified circuit board 3.

JTAG resistance detection module 12 is electrically connected to BSI control module 11 by a plurality of JTAG cables C, each JTAG cable C including a plurality (typically 4 or 5) JTAG signal lines. Thus, a plurality of actual ground resistance values of a plurality of probe numbers corresponding to the test signal probes 211 and 221 can be detected in advance before the BSI apparatus 2 is powered on.

Preferably, the JTAG resistor detection module 12, the BSI control module 11, any one of the test signal probes 211 and 221, and the qualified circuit board 3 form a detection loop, and a sampling resistor may be disposed in each detection loop, and by measuring the voltage division across the sampling resistor, the actual ground resistance between the test signal probes 211 and 221 and the system ground area of the qualified circuit board 3 may be calculated.

The determining module 132 captures a plurality of actual ground resistance values corresponding to the plurality of probe numbers, and compares the plurality of actual ground resistance values with a plurality of allowable ground resistance values respectively. The judging module 132 further includes an abnormal information prompting unit 1321, and when the judging module 132 compares that any one of the at least one actual grounding resistance values falls outside the allowable range of the corresponding grounding resistance value, the detecting signal probes 211 and 221 corresponding to the corresponding probe numbers are determined as at least one abnormal probe.

At this time, the abnormality information presentation unit 1321 transmits abnormality information to present the probe number corresponding to the abnormality probe, and displays the probe number corresponding to the abnormality probe presented by the abnormality information on the display 15. At this time, the user can retest the test to confirm by operating the operating device 14, or directly store the abnormality information in the storage module 133. The abnormal information stored in the storage module 133 may be further transmitted to a data server disposed in the control center, the management center or the cloud end by operating the operating device 14, so as to be used for statistical analysis of big data in the future.

Specifically, taking the detection situation shown in table two as an example, when the determination module 132 compares the actual ground resistance value with the corresponding allowable range of the ground resistance value, it can be determined that the actual ground resistance values of the test signal probes 221 with probe numbers 0003 and 0006 are outside the allowable range of the ground resistance value, which means that all the test signal probes 211 in the upper test needle board 21 are normal, and the test signal probes 221 with probe numbers 0003 and 0006 in the lower test needle board 22 are abnormal probes.

And (II) table: probe state judgment result correspondence table

In this case, abnormality information indicates abnormality of the test signal probes 221 with probe numbers 0003 and 0006 in the lower test needle board. It should be emphasized that the reason for the abnormality of the test signal probe 221 cannot be excluded from the JTAG cable C abnormality (e.g., cable breakage or poor contact of the end points), so that it is confirmed that the abnormality of the test signal probe 221 itself (e.g., breakage or bending of the probe results in the test contact 31 which does not actually contact the qualified circuit board 3) is determined after further confirming that the possibility of the abnormality of the JTAG cable C is excluded.

In view of the above, in the inspection system 1 provided by the present invention, the actual ground resistance values of the plurality of test signal probes 211 and 221 of the upper test needle board 21 and the lower test needle board 22 are inspected in advance before the BSI apparatus 2 is powered on; it is clear that the above-mentioned early waiting time can be drastically reduced. Moreover, the actual grounding resistance value is compared with the allowable range of the grounding resistance value, and the actual response signal and the normal response signal are not used for checking and comparing one by one as described in the prior art; as is well known, the time required for the numerical comparison is necessarily much shorter than the time required for the signal comparison, so that the post-inspection time can be further greatly reduced, and the self-inspection efficiency of the upper test needle board 21 and the lower test needle board 22 can be greatly improved.

With the foregoing detailed description of the preferred embodiments, it is intended to more clearly describe the features and spirit of the invention, but not to limit the scope of the invention by the above disclosed preferred embodiments. On the contrary, the intent is to cover all modifications and equivalent arrangements included within the scope of the appended claims.

Claims (7)

1. A detection system for detecting a test needle board of boundary scan interconnection equipment, which is electrically connected with at least one test needle board of boundary scan interconnection BSI equipment and is matched with a qualified circuit board to detect whether the at least one test needle board is normal, the detection system comprises:

the database stores a plurality of probe numbers and a plurality of allowed ranges of grounding resistance values corresponding to a plurality of test signal probes of the at least one test needle plate;

the BSI control module is electrically connected with the test signal probes of the at least one test needle plate, and before the BSI equipment is powered on, the test signal probes are in contact with a plurality of test joints corresponding to the qualified circuit board in advance;

the joint test working group JTAG resistance detection module is electrically connected with the BSI control module, so as to detect a plurality of actual grounding resistance values of the probe numbers corresponding to the test signal probes in advance before the BSI equipment is powered on;

the judging module is electrically connected with the database and the JTAG resistance detecting module, so as to capture the actual grounding resistance values corresponding to the probe numbers, compare the actual grounding resistance values with the allowable ranges of the grounding resistance values, judge the test signal probe corresponding to the probe number as at least one abnormal probe when any one of the actual grounding resistance values is out of the allowable range of the corresponding grounding resistance value, and transmit abnormal information to prompt the probe number corresponding to the at least one abnormal probe.

2. The inspection system for inspecting a test board of a boundary scan interconnect device of claim 1, wherein the at least one test board comprises an upper test board and a lower test board, and the upper test board and the lower test board are disposed on an upper side and a lower side of the qualified circuit board, respectively.

3. The test system for testing a test card of a boundary scan interconnect device of claim 1, further comprising a computer device, wherein the database and the determination module are disposed in the computer device.

4. The test system for testing a test card of a boundary-scan interconnect device of claim 3, wherein the computer device further comprises a storage module communicatively coupled to the determination module for storing the anomaly information.

5. The inspection system for inspecting a test card of a boundary-scan interconnect device of claim 1, further comprising a display communicatively coupled to the determination module for displaying the anomaly information.

6. The test system for testing the test card of the boundary-scan interconnect device of claim 1, wherein the BSI control module is disposed on the BSI device and the JTAG resistance testing module is external from the BSI device.

7. The inspection system for inspecting a test card of a boundary-scan interconnect device of claim 1, wherein the JTAG resistor inspection module is electrically connected to the BSI control module by a plurality of JTAG cables, each of the JTAG cables including a plurality of JTAG signal lines.