CN117741197A - Chip test fixture for inhibiting third harmonic - Google Patents
Chip test fixture for inhibiting third harmonic Download PDFInfo
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- CN117741197A CN117741197A CN202311763323.1A CN202311763323A CN117741197A CN 117741197 A CN117741197 A CN 117741197A CN 202311763323 A CN202311763323 A CN 202311763323A CN 117741197 A CN117741197 A CN 117741197A
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- 238000012360 testing method Methods 0.000 title claims abstract description 54
- 230000002401 inhibitory effect Effects 0.000 title abstract description 6
- 230000001629 suppression Effects 0.000 claims abstract description 86
- 230000005540 biological transmission Effects 0.000 claims abstract description 38
- 239000003990 capacitor Substances 0.000 claims description 39
- 230000001939 inductive effect Effects 0.000 claims 2
- 238000012345 traction test Methods 0.000 abstract description 5
- 238000000034 method Methods 0.000 abstract description 4
- 230000005764 inhibitory process Effects 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 12
- 230000009466 transformation Effects 0.000 description 3
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- 238000004088 simulation Methods 0.000 description 1
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Abstract
The invention discloses a chip test fixture for inhibiting third harmonic, which comprises a third harmonic inhibition unit, a first transmission line, a second transmission line, a radio frequency input port, a radio frequency output port and a chip to be tested; the radio frequency input port is connected with the first end of the first transmission line, the second end of the first transmission line is connected with the input end of the chip to be tested, the first end of the second transmission line is connected with the output end of the chip to be tested, the second end of the second transmission line is connected with the radio frequency output port, and the third harmonic suppression unit is connected with the input end of the chip to be tested or the output end of the chip to be tested. According to the invention, the third harmonic suppression unit is arranged at the input end or the output end of the chip to be tested, so that the third harmonic impedance of the chip to be tested is converted into short-circuit impedance, the influence of the third harmonic is reduced, and the radio frequency performance of the chip can be more comprehensively evaluated in the chip load traction test process; and a feeding unit is arranged on the clamp to supply power for the chip to be tested, so that the complexity and the testing cost of the testing system are reduced.
Description
Technical Field
The invention relates to the technical field of radio frequency chip testing, in particular to a chip testing clamp for inhibiting third harmonic.
Background
In the field of radio frequency chip testing, load pulling is a commonly used method for evaluating the radio frequency performance of a chip and the corresponding target impedance thereof. Fig. 1 is a system block diagram of a conventional load pull test, which sequentially includes a radio frequency signal source, a source impedance tuner, an input dc bias, a chip fixture to be tested, an output dc bias, a load impedance tuner, a power meter, and a voltage source. The chip clamp to be tested is an important component and mainly comprises the functions of placing the chip to be tested, transmitting radio frequency signals, connecting a direct current bias device to feed the chip, radiating the chip and the like, and the quality of the clamp design can directly influence the performance and the accuracy of the load traction test.
The conventional chip fixture to be tested is shown in fig. 1 or fig. 2, wherein the input and output ends of the chip to be tested are connected by two sections of transmission lines and are connected with an external direct current bias device to supply power to the chip. The test clip has two disadvantages:
1. the fixture itself does not contain a direct current feed circuit, and an additional direct current bias device needs to be connected to feed the chip, so that the test cost and the complexity of the circuit are increased.
2. The input and output of the traditional chip testing clamp are only connected by a transmission line, the third harmonic of the chip to be tested is not controlled, the existing load traction tuner can only tune the fundamental wave and the second harmonic impedance, the third harmonic impedance cannot be controlled, and the third harmonic impedance also has an influence on the performance of the chip, so that the traditional clamp and the load traction testing system cannot measure the optimal performance of the chip under the control of both the second harmonic and the third harmonic.
The information disclosed in this background section is only for enhancement of understanding of the general background of the invention and should not be taken as an acknowledgement or any form of suggestion that this information forms the prior art already known to a person of ordinary skill in the art.
Disclosure of Invention
The invention aims to provide a chip test fixture for inhibiting third harmonic, which can control the load of the third harmonic frequency of a chip to be tested to a short circuit point and improve the test efficiency.
To achieve the above object, an embodiment of the present invention provides a chip test fixture for suppressing a third harmonic, the fixture including: the device comprises a third harmonic suppression unit, a first transmission line, a second transmission line, a radio frequency input port, a radio frequency output port and a chip to be tested;
the radio frequency input port is connected with the first end of the first transmission line, the second end of the first transmission line is connected with the input end of the chip to be tested, the first end of the second transmission line is connected with the output end of the chip to be tested, the second end of the second transmission line is connected with the radio frequency output port, and the third harmonic suppression unit is connected with the input end of the chip to be tested or the output end of the chip to be tested.
In one or more embodiments of the present invention, the fixture further includes a feeding unit, the feeding unit includes a first feeding microstrip line, a first end of the first feeding microstrip line is connected to a first voltage source, and a second end of the first feeding microstrip line is connected to a feeding port of the chip to be tested.
In one or more embodiments of the present invention, the third harmonic suppression unit includes a first harmonic suppression module;
the first end of the first harmonic suppression module is open or connected with the second voltage source, and the second end of the first harmonic suppression module is connected with the input end of the chip to be tested or the output end of the chip to be tested.
In one or more embodiments of the present invention, the third harmonic suppression unit includes a first harmonic suppression module and a first capacitor;
the first end of the first harmonic suppression module is connected with the first end of the first capacitor, or the first end of the first harmonic suppression module is connected with the first end of the first capacitor and the second voltage source; the second end of the first capacitor is connected with the ground potential, and the second end of the first harmonic suppression module is connected with the input end of the chip to be detected or the output end of the chip to be detected.
In one or more embodiments of the present invention, the third harmonic suppression unit includes a first harmonic suppression module, a second harmonic suppression module, a first capacitor, and a switching unit;
the first end of the first harmonic suppression module is open or connected with a second voltage source;
the first end of the second harmonic suppression module is connected with the first end of the first capacitor or the first end of the second harmonic suppression module is connected with the first end of the first capacitor and the second voltage source;
the first end of the switch unit is connected with the input end of the chip to be tested or the output end of the chip to be tested, the second end of the switch unit is connected with the second end of the first harmonic suppression module, the third end of the switch unit is connected with the second end of the second harmonic suppression module, and the switch unit is used for controlling the chip to be tested to be connected with the first harmonic suppression module or the second harmonic control module.
In one or more embodiments of the present invention, the first harmonic rejection module includes a first microstrip line having an electrical length θ 1 Satisfy 25 DEG < theta 1 ＜35°。
In one or more embodiments of the present invention, the first harmonic rejection module includes a first microstrip line having an electrical length θ 1 Satisfy 55 DEG < theta 2 ＜65°。
In one or more embodiments of the present invention, the first harmonic rejection module includes a first microstrip line having an electrical length θ 1 Satisfy 25 DEG < theta 1 Less than 35 DEG; the second harmonic suppression module comprises a second microstrip line with an electrical length theta 2 Satisfy 55 DEG < theta 2 ＜65°。
In one or more embodiments of the present invention, the chip test fixture further includes an inductance unit, a first end of the inductance unit being connected to the second voltage source, and a second end of the inductance unit being connected to the third harmonic rejection unit.
In one or more embodiments of the present invention, the chip test fixture includes a circuit board for fixing the third harmonic suppression unit, the first transmission line, the second transmission line, the radio frequency input port, and the radio frequency output port, and a center of the circuit board fixes the chip to be tested.
Compared with the prior art, the chip test fixture for inhibiting the third harmonic is characterized in that the third harmonic inhibition unit is arranged at the input end or the output end of the chip to be tested, so that the third harmonic impedance of the chip to be tested is converted into short-circuit impedance, the influence of the third harmonic is reduced, and the radio frequency performance of the chip can be more comprehensively evaluated in the chip load traction test process; and a feeding unit is arranged on the clamp to supply power for the chip to be tested, so that the complexity and the testing cost of the testing system are reduced.
Drawings
FIG. 1 is a block diagram of a prior art chip fixture to be tested;
FIG. 2 is a block diagram of a prior art chip fixture to be tested;
FIG. 3 is a schematic diagram of a third harmonic suppression chip test fixture according to example 1;
FIG. 4 is a schematic diagram of a third harmonic suppression chip test fixture according to example 2;
FIG. 5 is a schematic diagram of a third harmonic suppression chip test fixture according to example 3;
FIG. 6 is a schematic diagram of a third harmonic rejection chip test fixture according to example 4;
FIG. 7 is a construction diagram of an implementation of a chip test jig for suppressing third harmonics according to embodiment 4;
FIG. 8 is a schematic diagram of a third harmonic suppression chip test fixture according to example 5;
FIG. 9 is a schematic diagram of a third harmonic suppression chip test fixture according to example 6;
FIG. 10 is a construction diagram of an implementation of a chip test jig for suppressing third harmonics according to embodiment 6;
FIG. 11 is a harmonic rejection simulation diagram of a chip test fixture to reject third harmonics in accordance with one or more embodiments of the present invention.
Detailed Description
The following detailed description of embodiments of the invention is, therefore, to be taken in conjunction with the accompanying drawings, and it is to be understood that the scope of the invention is not limited to the specific embodiments.
Throughout the specification and claims, unless explicitly stated otherwise, the term "comprise" or variations thereof such as "comprises" or "comprising", etc. will be understood to include the stated element or component without excluding other elements or components.
The term "coupled" or "connected" in this specification includes both direct and indirect connections. An indirect connection is a connection made through an intermediary, such as an electrically conductive medium, which may have parasitic inductance or parasitic capacitance; indirect connections may also include connections through other active or passive devices, such as through circuits or components such as switches, follower circuits, and the like, that accomplish the same or similar functional objectives. Furthermore, in the present invention, terms such as "first," "second," and the like, are used primarily to distinguish one technical feature from another, and do not necessarily require or imply a certain actual relationship, number or order between the technical features.
Example 1
As shown in fig. 3, the present embodiment provides a chip testing fixture for suppressing third harmonic, which includes a circuit board, a third harmonic suppression unit 1, a first transmission line 2, a second transmission line 3, a radio frequency input port 4, and a radio frequency output port 5, and a chip 6 to be tested is fixed in the center of the circuit board.
The radio frequency input port 4 is connected to a first end of the first transmission line 2, a second end of the first transmission line 2 is connected to an input end of the chip 6 to be tested, a first end of the second transmission line 3 is connected to an output end of the chip 6 to be tested, a second end of the second transmission line 3 is connected to the radio frequency output port 5, the third harmonic suppression unit 1 is connected to an input end of the chip 6 to be tested or an output end of the chip 6 to be tested, and the third harmonic suppression unit 1 is used for suppressing third harmonic impedance. It can be understood that the third harmonic suppression unit 1 is connected to the input terminal of the chip 6 to be tested or the output terminal of the chip 6 to be tested through a microstrip line.
In one embodiment, the third harmonic suppression unit 1 includes a first harmonic suppression module, a first end of the first harmonic suppression module is open, and a second end of the first harmonic suppression module is connected to an input end of the chip 6 to be detected or an output end of the chip 6 to be detected to suppress third harmonic impedance of the input end or third harmonic impedance of the output end of the chip 6 to be detected.
In one embodiment, the first harmonic suppression module includes a first microstrip line TL1, and an electrical length θ of the first microstrip line TL1 1 Satisfy 25 DEG < theta 1 ＜35°。
In the electric length range, the third harmonic of the first end of the first microstrip line TL1 is in an open circuit state, and the third harmonic of the output end of the parallel access chip is converted into a short circuit state after passing through the first microstrip line TL1, so that the efficiency of the load traction test is improved.
Example 2
As shown in fig. 4, this embodiment is different from embodiment 1 in that: the third harmonic suppression unit 1 includes a first harmonic suppression module and a first capacitor C1, in an embodiment, the first harmonic suppression module includes a second microstrip line TL2, a first end of the second microstrip line TL2 is connected to a first end of the first capacitor C1, a second end of the first capacitor C1 is connected to a ground potential, and a second end of the second microstrip line TL2 is connected to an input end of the chip 6 to be tested or an output end of the chip 6 to be tested.
In one embodiment, the electrical length θ of the second microstrip line TL2 2 Satisfy 55 DEG < theta 2 ＜65°。
In the electrical length range, the second microstrip TL2 is approximately equivalent to a half-wavelength microstrip line at the third harmonic frequency, the first end of the second microstrip TL2 is connected with the first capacitor C1, the first capacitor C1 is a radio frequency grounding capacitor, the third harmonic impedance at the connection point of the first end of the second microstrip TL2 and the first capacitor C1 is at a short-circuit point, after the second microstrip TL2 passes through the half-wavelength microstrip line, the third harmonic impedance at the connection point of the second microstrip TL2 and the output end of the chip 6 to be tested is still at the short-circuit point, and the third harmonic of the chip 6 to be tested is controlled at the short-circuit point by the method, so that the efficiency of load traction test is improved.
Example 3
As shown in FIG. 5, the present embodiment differs from embodiment 1 in thatThe third harmonic suppression unit 1 comprises a first harmonic suppression module, a second harmonic suppression module, a first capacitor C1 and a switch unit K1, wherein in one embodiment, the first harmonic suppression module comprises a first microstrip line TL1, and the electrical length theta of the first microstrip line TL1 1 Satisfy 25 DEG < theta 1 The second harmonic suppression module comprises a second microstrip line TL2, and the electrical length theta of the second microstrip line TL2 is less than 35 DEG 2 Satisfy 55 DEG < theta 1 ＜65°。
In one embodiment, the first end of the first microstrip line TL1 is open, the first end of the second microstrip line TL2 is connected to the first end of the first capacitor C1, and the second end of the first capacitor C1 is connected to the ground potential.
The first end of the switch unit K1 is connected with the input end of the chip 6 to be tested or the output end of the chip 6 to be tested, the second end of the switch unit K1 is connected with the second end of the first microstrip line TL1, the third end of the switch unit K1 is connected with the second microstrip line TL2, and the switch unit K1 is used for controlling the chip 6 to be tested to be connected with the first harmonic suppression module or the second harmonic control module. Based on the control of the switching unit K1 of the present embodiment, the output end or the input end of the chip 6 to be tested is selectively connected to the first harmonic suppression module or the second harmonic control module.
Example 4
As shown in fig. 6, this embodiment is different from embodiment 1 in that: the chip test fixture further includes a power supply unit. The feeding unit 7 includes a first feeding unit 71, where the first feeding unit includes a first feeding microstrip line, a first end of which is connected to a first voltage source through a power line, and a second end of which is connected to a feeding port of the chip 6 to be tested. The first feeding unit 71 is used for supplying power to the chip to be tested, and is used for replacing a traditional direct current bias device externally connected with the clamp to be tested, so that the complexity and the testing cost of the testing system are reduced.
It can be understood that the third harmonic suppression unit 1 is connected to the second voltage source through the inductance unit L1 and the power line to form a second feeding unit 72, and the second feeding unit 72 is used for supplying power to the chip to be tested. Specifically, a first end of the inductance unit L1 is connected to a second voltage source through a power line, and a second end of the inductance unit L1 is connected to the third harmonic suppression unit 1. The second feeding unit 72 is used for supplying power to the chip 6 to be tested, and is used for replacing a direct current bias device externally connected with a traditional clamp to be tested, so that the complexity and the testing cost of the testing system are reduced.
In other alternative embodiments, the second feeding unit 72 may not include the inductance unit L1, that is, the third harmonic suppression unit 1 is connected to the second voltage source through a power line to constitute the second feeding unit 72.
As shown in fig. 7, the chip 6 to be tested includes a feeding port 61 of the chip to be tested, which is connected to a first feeding unit 71 on the circuit board 9 and is connected to a first voltage source Vgs through a first power line 81, it being understood that the first feeding unit 71 includes a first feeding microstrip line.
The input end 63 of the chip to be tested is connected with the radio frequency input port 4 through the first transmission line 2, and the output end 62 of the chip to be tested is connected with the radio frequency output port 5 through the second transmission line 3. In one embodiment, the first transmission line 2 and the second transmission line 3 are microstrip lines.
The first microstrip line TL1 has a fundamental center operating frequency of 2.1GHz and an electrical length θ of 30 °, and the first microstrip line TL1 is a quarter-wavelength impedance transformation line at the third harmonic of 6.3 GHz.
In an embodiment, the inductance unit L1 includes a surface-mounted inductance L1, a first end of the first microstrip line TL1 is connected to the surface-mounted inductance L1 through the microstrip line 83, the surface-mounted inductance L1 is connected to a first end of the second power line 82 through the microstrip line 83, and a second end of the second power line 82 is connected to the second voltage source V DD . As can be seen from fig. 7, in the present embodiment, the surface-mount inductor L1 can be moved between a set of parallel microstrip lines 83, and the equivalent electrical length of the first microstrip line TL1 is changed by moving the position of the surface-mount inductor L1.
The first microstrip line TL1 changes the 6.3GHz open-circuit impedance at the connection of the first microstrip line TL1 and the surface-mount inductor L1 into the short-circuit impedance at the connection of the first microstrip line TL1 and the output end 62 of the chip to be tested, and controls the third harmonic at the short-circuit point. The third harmonic impedance of the chip working at 2.1GHz can be controlled to be short-circuit impedance through the embodiment, so that the performance of the chip can be tested and evaluated more comprehensively.
Example 5
As shown in fig. 8, this embodiment differs from embodiment 4 in that: the third harmonic suppression unit 1 comprises a first harmonic suppression module and a first capacitor C1, wherein the first harmonic suppression module comprises a second microstrip line TL2, and in one embodiment, the second microstrip line TL2 has an electrical length θ 2 Satisfy 55 DEG < theta 1 ＜65°。
The first end of the second microstrip line TL2 is connected to the first end of the first capacitor C1 and the second voltage source, the second end of the first capacitor C1 is connected to the ground potential, the second end of the second microstrip line TL2 is connected to the input end of the chip 6 to be tested or the output end of the chip 6 to be tested, and the second harmonic suppression module is configured to suppress third harmonic impedance of the input end or the output end of the chip 6 to be tested.
The feeding unit 7 comprises a first feeding unit 71, wherein the first feeding unit 71 comprises a first feeding microstrip line, a first end of which is connected to a first voltage source, and a second end of which is connected to a feeding port of the chip 6 to be tested. The first feeding unit 71 is used for supplying power to the chip to be tested, so as to replace a traditional direct current bias device externally connected with the clamp to be tested, and reduce the complexity and the testing cost of the testing system.
It can be understood that the second microstrip line TL2 is connected to the second voltage source through the power line and the inductance unit L1 to form a second feeding unit 72, and the second feeding unit 72 is configured to supply power to the chip 6 to be tested. The first end of the inductance unit L1 is connected to a power line, the power line is connected to a second voltage source, and the second end of the inductance unit L1 is connected to a second microstrip line TL2.
It is understood that in other embodiments, the second feeding unit 72 may not include the inductance unit L1, that is, the second microstrip line TL2 is connected to the second voltage source through the power line to form the second feeding unit 72.
Example 6
As shown in fig. 9, this embodiment differs from embodiment 4 in that: the third harmonic suppression unit 1 includes a first harmonic suppression module, a second harmonic suppression module, a first capacitor C1, and a switching unit K1. Wherein the first harmonic rejection module comprises a first microstrip line TL1 and the second harmonic rejection module comprises a second microstrip line TL2.
The first end of the first microstrip line TL1 is connected with a second voltage source, the first end of the second microstrip line TL2 is connected with the first end of the first capacitor C1 and the second voltage source, the second end of the first capacitor C1 is connected with the ground potential, the first end of the switch unit K1 is connected with the input end of the chip 6 to be tested or the output end of the chip 6 to be tested, the second end of the switch unit K1 is connected with the second end of the first microstrip line TL1, the third end of the switch unit K1 is connected with the second end of the second microstrip line TL2, and the switch unit K1 is used for controlling the chip 6 to be tested to be connected with the first harmonic suppression module or the second harmonic control module.
As shown in fig. 10, the chip 6 to be tested includes a feeding port 61 of the chip to be tested, which is connected to a first feeding unit 71 on the circuit board 9 and is connected to a first voltage source Vgs through a first power line 81, it being understood that the first feeding unit 71 includes a first feeding microstrip line.
The input end 63 of the chip to be tested is connected with the radio frequency input port 4 through the first transmission line 2, and the output end 62 of the chip to be tested is connected with the radio frequency output port 5 through the second transmission line 3. In one embodiment, the first transmission line 2 and the second transmission line 3 are microstrip lines.
The first microstrip line TL1 has a fundamental center operating frequency of 2.1GHz and an electrical length θ of 30 °, and the first microstrip line TL1 is a quarter-wavelength impedance transformation line at the third harmonic of 6.3 GHz.
The second microstrip line TL2 has a fundamental center operating frequency of 2.1GHz and an electrical length θ of 60 °, and the second microstrip line TL2 is a half wavelength impedance transformation line at the third harmonic of 6.3 GHz. The first end of the second microstrip line TL2 is connected to the first end of the first capacitor C1, in an embodiment, the first capacitor C1 is a radio frequency grounded capacitor, and the second end of the first capacitor C1 is connected to the ground potential. In one embodiment, the ground potential may be a via to ground on the circuit board 9.
The first end of the switch unit K1 is connected with the output end of the chip 6 to be tested, the second end of the switch unit K1 is connected with the first microstrip line TL1, the third end of the switch unit K1 is connected with the second microstrip line TL2, and the switch unit K1 is used for controlling the chip 6 to be tested to be connected with the first harmonic suppression module or the second harmonic control module. In one embodiment, the switch unit K1 is a MEMS switch chip.
In an embodiment, the inductance unit L1 includes a surface-mount inductance L1, and the first capacitor C1 includes a surface-mount capacitor C1; the first end of the first microstrip line TL1 is connected with the inductance unit L1 through the microstrip line 83, the surface-mounted inductance L1 is connected with the first end of the second power line 82 through the microstrip line 83, the first end of the second microstrip line TL2 is connected with the surface-mounted inductance L1 through the microstrip line 83, the surface-mounted inductance L1 is connected with the first end of the second power line 82 through the microstrip line 83, and the second end of the second power line 82 is connected with the second voltage source V DD 。
As can be seen from fig. 10, in the present embodiment, the surface-mount inductor L1 can be moved between a set of parallel microstrip lines 83, and the equivalent electrical length of the first microstrip line TL1 is changed by moving the position of the surface-mount inductor L1. The surface-mount capacitor C1 can be moved between a set of parallel microstrip lines 83, and the equivalent electrical length of the second microstrip line TL2 is changed by moving the position of the surface-mount capacitor C1.
By the control of the switching unit K1 in this embodiment, the third harmonic can be controlled at the short-circuit point by changing the 6.3GHz open-circuit resistance of the point where the first microstrip line TL1 is connected to the surface-mount inductor L1 to the short-circuit resistance of the point where the first microstrip line TL1 is connected to the output terminal 62 of the chip to be tested, or the third harmonic can be controlled at the short-circuit point by changing the 6.3GHz short-circuit resistance of the point where the second microstrip line TL2 is connected to the surface-mount capacitor C1 to the short-circuit resistance of the point where the second microstrip line TL2 is connected to the output terminal 62 of the chip to be tested. The third harmonic of the chip working at 2.1GHz can be controlled to be short-circuit impedance through the embodiment, and the performance of the chip can be tested and evaluated more comprehensively.
The first feeding unit 71 is connected with a first voltage source Vgs through a first power line 81 to supply power to the chip to be tested, and is used for replacing a direct current bias device externally connected with a traditional clamp to be tested, so that the complexity and the testing cost of a testing system are reduced.
The first harmonic suppression module or the second harmonic suppression module passes through the second power line82, the inductance unit L1 and the second voltage source V DD After being connected, the second feeding unit 72 is formed, and the second feeding unit 72 is used for supplying power to the chip 6 to be tested. The first end of the inductance unit L1 is connected with the second power line 82, and the second power line 82 is connected with the second voltage source V DD The second end of the inductance unit L1 is connected to the first harmonic suppression module or the second harmonic suppression module. It will be appreciated that in other embodiments, the second feeding unit 72 may not include the inductance unit L1, and a harmonic suppression module or a second harmonic suppression module may be directly connected to the second voltage source V via the second power line 82 DD A first end of an inductance unit L1 and a second voltage source V are connected to form a second feeding unit 72 DD Connected to power the chip 6 to be tested.
As shown in fig. 11 (a), the third harmonic impedance Za at the chip pin to be tested is controlled to Zb after passing through the third harmonic suppression unit 1 of the chip test fixture for suppressing harmonics proposed by the invention. As shown in fig. 11 (b), when the third harmonic control is not performed on the chip to be tested, the third harmonic impedance Za may be any position in the Smith chart, and after the third harmonic suppression in this scheme, the impedance is in the area close to the short-circuit point in fig. 11 (c).
The foregoing descriptions of specific exemplary embodiments of the present invention are presented for purposes of illustration and description. It is not intended to limit the invention to the precise form disclosed, and obviously many modifications and variations are possible in light of the above teaching. The exemplary embodiments were chosen and described in order to explain the specific principles of the invention and its practical application to thereby enable one skilled in the art to make and utilize the invention in various exemplary embodiments and with various modifications as are suited to the particular use contemplated. It is intended that the scope of the invention be defined by the claims and their equivalents.
Claims (10)
1. A chip test fixture for suppressing third harmonics, said fixture comprising: the device comprises a third harmonic suppression unit, a first transmission line, a second transmission line, a radio frequency input port, a radio frequency output port and a chip to be tested;
the radio frequency input port is connected with the first end of the first transmission line, the second end of the first transmission line is connected with the input end of the chip to be tested, the first end of the second transmission line is connected with the output end of the chip to be tested, the second end of the second transmission line is connected with the radio frequency output port, and the third harmonic suppression unit is connected with the input end of the chip to be tested or the output end of the chip to be tested.
2. The chip test fixture for suppressing third harmonics of claim 1, further comprising a feed unit, said feed unit comprising a first feed microstrip line, a first end of said first feed microstrip line connected to a first voltage source, and a second end of said first feed microstrip line connected to a feed port of a chip under test.
3. The third harmonic suppressing chip test fixture as in claim 1 wherein the third harmonic suppressing unit comprises a first harmonic suppressing module;
the first end of the first harmonic suppression module is open circuit, or the first end of the first harmonic suppression module is connected with a second voltage source;
the second end of the first harmonic suppression module is connected with the input end of the chip to be detected or the output end of the chip to be detected.
4. The third harmonic suppressing chip test fixture as in claim 1 wherein the third harmonic suppressing unit comprises a first harmonic suppressing module and a first capacitor;
the first end of the first harmonic suppression module is connected with the first end of the first capacitor, or the first end of the first harmonic suppression module is connected with the first end of the first capacitor and the second voltage source;
the second end of the first capacitor is connected with the ground potential, and the second end of the first harmonic suppression module is connected with the input end of the chip to be detected or the output end of the chip to be detected.
5. The third harmonic suppressing chip test fixture as in claim 1 wherein the third harmonic suppressing unit comprises a first harmonic suppressing module, a second harmonic suppressing module, a first capacitor and a switching unit;
the first end of the first harmonic suppression module is open or connected with a second voltage source;
the first end of the second harmonic suppression module is connected with the first end of the first capacitor, or the first end of the second harmonic suppression module is connected with the first end of the first capacitor and the second voltage source;
the first end of the switch unit is connected with the input end of the chip to be tested or the output end of the chip to be tested, the second end of the switch unit is connected with the second end of the first harmonic suppression module, the third end of the switch unit is connected with the second end of the second harmonic suppression module, and the switch unit is used for controlling the chip to be tested to be connected with the first harmonic suppression module or the second harmonic control module.
6. The third harmonic suppressing chip test fixture as in claim 3 wherein the first harmonic suppressing module comprises a first microstrip line having an electrical length θ 1 Satisfy 25 DEG < theta 1 ＜35°。
7. The third harmonic suppressing chip test fixture as in claim 4, wherein the first harmonic suppressing module comprises a first microstrip line having an electrical length θ 1 Satisfy 55 DEG < theta 2 ＜65°。
8. The third harmonic suppressing chip test fixture as in claim 5, wherein the first harmonic suppression module comprises a first microstrip line having an electrical length θ 1 Satisfy 25 DEG < theta 1 Less than 35 DEG; the second harmonic suppression module comprises a second microstrip line with an electrical length theta 2 Satisfy 55 DEG < theta 2 ＜65°。
9. The die test fixture for suppressing third harmonics of claim 1, further comprising an inductive element, said inductive element having a first end connected to a second voltage source and a second end connected to a third harmonic suppression element.
10. The die test fixture for suppressing third harmonics of claim 1, wherein said die test fixture comprises a circuit board for holding a third harmonic suppression unit, a first transmission line, a second transmission line, a radio frequency input port, and a radio frequency output port, said circuit board having a center for holding a die under test.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311763323.1A CN117741197A (en) | 2023-12-20 | 2023-12-20 | Chip test fixture for inhibiting third harmonic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311763323.1A CN117741197A (en) | 2023-12-20 | 2023-12-20 | Chip test fixture for inhibiting third harmonic |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN117741197A true CN117741197A (en) | 2024-03-22 |
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ID=90254174
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311763323.1A Pending CN117741197A (en) | 2023-12-20 | 2023-12-20 | Chip test fixture for inhibiting third harmonic |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117741197A (en) |
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2023
- 2023-12-20 CN CN202311763323.1A patent/CN117741197A/en active Pending
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