CN117729308A - Multipath high-definition video real-time monitoring and distributing system - Google Patents
Multipath high-definition video real-time monitoring and distributing system Download PDFInfo
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- CN117729308A CN117729308A CN202311464721.3A CN202311464721A CN117729308A CN 117729308 A CN117729308 A CN 117729308A CN 202311464721 A CN202311464721 A CN 202311464721A CN 117729308 A CN117729308 A CN 117729308A
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Abstract
The invention discloses a multipath high-definition video real-time monitoring and distributing system, which comprises a video transmitting end, a video receiving end and a video monitoring and distributing end; the video transmitting end is responsible for collecting camera video signals and completing format conversion, and transmitting the video signals through the optical module; the video receiving end is responsible for receiving video signals through the optical module and driving the display equipment; the video monitoring and distributing end comprises a photoelectric conversion module, a video image encoder, an FPGA, a video image encoder, a 16 multiplied by 16 exchanger and an electro-optical conversion module; the invention adopts the 16X 16 exchanger to support the interconnection of the multipath high-definition video and the multiple display devices, can realize the distribution and output of any path of interested high-definition signals to any one interested display device, has the function of monitoring the multipath high-definition video signals and the 16X 16 exchanger loop-back signals in real time through the FPGA, and can rapidly diagnose the video image faults under the condition that the system is not powered off.
Description
Technical Field
The invention belongs to the technical field of video image signal processing, and particularly relates to a multipath high-definition video real-time monitoring and distributing system.
Background
Video images play an increasingly important role in fields such as industrial vision, security monitoring, military equipment, and the like. The demands for executing tasks such as environment sensing, situation generation, associated object state judgment, identity estimation and the like in a plurality of concerned areas are increasing, and a plurality of paths of high-definition cameras are required to be deployed in a distributed manner. The video links may differ from one scene to another, and the number and location of camera and display device deployments may also differ.
When the number of users is increased, a reliable multi-channel high-definition video sharing method is needed, videos can be monitored in real time, users are reminded in time, the cost of the system and the consumption of link investigation time are reduced, and timeliness and reliability are guaranteed.
Disclosure of Invention
In view of the above, the invention provides a real-time monitoring and distributing system for multi-channel high-definition videos, which can timely share the multi-channel videos and timely monitor the videos to remind users.
The technical scheme for realizing the invention is as follows:
a multipath high-definition video real-time monitoring and distributing system comprises a video transmitting end, a video receiving end and a video monitoring and distributing end; wherein,
the video transmitting end acquires video signals corresponding to the video sources and transmits the video signals to the video monitoring and distributing end; the number of the video sources is N, each video transmitting end corresponds to one video source, and one path of video signal is generated;
the video monitoring and distributing end performs format conversion on the N paths of video signals sent by the video sending end, and outputs the video signals and/or preset fault image codes to the video receiving end according to the monitoring result;
the video receiving end comprises a plurality of display devices, the video receiving end receives video signals and/or preset fault image codes output by the video monitoring and distributing end and drives the video monitoring and distributing end to display corresponding video signals and/or preset fault image codes on the selected display devices, and the number of the display devices is M, and each display device corresponds to one video source.
Further, the video monitoring and distributing end comprises a photoelectric conversion module, a video image encoder, an FPGA, a video image decoder, a 16 multiplied by 16 exchanger and an electro-optical conversion module;
the photoelectric conversion module converts the N paths of video signals into serial differential video signals and sends the serial differential video signals to the video image decoder;
the video image decoders are used for converting the serial differential video signals into parallel video data and sending the parallel video data to the FPGA, wherein the number of the video image decoders is N, and the first video image decoder to the N video image decoder are all connected with the photoelectric conversion module;
the FPGA is used for receiving N paths of parallel video data generated by the video image decoder, analyzing each path of video data, and counting video attributes of each path of video data in real time, wherein the video attributes comprise a clock effective counter counting result, a pixel counter counting result, a line counter counting result and a frame frequency counter counting result, and comparing the counting result with attributes of video sources corresponding to each path of video data in real time; if the comparison result of a certain path is inconsistent, the video data received by the path has faults, and a preset fault image code is output to a video image encoder corresponding to the path; otherwise, the video data received by the path is coded and output by the video image coder corresponding to the path;
the number of the video image encoders is N, each video image encoder corresponds to one video image decoder and is used for converting video data or preset images from the FPGA into video signals or image signals, and serial differential signals formed by the N video image encoders are sent to the 16X 16 exchanger;
the 16×16 switch supports 16 channel signal input and 16 channel signal output, and the maximum rate supported by each channel is 3.125Gbps, and is used for selecting corresponding display devices according to the output of the first video image encoder to the nth video image encoder by the I2C control bus, and sending the output of the first video image encoder to the nth video image encoder to the electro-optical conversion module to generate serial differential signals; the serial differential signals are sequentially looped back and output to a video image decoder LB according to a preset period;
the video image decoder LB is used for being connected with the output of the 16X 16 exchanger to finish video signal loop monitoring; if the video signal received by the video image decoder LB has a fault, the fault is required to be output through other communication modes;
the electro-optical conversion module is used for converting the serial differential signals of the 16×16 exchanger into optical signals and transmitting the optical signals through optical fibers.
The clock effective counter is used for carrying out effectiveness detection count statistics on clock signals of all paths of video data according to the local clock signals of the FPGA;
the pixel counter is used for counting and counting the pixel points row by row according to the row synchronous effective signals of each path of video data according to the rising edge of the video image clock of each path of video data;
the line counter is used for counting the number of lines of field synchronous effective signals of each path of video data under the control of the FPGA;
the frame frequency counter is used for counting rising edge times within 1 second for the rising edges of the field synchronous effective signals of all paths of video data under the control of the FPGA;
the preset fault pattern codes comprise four fault diagnosis type codes of invalid clocks, horizontal resolution disagreement, vertical resolution disagreement and frame frequency disagreement.
Further, the parallel video data is 28-32-bit video data.
Further, the FPGA is an XC7K325T chip.
Further, the clock valid counter, the pixel counter, the line counter and the frame frequency counter are used as a logic control module of the FPGA.
The beneficial effects are that:
compared with the prior art, the invention has the following beneficial effects:
(1) The high-definition video of any channel can be distributed and output to any display equipment;
(2) Different display devices can view high-definition videos of the same channel at the same time;
(3) The system has the functions of real-time monitoring of input video signals and loop video signals, accurate and quick fault positioning, no power failure, simple graphic coding and less memory burden.
Drawings
Fig. 1 is a schematic diagram of a multi-channel high definition video real-time monitoring and distributing system architecture according to the present invention.
Detailed Description
The invention will now be described in detail by way of example with reference to the accompanying drawings.
As shown in fig. 1, the invention provides a multi-channel high-definition video real-time monitoring and distributing system, which comprises a video transmitting end, a video receiving end and a video monitoring and distributing end; wherein,
the video transmitting end acquires video signals corresponding to the video sources and transmits the video signals to the video monitoring and distributing end; the number of the video sources is N, each video transmitting end corresponds to one video source, and one path of video signal is generated;
the video monitoring and distributing end performs format conversion on the N paths of video signals sent by the video sending end, and outputs the video signals and/or preset fault image codes to the video receiving end according to the monitoring result;
the video receiving end comprises a plurality of display devices, the video receiving end receives video signals and/or preset fault image codes output by the video monitoring and distributing end and drives the video monitoring and distributing end to display corresponding video signals and/or preset fault image codes on the selected display devices, and the number of the display devices is M, and each display device corresponds to one video source.
Further, the video monitoring and distributing end comprises a photoelectric conversion module, a video image encoder, an FPGA, a video image decoder, a 16 multiplied by 16 exchanger and an electro-optical conversion module;
the photoelectric conversion module converts the N paths of video signals into serial differential video signals and sends the serial differential video signals to the video image decoder;
the video image decoders are used for converting the serial differential video signals into parallel video data and sending the parallel video data to the FPGA, wherein the number of the video image decoders is N, and the first video image decoder to the N video image decoder are all connected with the photoelectric conversion module;
the FPGA is used for receiving N paths of parallel video data generated by the video image decoder, analyzing each path of video data, and counting video attributes of each path of video data in real time, wherein the video attributes comprise a clock effective counter counting result, a pixel counter counting result, a line counter counting result and a frame frequency counter counting result, and comparing the counting result with attributes of video sources corresponding to each path of video data in real time; if the comparison result of a certain path is inconsistent, the video data received by the path has faults, and a preset fault image code is output to a video image encoder corresponding to the path; otherwise, the video data received by the path is coded and output by the video image coder corresponding to the path;
the number of the video image encoders is N, each video image encoder corresponds to one video image decoder and is used for converting video data or preset images from the FPGA into video signals or image signals, and serial differential signals formed by the N video image encoders are sent to the 16X 16 exchanger;
the 16×16 switch supports 16 channel signal input and 16 channel signal output, and the maximum rate supported by each channel is 3.125Gbps, and is used for selecting corresponding display devices according to the output of the first video image encoder to the nth video image encoder by the I2C control bus, and sending the output of the first video image encoder to the nth video image encoder to the electro-optical conversion module to generate serial differential signals; the serial differential signals are sequentially looped back and output to a video image decoder LB according to a preset period;
the video image decoder LB is used for being connected with the output of the 16X 16 exchanger to finish video signal loop monitoring; if the video signal received by the video image decoder LB has a fault, the fault is required to be output through other communication modes;
the electro-optical conversion module is used for converting the serial differential signals of the 16×16 exchanger into optical signals and transmitting the optical signals through optical fibers.
In this embodiment, any path of video distribution output to any interested display device can be realized, and the video source and the display device are not fixedly bound in advance.
The clock effective counter is used for carrying out effectiveness detection count statistics on clock signals of all paths of video data according to the local clock signals of the FPGA;
the pixel counter is used for counting and counting the pixel points row by row according to the row synchronous effective signals of each path of video data according to the rising edge of the video image clock of each path of video data;
the line counter is used for counting the number of lines of field synchronous effective signals of each path of video data under the control of the FPGA;
the frame frequency counter is used for counting rising edge times within 1 second for the rising edges of the field synchronous effective signals of all paths of video data under the control of the FPGA;
the preset fault graphic codes comprise four fault diagnosis type codes of invalid clocks, horizontal resolution disagreement, vertical resolution disagreement and frame frequency disagreement;
further, the parallel video data is 28-32-bit video data.
Further, the FPGA is an XC7K325T chip.
Further, the clock valid counter, the pixel counter, the line counter and the frame frequency counter are used as a logic control module of the FPGA.
The invention adopts the 16X 16 exchanger to support the interconnection of the multipath high-definition video and the multiple display devices, can realize the distribution and output of any path of interested high-definition signals to any one interested display device, has the function of monitoring the multipath high-definition video signals and the 16X 16 exchanger loop-back signals in real time through the FPGA, and can rapidly diagnose the video image faults under the condition that the system is not powered off.
In summary, the above embodiments are only preferred embodiments of the present invention, and are not intended to limit the scope of the present invention. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (6)
1. The multichannel high-definition video real-time monitoring and distributing system is characterized by comprising a video sending end, a video receiving end and a video monitoring and distributing end; wherein:
the video transmitting end acquires video signals corresponding to the video sources and transmits the video signals to the video monitoring and distributing end; the number of the video sources is N, each video transmitting end corresponds to one video source, and one path of video signal is generated;
the video monitoring and distributing end performs format conversion on the N paths of video signals sent by the video sending end, and outputs the video signals and/or preset fault image codes to the video receiving end according to the monitoring result;
the video receiving end comprises a plurality of display devices, the video receiving end receives video signals and/or preset fault image codes output by the video monitoring and distributing end and drives the video monitoring and distributing end to display corresponding video signals and/or preset fault image codes on the selected display devices, and the number of the display devices is M, and each display device corresponds to one video source.
2. The system of claim 1, wherein the video monitoring and distribution terminal comprises a photoelectric conversion module, a video image encoder, an FPGA, a video image decoder, a 16 x 16 switch, an electro-optic conversion module;
the photoelectric conversion module converts the N paths of video signals into serial differential video signals and sends the serial differential video signals to the video image decoder;
the video image decoders are used for converting the serial differential video signals into parallel video data and sending the parallel video data to the FPGA, wherein the number of the video image decoders is N, and the first video image decoder to the N video image decoder are all connected with the photoelectric conversion module;
the FPGA is used for receiving N paths of parallel video data generated by the video image decoder, analyzing each path of video data, and counting video attributes of each path of video data in real time, wherein the video attributes comprise a clock effective counter counting result, a pixel counter counting result, a line counter counting result and a frame frequency counter counting result, and comparing the counting result with attributes of video sources corresponding to each path of video data in real time; if the comparison result of a certain path is inconsistent, the video data received by the path has faults, and a preset fault image code is output to a video image encoder corresponding to the path; otherwise, the video data received by the path is coded and output by the video image coder corresponding to the path;
the number of the video image encoders is N, each video image encoder corresponds to one video image decoder and is used for converting video data or preset images from the FPGA into video signals or image signals, and serial differential signals formed by the N video image encoders are sent to the 16X 16 exchanger;
the 16×16 switch supports 16 channel signal input and 16 channel signal output, and the maximum rate supported by each channel is 3.125Gbps, and is used for selecting corresponding display devices according to the output of the first video image encoder to the nth video image encoder by the I2C control bus, and sending the output of the first video image encoder to the nth video image encoder to the electro-optical conversion module to generate serial differential signals; the serial differential signals are sequentially looped back and output to a video image decoder LB according to a preset period;
the video image decoder LB is used for being connected with the output of the 16X 16 exchanger to finish video signal loop monitoring; if the video signal received by the video image decoder LB has a fault, the fault is required to be output through other communication modes;
the electro-optical conversion module is used for converting the serial differential signals of the 16×16 exchanger into optical signals and transmitting the optical signals through optical fibers.
3. The system of claim 2, wherein the clock valid counter is configured to perform validity detection count statistics on clock signals of each path of video data according to an FPGA local clock signal;
the pixel counter is used for counting and counting the pixel points row by row according to the row synchronous effective signals of each path of video data according to the rising edge of the video image clock of each path of video data;
the line counter is used for counting the number of lines of field synchronous effective signals of each path of video data under the control of the FPGA;
the frame frequency counter is used for counting rising edge times within 1 second for the rising edges of the field synchronous effective signals of all paths of video data under the control of the FPGA;
the preset fault pattern codes comprise four fault diagnosis type codes of invalid clocks, horizontal resolution disagreement, vertical resolution disagreement and frame frequency disagreement.
4. A system according to any one of claims 2-3, wherein the parallel video data is 28-32 bits of video data.
5. A system according to any of claims 2-3, wherein the FPGA is an XC7K325T chip.
6. A system according to any of claims 2-3, characterized in that said clock valid counter, pixel counter, line counter, frame rate counter are used as a logic control module of said FPGA.
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| CN202311464721.3A CN117729308A (en) | 2023-11-06 | 2023-11-06 | Multipath high-definition video real-time monitoring and distributing system |
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| CN202311464721.3A CN117729308A (en) | 2023-11-06 | 2023-11-06 | Multipath high-definition video real-time monitoring and distributing system |
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